diff options
| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2021-02-04 08:21:35 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-02-18 16:43:11 -0500 |
| commit | 0b7421f0a6a41a8ce60c4dadf6f9e7c62fbd2f1f (patch) | |
| tree | f9646863d791237c54eb7d324320c70c8fb3ec27 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | ea1b8c9b837c18e2322d1b91ac3c1af8a4f7a455 (diff) | |
drm/amd/display: Old sequence for HUBP blank
New proposed sequence for HUBP blanking causes regressions where the
hardware would fail to enter blank which triggers an assert in the new
sequence. This change brings back the old sequence.
Fixes: 985faf2c4ecb60 ("drm/amd/display: New sequence for HUBP blank")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index b79a17f6a9cc..48d1e0e2cf75 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1576,7 +1576,7 @@ static void dcn20_update_dchubp_dpp( if (pipe_ctx->update_flags.bits.enable) - dc->hwss.set_hubp_blank(dc, pipe_ctx, false); + hubp->funcs->set_blank(hubp, false); } @@ -1772,10 +1772,19 @@ void dcn20_post_unlock_program_front_end( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *mpcc_pipe; if (pipe->vtp_locked) { - dc->hwss.set_hubp_blank(dc, pipe, true); + dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp); + pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true); pipe->vtp_locked = false; + + for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) + mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); + + for (i = 0; i < dc->res_pool->pipe_count; i++) + if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) + dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); } } /* WA to apply WM setting*/ |