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authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>2019-07-19 11:43:39 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-08-15 10:55:23 -0500
commit2b162fd3024997b97c95290b0a8ed08d914f115d (patch)
treec2ed9dbd8eddf3bb90d8f23d7940e9edf58bea42 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
parent1071a0ecf4a6a1fb7c98bf8351ebf414265cb780 (diff)
drm/amd/display: update optc odm interface for more than 2 opps
Current optc odm interface only accepts 2 opps, we need to expand this to allow 4 to 1 odm combine. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c22
1 files changed, 13 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index c3635f5cd990..5904d4d329df 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -545,12 +545,14 @@ enum dc_status dcn20_enable_stream_timing(
/* TODO check if timing_changed, disable stream if timing changed */
- if (odm_pipe)
+ if (odm_pipe) {
+ int opp_inst[2] = { pipe_ctx->stream_res.opp->inst, odm_pipe->stream_res.opp->inst };
+
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
- odm_pipe->stream_res.opp->inst,
- pipe_ctx->stream->timing.h_addressable/2,
- pipe_ctx->stream->timing.pixel_encoding);
+ opp_inst, 2,
+ &pipe_ctx->stream->timing);
+ }
/* HW program guide assume display already disable
* by unplug sequence. OTG assume stop.
*/
@@ -822,13 +824,15 @@ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pip
{
struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
- if (combine_pipe)
+ if (combine_pipe) {
+ int opp_inst[2] = { pipe_ctx->stream_res.opp->inst,
+ combine_pipe->stream_res.opp->inst };
+
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
- combine_pipe->stream_res.opp->inst,
- pipe_ctx->plane_res.scl_data.h_active,
- pipe_ctx->stream->timing.pixel_encoding);
- else
+ opp_inst, 2,
+ &pipe_ctx->stream->timing);
+ } else
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
}