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authorIlya Bakoulin <Ilya.Bakoulin@amd.com>2019-06-26 14:52:46 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 14:27:25 -0500
commit473e0ecbb4f62e0a971b47b27ec778371653f5ac (patch)
treead986acf57106ad945cdae4c6cff4fa6b33e3e21 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
parent8bee5c5c7e9ed478272bcd1288a425b5a101b376 (diff)
drm/amd/display: Fixes for some MPO cases
[Why] Alpha could be improperly applied (only affecting half the frame) for some source pixel formats. [How] Change how alpha is enabled in MPC/DPP LB and change the bottom plane blend mode in MPC. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 64ebfdbbba9b..566cd4cdfef4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1863,7 +1863,7 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct mpcc_blnd_cfg blnd_cfg = { {0} };
- bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
+ bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
int mpcc_id;
struct mpcc *new_mpcc;
struct mpc *mpc = dc->res_pool->mpc;