diff options
| author | Charlene Liu <charlene.liu@amd.com> | 2019-07-24 18:14:46 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 10:56:19 -0500 |
| commit | 544618596fd58848f5f881e265a09320e91f2e97 (patch) | |
| tree | c2e5bade09b480f1ad77f5d43d307b149d4ededa /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | 1bb32e5a872daa8f918b73d4476862c5651d45bf (diff) | |
drm/amd/display: wake up ogam mem pwr before programming ocsc
[Description]
OGAM_MEM_PWR could stay in light up when driver woke up to update gamma.
either disable MEM_LOW power feature or set to OGAM_bypass could make artificial color distortion goes away.
Easy reproduce after LOW_MEM Power feature enables and resume from S3.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Julian Parkin <jparkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 5904d4d329df..4e9ac051d3d8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -631,6 +631,10 @@ void dcn20_program_output_csc(struct dc *dc, { struct mpc *mpc = dc->res_pool->mpc; enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (mpc->funcs->power_on_mpc_mem_pwr) + mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { if (mpc->funcs->set_output_csc != NULL) @@ -660,6 +664,8 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx, * if programming for all pipes is required then remove condition * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. */ + if (mpc->funcs->power_on_mpc_mem_pwr) + mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx)) && mpc->funcs->set_output_gamma && stream->out_transfer_func) { if (stream->out_transfer_func->type == TF_TYPE_HWPWL) |