diff options
| author | Charlene Liu <charlene.liu@amd.com> | 2019-07-29 11:59:33 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 10:57:18 -0500 |
| commit | 79e005204f75b54db9e42a39b3f66fac2ba190b9 (patch) | |
| tree | a59bf999c665438fa47213389d005afff56690f2 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | 8d966bdd48385d3ebdecfc25f195db034061e94f (diff) | |
drm/amd/display: enable dcn_mem_pwr as golden setting updates
Enable dcn_mem_pwr as golden setting updates
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 4e9ac051d3d8..fa8a73f6c8e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -142,8 +142,7 @@ void dcn20_display_init(struct dc *dc) /* DCCG */ dcn20_dccg_init(hws); - /* Disable all memory low power mode. All memories are enabled. */ - REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); + REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0); /* DCHUB/MMHUBBUB * set global timer refclk divider |