diff options
| author | Ilya Bakoulin <Ilya.Bakoulin@amd.com> | 2019-04-09 11:50:38 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:10 -0500 |
| commit | fbc9ca671f4ffbc0c873de17cf2305ca438cb09e (patch) | |
| tree | 5ecb5a259a0835afca9af67e9dfa8a8fbdad71f9 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | 2a874fa0257ac834142e0570a2bec629421ee031 (diff) | |
drm/amd/display: Fix ODM combine data format
[Why]
OPTC data format was left at its default value (444) when enabling
ODM combine. This caused issues with FPGA capture.
[How]
Write the OPTC_DATA_FORMAT field when enabling ODM combine.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index fbcb4d860e7a..2ea72e965c1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -703,7 +703,8 @@ enum dc_status dcn20_enable_stream_timing( pipe_ctx->stream_res.tg->funcs->set_odm_combine( pipe_ctx->stream_res.tg, odm_pipe->stream_res.opp->inst, - pipe_ctx->stream->timing.h_addressable/2); + pipe_ctx->stream->timing.h_addressable/2, + pipe_ctx->stream->timing.pixel_encoding); /* HW program guide assume display already disable * by unplug sequence. OTG assume stop. */ @@ -1007,7 +1008,8 @@ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pip pipe_ctx->stream_res.tg->funcs->set_odm_combine( pipe_ctx->stream_res.tg, combine_pipe->stream_res.opp->inst, - pipe_ctx->plane_res.scl_data.h_active); + pipe_ctx->plane_res.scl_data.h_active, + pipe_ctx->stream->timing.pixel_encoding); else pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); |