diff options
| author | Daniel Miess <daniel.miess@amd.com> | 2023-10-12 12:55:47 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-17 09:30:50 -0500 |
| commit | 5f70d4ff8095a2ad362d2a00eb8d9f7e20f3daa1 (patch) | |
| tree | e48451c935e8802f2b0f55ed8858ff17de71a7ab /drivers/gpu/drm/amd/display/dc/dcn20 | |
| parent | 673d6d73eba79a1205ac403b68ef63da1c823da2 (diff) | |
drm/amd/display: Enable DCN clock gating for DCN35
[WHY & HOW]
Enable DCN clock gating for DCN35.
Disable DTBCLK gate before link training
and re-enable afterwards
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index ab6d09c6fe34..76da59d8caaf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -291,7 +291,11 @@ type SYMCLKB_FE_SRC_SEL;\ type SYMCLKC_FE_SRC_SEL;\ type SYMCLKD_FE_SRC_SEL;\ - type SYMCLKE_FE_SRC_SEL; + type SYMCLKE_FE_SRC_SEL;\ + type DTBCLK_P0_GATE_DISABLE;\ + type DTBCLK_P1_GATE_DISABLE;\ + type DTBCLK_P2_GATE_DISABLE;\ + type DTBCLK_P3_GATE_DISABLE;\ struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) |