diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-05-15 09:43:42 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-05-15 09:43:42 -0700 |
| commit | db5d28c0bfe566908719bec8e25443aabecbb802 (patch) | |
| tree | c113e307ba7a5964ff174f590cd58bce07e2e4ee /drivers/gpu/drm/amd/display/dc/dcn20 | |
| parent | 46c6d2b186915176be5acc5d4b6f9793eb32a0c7 (diff) | |
| parent | 275654c02f0ba09d409c36d71dc238e470741e30 (diff) | |
Merge tag 'drm-next-2024-05-15' of https://gitlab.freedesktop.org/drm/kernel
Pull drm updates from Dave Airlie:
"This is the main pull request for the drm subsystems for 6.10.
In drivers the main thing is a new driver for ARM Mali firmware based
GPUs, otherwise there are a lot of changes to amdgpu/xe/i915/msm and
scattered changes to everything else.
In the core a bunch of headers and Kconfig was refactored, along with
the addition of a new panic handler which is meant to provide a user
friendly message when a panic happens and graphical display is
enabled.
New drivers:
- panthor: ARM Mali/Immortalis CSF-based GPU driver
Core:
- add a CONFIG_DRM_WERROR option
- make more headers self-contained
- grab resv lock in pin/unpin
- fix vmap resv locking
- EDID/eDP panel matching
- Kconfig cleanups
- DT sound bindings
- Add SIZE_HINTS property for cursor planes
- Add struct drm_edid_product_id and helpers.
- Use drm device based logging in more drm functions.
- drop seq_file.h from a bunch of places
- use drm_edid driver conversions
dp:
- DP Tunnel documentation
- MST read sideband cap
- Adaptive sync SDP prep work
ttm:
- improve placement for TTM BOs in idle/busy handling
panic:
- Fixes for drm-panic, and option to test it.
- Add drm panic to simpledrm, mgag200, imx, ast
bridge:
- improve init ordering
- adv7511: allow GPIO pin sharing
- tc358775: add tc358675 support
panel:
- AUO B120XAN01.0
- Samsung s6e3fa7
- BOE NT116WHM-N44
- CMN N116BCA-EA1,
- CrystalClear CMT430B19N00
- Startek KD050HDFIA020-C020A
- powertip PH128800T006-ZHC01
- Innolux G121X1-L03
- LG sw43408
- Khadas TS050 V2
- EDO RM69380 OLED
- CSOT MNB601LS1-1
amdgpu:
- HDCP/ODM/RAS fixes
- Devcoredump improvements
- Expose VCN activity via sysfs
- SMY 13.0.x updates
- Enable fast updates on DCN 3.1.4
- Add dclk and vclk reporting on additional devices
- Add ACA RAS infrastructure
- Implement TLB flush fence
- EEPROM handling fixes
- SMUIO 14.0.2 support
- SMU 14.0.1 Updates
- SMU 14.0.2 support
- Sync page table freeing with TLB flushes
- DML2 refactor
- DC debug improvements
- DCN 3.5.x Updates
- GPU reset fixes
- HDP fix for second GFX pipe on GC 10.x
- Enable secondary GFX pipe on GC 10.3
- Refactor and clean up BACO/BOCO/BAMACO handling
- Remove invalid TTM resource start check
- UAF fix in VA IOCTL
- GPUVM page fault redirection to secondary IH rings for IH 6.x
- Initial support for mapping kernel queues via MES
- Fix VRAM memory accounting
amdkfd:
- MQD handling cleanup
- Preemption handling fixes for XCDs
- TLB flush fix for GC 9.4.2
- Properly clean up workqueue during module unload
- Fix memory leak process create failure
- Range check CP bad op exception targets to avoid reporting invalid exceptions to userspace
- Fix eviction fence handling
- Fix leak in GPU memory allocation failure case
- DMABuf import handling fix
- Enable SQ watchpoint for gfx10
i915:
- Adding new DG2 PCI ID
- add context hints for GT frequency
- enable only one CCS for compute workloads
- new workarounds
- Fix UAF on destroy against retire race and remove two earlier partial fixes
- Limit the reserved VM space to only the platforms that need it
- Fix gt reset with GuC submission is disable
- Add and use gt_to_guc() wrapper
i915/xe display:
- Lunar Lake display enabling, including cdclk and other refactors
- BIOS/VBT/opregion related refactor
- Digital port related refactor/clean-up
- Fix 2s boot time regression on DP panel replay init
- Remove duplication on audio enable/disable on SDVO and g4x+ DP
- Disable AuxCCS framebuffers if built for Xe
- Make crtc disable more atomic
- Increase DP idle pattern wait timeout to 2ms
- Start using container_of_const() for some extra const safety
- Fix Jasper Lake boot freeze
- Enable MST mode for 128b/132b single-stream sideband
- Enable Adaptive Sync SDP Support for DP
- Fix MTL supported DP rates - removal of UHBR13.5
- PLL refactoring
- Limit eDP MSO pipe only for display version 20
- More display refactor towards independence from i915 dev_priv
- Convert i915/xe fbdev to DRM client
- More initial work to make display code more independent from i915
xe:
- improved error capture
- clean up some uAPI leftovers
- devcoredump update
- Add BMG mocs table
- Handle GSCCS ER interrupt
- Implement xe2- and GuC workarounds
- struct xe_device cleanup
- Hwmon updates
- Add LRC parsing for more GPU instruction
- Increase VM_BIND number of per-ioctl Ops
- drm/xe: Add XE_BO_GGTT_INVALIDATE flag
- Initial development for SR-IOV support
- Add new PCI IDs to DG2 platform
- Move userptr over to start using hmm_range_fault
msm:
- Switched to generating register header files during build process
instead of shipping pre-generated headers
- Merged DPU and MDP4 format databases.
- DP:
- Stop using compat string to distinguish DP and eDP cases
- Added support for X Elite platform (X1E80100)
- Reworked DP aux/audio support
- Added SM6350 DP to the bindings
- GPU:
- a7xx perfcntr reg fixes
- MAINTAINERS updates
- a750 devcoredump support
radeon:
- Silence UBSAN warnings related to flexible arrays
nouveau:
- move some uAPI objects to uapi headers
omapdrm:
- console fix
ast:
- add i2c polling
qaic:
- add debugfs entries
exynos:
- fix platform_driver .owner
- drop cleanup code
mediatek:
- Use devm_platform_get_and_ioremap_resource() in mtk_hdmi_ddc_probe()
- Add GAMMA 12-bit LUT support for MT8188
- Rename mtk_drm_* to mtk_*
- Drop driver owner initialization
- Correct calculation formula of PHY Timing"
* tag 'drm-next-2024-05-15' of https://gitlab.freedesktop.org/drm/kernel: (1477 commits)
drm/xe/ads: Use flexible-array
drm/xe: Use ordered WQ for G2H handler
drm/msm/gen_header: allow skipping the validation
drm/msm/a6xx: Cleanup indexed regs const'ness
drm/msm: Add devcoredump support for a750
drm/msm: Adjust a7xx GBIF debugbus dumping
drm/msm: Update a6xx registers XML
drm/msm: Fix imported a750 snapshot header for upstream
drm/msm: Import a750 snapshot registers from kgsl
MAINTAINERS: Add Konrad Dybcio as a reviewer for the Adreno driver
MAINTAINERS: Add a separate entry for Qualcomm Adreno GPU drivers
drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting fails
drm/msm/adreno: fix CP cycles stat retrieval on a7xx
drm/msm/a7xx: allow writing to CP_BV counter selection registers
drm: zynqmp_dpsub: Always register bridge
Revert "drm/bridge: ti-sn65dsi83: Fix enable error path"
drm/fb_dma: Add checks in drm_fb_dma_get_scanout_buffer()
drm/fbdev-generic: Do not set physical framebuffer address
drm/panthor: Fix the FW reset logic
drm/panthor: Make sure we handle 'unknown group state' case properly
...
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 435 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 781 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 1202 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 |
11 files changed, 29 insertions, 2429 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile index 3dae3943b056..9b6070c99794 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile @@ -2,7 +2,7 @@ # # Makefile for DCN. -DCN20 = dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \ +DCN20 = dcn20_hubp.o \ dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_mmhubbub.o \ dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \ dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c deleted file mode 100644 index 1516c0a48726..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "core_types.h" - -#include "reg_helper.h" -#include "dcn20_dpp.h" -#include "basics/conversion.h" - -#define NUM_PHASES 64 -#define HORZ_MAX_TAPS 8 -#define VERT_MAX_TAPS 8 - -#define BLACK_OFFSET_RGB_Y 0x0 -#define BLACK_OFFSET_CBCR 0x8000 - -#define REG(reg)\ - dpp->tf_regs->reg - -#define CTX \ - dpp->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - dpp->tf_shift->field_name, dpp->tf_mask->field_name - -void dpp20_read_state(struct dpp *dpp_base, - struct dcn_dpp_state *s) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(DPP_CONTROL, - DPP_CLOCK_ENABLE, &s->is_enabled); - - // Degamma LUT (RAM) - REG_GET(CM_DGAM_CONTROL, - CM_DGAM_LUT_MODE, &s->dgam_lut_mode); - - // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) - REG_GET(CM_SHAPER_CONTROL, - CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); - REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL, - CM_3DLUT_CONFIG_STATUS, &s->lut3d_mode, - CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); - REG_GET(CM_3DLUT_MODE, - CM_3DLUT_SIZE, &s->lut3d_size); - - // Blend/Out Gamma (RAM) - REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, - CM_BLNDGAM_CONFIG_STATUS, &s->rgam_lut_mode); -} - -void dpp2_power_on_obuf( - struct dpp *dpp_base, - bool power_on) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); - - REG_UPDATE(OBUF_MEM_PWR_CTRL, - OBUF_MEM_PWR_FORCE, power_on == true ? 0:1); - - REG_UPDATE(DSCL_MEM_PWR_CTRL, - LUT_MEM_PWR_FORCE, power_on == true ? 0:1); -} - -void dpp2_dummy_program_input_lut( - struct dpp *dpp_base, - const struct dc_gamma *gamma) -{} - -static void dpp2_cnv_setup ( - struct dpp *dpp_base, - enum surface_pixel_format format, - enum expansion_mode mode, - struct dc_csc_transform input_csc_color_matrix, - enum dc_color_space input_color_space, - struct cnv_alpha_2bit_lut *alpha_2bit_lut) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - uint32_t pixel_format = 0; - uint32_t alpha_en = 1; - enum dc_color_space color_space = COLOR_SPACE_SRGB; - enum dcn20_input_csc_select select = DCN2_ICSC_SELECT_BYPASS; - bool force_disable_cursor = false; - struct out_csc_color_matrix tbl_entry; - uint32_t is_2bit = 0; - int i = 0; - - REG_SET_2(FORMAT_CONTROL, 0, - CNVC_BYPASS, 0, - FORMAT_EXPANSION_MODE, mode); - - //hardcode default - //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14 - //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled - //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled - //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled - REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); - REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); - REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); - REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); - - switch (format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - pixel_format = 1; - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - pixel_format = 3; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - pixel_format = 8; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - pixel_format = 10; - is_2bit = 1; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: - force_disable_cursor = false; - pixel_format = 65; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: - force_disable_cursor = true; - pixel_format = 64; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: - force_disable_cursor = true; - pixel_format = 67; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: - force_disable_cursor = true; - pixel_format = 66; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: - pixel_format = 26; /* ARGB16161616_UNORM */ - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - pixel_format = 24; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: - pixel_format = 25; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: - pixel_format = 12; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: - pixel_format = 112; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: - pixel_format = 113; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: - pixel_format = 114; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - is_2bit = 1; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: - pixel_format = 115; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - is_2bit = 1; - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: - pixel_format = 118; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: - pixel_format = 119; - alpha_en = 0; - break; - default: - break; - } - - /* Set default color space based on format if none is given. */ - color_space = input_color_space ? input_color_space : color_space; - - if (is_2bit == 1 && alpha_2bit_lut != NULL) { - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); - } - - REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, - CNVC_SURFACE_PIXEL_FORMAT, pixel_format); - REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); - - // if input adjustments exist, program icsc with those values - if (input_csc_color_matrix.enable_adjustment - == true) { - for (i = 0; i < 12; i++) - tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; - - tbl_entry.color_space = input_color_space; - - if (color_space >= COLOR_SPACE_YCBCR601) - select = DCN2_ICSC_SELECT_ICSC_A; - else - select = DCN2_ICSC_SELECT_BYPASS; - - dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); - } else - dpp2_program_input_csc(dpp_base, color_space, select, NULL); - - if (force_disable_cursor) { - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, 0); - REG_UPDATE(CURSOR0_CONTROL, - CUR0_ENABLE, 0); - - } - dpp2_power_on_obuf(dpp_base, true); - -} - -/*compute the maximum number of lines that we can fit in the line buffer*/ -void dscl2_calc_lb_num_partitions( - const struct scaler_data *scl_data, - enum lb_memory_config lb_config, - int *num_part_y, - int *num_part_c) -{ - int memory_line_size_y, memory_line_size_c, memory_line_size_a, - lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a; - - int line_size = scl_data->viewport.width < scl_data->recout.width ? - scl_data->viewport.width : scl_data->recout.width; - int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? - scl_data->viewport_c.width : scl_data->recout.width; - - if (line_size == 0) - line_size = 1; - - if (line_size_c == 0) - line_size_c = 1; - - memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ - memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ - memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ - - if (lb_config == LB_MEMORY_CONFIG_1) { - lb_memory_size = 970; - lb_memory_size_c = 970; - lb_memory_size_a = 970; - } else if (lb_config == LB_MEMORY_CONFIG_2) { - lb_memory_size = 1290; - lb_memory_size_c = 1290; - lb_memory_size_a = 1290; - } else if (lb_config == LB_MEMORY_CONFIG_3) { - /* 420 mode: using 3rd mem from Y, Cr and Cb */ - lb_memory_size = 970 + 1290 + 484 + 484 + 484; - lb_memory_size_c = 970 + 1290; - lb_memory_size_a = 970 + 1290 + 484; - } else { - lb_memory_size = 970 + 1290 + 484; - lb_memory_size_c = 970 + 1290 + 484; - lb_memory_size_a = 970 + 1290 + 484; - } - *num_part_y = lb_memory_size / memory_line_size_y; - *num_part_c = lb_memory_size_c / memory_line_size_c; - num_partitions_a = lb_memory_size_a / memory_line_size_a; - - if (scl_data->lb_params.alpha_en - && (num_partitions_a < *num_part_y)) - *num_part_y = num_partitions_a; - - if (*num_part_y > 64) - *num_part_y = 64; - if (*num_part_c > 64) - *num_part_c = 64; -} - -void dpp2_cnv_set_alpha_keyer( - struct dpp *dpp_base, - struct cnv_color_keyer_params *color_keyer) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en); - - REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode); - - REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low); - REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high); - - REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low); - REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high); - - REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low); - REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high); - - REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low); - REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high); -} - -void dpp2_set_cursor_attributes( - struct dpp *dpp_base, - struct dc_cursor_attributes *cursor_attributes) -{ - enum dc_cursor_color_format color_format = cursor_attributes->color_format; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - int cur_rom_en = 0; - - if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || - color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { - if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) { - cur_rom_en = 1; - } - } - - REG_UPDATE_3(CURSOR0_CONTROL, - CUR0_MODE, color_format, - CUR0_EXPANSION_MODE, 0, - CUR0_ROM_EN, cur_rom_en); - - if (color_format == CURSOR_MODE_MONO) { - /* todo: clarify what to program these to */ - REG_UPDATE(CURSOR0_COLOR0, - CUR0_COLOR0, 0x00000000); - REG_UPDATE(CURSOR0_COLOR1, - CUR0_COLOR1, 0xFFFFFFFF); - } -} - -void oppn20_dummy_program_regamma_pwl( - struct dpp *dpp, - const struct pwl_params *params, - enum opp_regamma mode) -{} - -static struct dpp_funcs dcn20_dpp_funcs = { - .dpp_read_state = dpp20_read_state, - .dpp_reset = dpp_reset, - .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, - .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps, - .dpp_set_gamut_remap = dpp2_cm_set_gamut_remap, - .dpp_set_csc_adjustment = NULL, - .dpp_set_csc_default = NULL, - .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl, - .dpp_set_degamma = dpp2_set_degamma, - .dpp_program_input_lut = dpp2_dummy_program_input_lut, - .dpp_full_bypass = dpp1_full_bypass, - .dpp_setup = dpp2_cnv_setup, - .dpp_program_degamma_pwl = dpp2_set_degamma_pwl, - .dpp_program_blnd_lut = dpp20_program_blnd_lut, - .dpp_program_shaper_lut = dpp20_program_shaper, - .dpp_program_3dlut = dpp20_program_3dlut, - .dpp_program_bias_and_scale = NULL, - .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, - .set_cursor_attributes = dpp2_set_cursor_attributes, - .set_cursor_position = dpp1_set_cursor_position, - .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, - .dpp_dppclk_control = dpp1_dppclk_control, - .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier, - .dpp_get_gamut_remap = dpp2_cm_get_gamut_remap, -}; - -static struct dpp_caps dcn20_dpp_cap = { - .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, - .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, -}; - -bool dpp2_construct( - struct dcn20_dpp *dpp, - struct dc_context *ctx, - uint32_t inst, - const struct dcn2_dpp_registers *tf_regs, - const struct dcn2_dpp_shift *tf_shift, - const struct dcn2_dpp_mask *tf_mask) -{ - dpp->base.ctx = ctx; - - dpp->base.inst = inst; - dpp->base.funcs = &dcn20_dpp_funcs; - dpp->base.caps = &dcn20_dpp_cap; - - dpp->tf_regs = tf_regs; - dpp->tf_shift = tf_shift; - dpp->tf_mask = tf_mask; - - dpp->lb_pixel_depth_supported = - LB_PIXEL_DEPTH_18BPP | - LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP | - LB_PIXEL_DEPTH_36BPP; - - dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; - dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ - - return true; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h deleted file mode 100644 index 672cde46c4b9..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h +++ /dev/null @@ -1,781 +0,0 @@ -/* Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN20_DPP_H__ -#define __DCN20_DPP_H__ - -#include "dcn10/dcn10_dpp.h" - -#define TO_DCN20_DPP(dpp)\ - container_of(dpp, struct dcn20_dpp, base) - -#define TF_REG_LIST_DCN20_COMMON_UPDATED(id) \ - SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \ - SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id) - -#define TF_REG_LIST_DCN20_COMMON(id) \ - SRI(CM_BLNDGAM_CONTROL, CM, id), \ - SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL2_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL1_R, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL2_R, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_0_1, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_2_3, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_4_5, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_6_7, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_8_9, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_10_11, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_12_13, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_14_15, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_16_17, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_18_19, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_20_21, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_22_23, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_24_25, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_26_27, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_28_29, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_30_31, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_32_33, CM, id), \ - SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL2_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL1_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL2_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_0_1, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_2_3, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_4_5, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_6_7, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_8_9, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_10_11, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_12_13, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_14_15, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_16_17, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_18_19, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_20_21, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_22_23, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_24_25, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_26_27, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_28_29, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_30_31, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_32_33, CM, id), \ - SRI(CM_BLNDGAM_LUT_INDEX, CM, id), \ - SRI(CM_BLNDGAM_LUT_DATA, CM, id), \ - SRI(CM_3DLUT_MODE, CM, id), \ - SRI(CM_3DLUT_INDEX, CM, id), \ - SRI(CM_3DLUT_DATA, CM, id), \ - SRI(CM_3DLUT_DATA_30BIT, CM, id), \ - SRI(CM_3DLUT_READ_WRITE_CONTROL, CM, id), \ - SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \ - SRI(CM_SHAPER_CONTROL, CM, id), \ - SRI(CM_SHAPER_RAMB_START_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMB_START_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMB_START_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMB_END_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMB_END_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMB_END_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_0_1, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_2_3, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_4_5, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_6_7, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_8_9, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_10_11, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_12_13, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_14_15, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_16_17, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_18_19, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_20_21, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_22_23, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_24_25, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_26_27, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_28_29, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_30_31, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_32_33, CM, id), \ - SRI(CM_SHAPER_RAMA_START_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMA_START_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMA_START_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMA_END_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMA_END_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMA_END_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_0_1, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_2_3, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_4_5, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_6_7, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_8_9, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_10_11, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_12_13, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_14_15, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_16_17, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_18_19, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_20_21, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_22_23, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_24_25, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_26_27, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \ - SRI(CM_SHAPER_LUT_INDEX, CM, id) - -#define TF_REG_LIST_DCN20_COMMON_APPEND(id) \ - SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\ - SRI(CM_ICSC_B_C11_C12, CM, id), \ - SRI(CM_ICSC_B_C33_C34, CM, id) - -#define TF_REG_LIST_DCN20(id) \ - TF_REG_LIST_DCN(id), \ - TF_REG_LIST_DCN20_COMMON(id), \ - TF_REG_LIST_DCN20_COMMON_UPDATED(id), \ - SRI(CURSOR_CONTROL, CURSOR0_, id), \ - SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \ - SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \ - SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \ - SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \ - SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \ - SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \ - SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \ - SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ - SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ - SRI(COLOR_KEYER_RED, CNVC_CFG, id), \ - SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \ - SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \ - SRI(CM_SHAPER_LUT_DATA, CM, id), \ - SRI(CURSOR_CONTROL, CURSOR0_, id),\ - SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\ - SRI(DSCL_MEM_PWR_CTRL, DSCL, id) - - -#define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\ - TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh) - - -#define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\ - TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \ - TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \ - TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ - TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \ - TF_SF(CM0_CM_3DLUT_INDEX, CM_3DLUT_INDEX, mask_sh), \ - TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \ - TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA1, mask_sh), \ - TF_SF(CM0_CM_3DLUT_DATA_30BIT, CM_3DLUT_DATA_30BIT, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \ - TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh) - - -#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ - TF_REG_LIST_SH_MASK_DCN(mask_sh), \ - TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \ - TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \ - TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \ - TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ - TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ - TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ - TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ - TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ - TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh) - -/* DPP CM debug status register: - * - * Status index including current ICSC, Gamut Remap Mode is 9 - * ICSC Mode: [4..3] - * Gamut Remap Mode: [10..9] - */ -#define CM_TEST_DEBUG_DATA_STATUS_IDX 9 - -#define TF_DEBUG_REG_LIST_SH_DCN20 \ - TF_DEBUG_REG_LIST_SH_DCN10, \ - .CM_TEST_DEBUG_DATA_ICSC_MODE = 3, \ - .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 9 - -#define TF_DEBUG_REG_LIST_MASK_DCN20 \ - TF_DEBUG_REG_LIST_MASK_DCN10, \ - .CM_TEST_DEBUG_DATA_ICSC_MODE = 0x18, \ - .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 0x600 - -#define TF_REG_FIELD_LIST_DCN2_0(type) \ - TF_REG_FIELD_LIST(type) \ - type CM_BLNDGAM_LUT_DATA; \ - type CM_TEST_DEBUG_DATA_ICSC_MODE; \ - type CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE; \ - type FORMAT_CNV16; \ - type CNVC_BYPASS_MSB_ALIGN; \ - type CLAMP_POSITIVE; \ - type CLAMP_POSITIVE_C; \ - type ALPHA_2BIT_LUT0; \ - type ALPHA_2BIT_LUT1; \ - type ALPHA_2BIT_LUT2; \ - type ALPHA_2BIT_LUT3; \ - type FCNV_FP_BIAS_R; \ - type FCNV_FP_BIAS_G; \ - type FCNV_FP_BIAS_B; \ - type FCNV_FP_SCALE_R; \ - type FCNV_FP_SCALE_G; \ - type FCNV_FP_SCALE_B; \ - type COLOR_KEYER_EN; \ - type COLOR_KEYER_MODE; \ - type COLOR_KEYER_ALPHA_LOW; \ - type COLOR_KEYER_ALPHA_HIGH; \ - type COLOR_KEYER_RED_LOW; \ - type COLOR_KEYER_RED_HIGH; \ - type COLOR_KEYER_GREEN_LOW; \ - type COLOR_KEYER_GREEN_HIGH; \ - type COLOR_KEYER_BLUE_LOW; \ - type COLOR_KEYER_BLUE_HIGH; \ - type CUR0_PIX_INV_MODE; \ - type CUR0_PIXEL_ALPHA_MOD_EN; \ - type CUR0_ROM_EN;\ - type OBUF_MEM_PWR_FORCE - - -struct dcn2_dpp_shift { - TF_REG_FIELD_LIST_DCN2_0(uint8_t); -}; - -struct dcn2_dpp_mask { - TF_REG_FIELD_LIST_DCN2_0(uint32_t); -}; - -#define DPP_DCN2_REG_VARIABLE_LIST \ - DPP_COMMON_REG_VARIABLE_LIST \ - uint32_t CM_BLNDGAM_LUT_DATA; \ - uint32_t ALPHA_2BIT_LUT; \ - uint32_t FCNV_FP_BIAS_R; \ - uint32_t FCNV_FP_BIAS_G; \ - uint32_t FCNV_FP_BIAS_B; \ - uint32_t FCNV_FP_SCALE_R; \ - uint32_t FCNV_FP_SCALE_G; \ - uint32_t FCNV_FP_SCALE_B; \ - uint32_t COLOR_KEYER_CONTROL; \ - uint32_t COLOR_KEYER_ALPHA; \ - uint32_t COLOR_KEYER_RED; \ - uint32_t COLOR_KEYER_GREEN; \ - uint32_t COLOR_KEYER_BLUE; \ - uint32_t OBUF_MEM_PWR_CTRL - -#define DPP_DCN2_REG_VARIABLE_LIST_CM_APPEND \ - uint32_t CM_GAMUT_REMAP_B_C11_C12; \ - uint32_t CM_GAMUT_REMAP_B_C13_C14; \ - uint32_t CM_GAMUT_REMAP_B_C21_C22; \ - uint32_t CM_GAMUT_REMAP_B_C23_C24; \ - uint32_t CM_GAMUT_REMAP_B_C31_C32; \ - uint32_t CM_GAMUT_REMAP_B_C33_C34; \ - uint32_t CM_ICSC_B_C11_C12; \ - uint32_t CM_ICSC_B_C33_C34 - -struct dcn2_dpp_registers { - DPP_DCN2_REG_VARIABLE_LIST; - DPP_DCN2_REG_VARIABLE_LIST_CM_APPEND; -}; - -struct dcn20_dpp { - struct dpp base; - - const struct dcn2_dpp_registers *tf_regs; - const struct dcn2_dpp_shift *tf_shift; - const struct dcn2_dpp_mask *tf_mask; - - const uint16_t *filter_v; - const uint16_t *filter_h; - const uint16_t *filter_v_c; - const uint16_t *filter_h_c; - int lb_pixel_depth_supported; - int lb_memory_size; - int lb_bits_per_entry; - bool is_write_to_ram_a_safe; - struct scaler_data scl_data; - struct pwl_params pwl_data; -}; - -enum dcn20_input_csc_select { - DCN2_ICSC_SELECT_BYPASS = 0, - DCN2_ICSC_SELECT_ICSC_A = 1, - DCN2_ICSC_SELECT_ICSC_B = 2 -}; - -enum dcn20_gamut_remap_select { - DCN2_GAMUT_REMAP_BYPASS = 0, - DCN2_GAMUT_REMAP_COEF_A = 1, - DCN2_GAMUT_REMAP_COEF_B = 2 -}; - -void dpp20_read_state(struct dpp *dpp_base, - struct dcn_dpp_state *s); - -void dpp2_set_degamma_pwl( - struct dpp *dpp_base, - const struct pwl_params *params); - -void dpp2_set_degamma( - struct dpp *dpp_base, - enum ipp_degamma_mode mode); - -void dpp2_cm_set_gamut_remap( - struct dpp *dpp_base, - const struct dpp_grph_csc_adjustment *adjust); - -void dpp2_program_input_csc( - struct dpp *dpp_base, - enum dc_color_space color_space, - enum dcn20_input_csc_select input_select, - const struct out_csc_color_matrix *tbl_entry); - -bool dpp20_program_blnd_lut( - struct dpp *dpp_base, const struct pwl_params *params); - -bool dpp20_program_shaper( - struct dpp *dpp_base, - const struct pwl_params *params); - -bool dpp20_program_3dlut( - struct dpp *dpp_base, - struct tetrahedral_params *params); - -void dpp2_cnv_set_alpha_keyer( - struct dpp *dpp_base, - struct cnv_color_keyer_params *color_keyer); - -void dscl2_calc_lb_num_partitions( - const struct scaler_data *scl_data, - enum lb_memory_config lb_config, - int *num_part_y, - int *num_part_c); - -void dpp2_set_cursor_attributes( - struct dpp *dpp_base, - struct dc_cursor_attributes *cursor_attributes); - -void dpp2_dummy_program_input_lut( - struct dpp *dpp_base, - const struct dc_gamma *gamma); - -void oppn20_dummy_program_regamma_pwl( - struct dpp *dpp, - const struct pwl_params *params, - enum opp_regamma mode); - -void dpp2_set_hdr_multiplier( - struct dpp *dpp_base, - uint32_t multiplier); - -bool dpp2_construct(struct dcn20_dpp *dpp2, - struct dc_context *ctx, - uint32_t inst, - const struct dcn2_dpp_registers *tf_regs, - const struct dcn2_dpp_shift *tf_shift, - const struct dcn2_dpp_mask *tf_mask); - -void dpp2_power_on_obuf( - struct dpp *dpp_base, - bool power_on); - -void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, - struct dpp_grph_csc_adjustment *adjust); -#endif /* __DC_HWSS_DCN20_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c deleted file mode 100644 index 58dc69926e8a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c +++ /dev/null @@ -1,1202 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "core_types.h" - -#include "reg_helper.h" -#include "dcn20_dpp.h" -#include "basics/conversion.h" - -#include "dcn10/dcn10_cm_common.h" - -#define REG(reg)\ - dpp->tf_regs->reg - -#define IND_REG(index) \ - (index) - -#define CTX \ - dpp->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - dpp->tf_shift->field_name, dpp->tf_mask->field_name - - -static void dpp2_enable_cm_block( - struct dpp *dpp_base) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - unsigned int cm_bypass_mode = 0; - //Temp, put CM in bypass mode - if (dpp_base->ctx->dc->debug.cm_in_bypass) - cm_bypass_mode = 1; - - REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode); -} - - -static bool dpp2_degamma_ram_inuse( - struct dpp *dpp_base, - bool *ram_a_inuse) -{ - bool ret = false; - uint32_t status_reg = 0; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, - &status_reg); - - if (status_reg == 3) { - *ram_a_inuse = true; - ret = true; - } else if (status_reg == 4) { - *ram_a_inuse = false; - ret = true; - } - return ret; -} - -static void dpp2_program_degamma_lut( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num, - bool is_ram_a) -{ - uint32_t i; - - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, - CM_DGAM_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, - is_ram_a == true ? 0:1); - - REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); - for (i = 0 ; i < num; i++) { - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); - - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg); - - } - -} - -void dpp2_set_degamma_pwl( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - bool is_ram_a = true; - - dpp1_power_on_degamma_lut(dpp_base, true); - dpp2_enable_cm_block(dpp_base); - dpp2_degamma_ram_inuse(dpp_base, &is_ram_a); - if (is_ram_a == true) - dpp1_program_degamma_lutb_settings(dpp_base, params); - else - dpp1_program_degamma_luta_settings(dpp_base, params); - - dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); - dpp1_degamma_ram_select(dpp_base, !is_ram_a); -} - -void dpp2_set_degamma( - struct dpp *dpp_base, - enum ipp_degamma_mode mode) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - dpp2_enable_cm_block(dpp_base); - - switch (mode) { - case IPP_DEGAMMA_MODE_BYPASS: - /* Setting de gamma bypass for now */ - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); - break; - case IPP_DEGAMMA_MODE_HW_sRGB: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); - break; - case IPP_DEGAMMA_MODE_HW_xvYCC: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); - break; - case IPP_DEGAMMA_MODE_USER_PWL: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } -} - -static void program_gamut_remap( - struct dcn20_dpp *dpp, - const uint16_t *regval, - enum dcn20_gamut_remap_select select) -{ - uint32_t cur_select = 0; - struct color_matrices_reg gam_regs; - - if (regval == NULL || select == DCN2_GAMUT_REMAP_BYPASS) { - REG_SET(CM_GAMUT_REMAP_CONTROL, 0, - CM_GAMUT_REMAP_MODE, 0); - return; - } - - /* determine which gamut_remap coefficients (A or B) we are using - * currently. select the alternate set to double buffer - * the update so gamut_remap is updated on frame boundary - */ - IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA, - CM_TEST_DEBUG_DATA_STATUS_IDX, - CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE, &cur_select); - - /* value stored in dbg reg will be 1 greater than mode we want */ - if (cur_select != DCN2_GAMUT_REMAP_COEF_A) - select = DCN2_GAMUT_REMAP_COEF_A; - else - select = DCN2_GAMUT_REMAP_COEF_B; - - gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; - gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; - gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; - gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; - - if (select == DCN2_GAMUT_REMAP_COEF_A) { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); - } else { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); - } - - cm_helper_program_color_matrices( - dpp->base.ctx, - regval, - &gam_regs); - - REG_SET( - CM_GAMUT_REMAP_CONTROL, 0, - CM_GAMUT_REMAP_MODE, select); - -} - -void dpp2_cm_set_gamut_remap( - struct dpp *dpp_base, - const struct dpp_grph_csc_adjustment *adjust) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - int i = 0; - - if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) - /* Bypass if type is bypass or hw */ - program_gamut_remap(dpp, NULL, DCN2_GAMUT_REMAP_BYPASS); - else { - struct fixed31_32 arr_matrix[12]; - uint16_t arr_reg_val[12]; - - for (i = 0; i < 12; i++) - arr_matrix[i] = adjust->temperature_matrix[i]; - - convert_float_matrix( - arr_reg_val, arr_matrix, 12); - - program_gamut_remap(dpp, arr_reg_val, DCN2_GAMUT_REMAP_COEF_A); - } -} - -static void read_gamut_remap(struct dcn20_dpp *dpp, - uint16_t *regval, - enum dcn20_gamut_remap_select *select) -{ - struct color_matrices_reg gam_regs; - uint32_t selection; - - IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA, - CM_TEST_DEBUG_DATA_STATUS_IDX, - CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE, &selection); - - *select = selection; - - gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; - gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; - gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; - gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; - - if (*select == DCN2_GAMUT_REMAP_COEF_A) { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); - - cm_helper_read_color_matrices(dpp->base.ctx, - regval, - &gam_regs); - - } else if (*select == DCN2_GAMUT_REMAP_COEF_B) { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); - - cm_helper_read_color_matrices(dpp->base.ctx, - regval, - &gam_regs); - } -} - -void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, - struct dpp_grph_csc_adjustment *adjust) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - uint16_t arr_reg_val[12]; - enum dcn20_gamut_remap_select select; - - read_gamut_remap(dpp, arr_reg_val, &select); - - if (select == DCN2_GAMUT_REMAP_BYPASS) { - adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - return; - } - - adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; - convert_hw_matrix(adjust->temperature_matrix, - arr_reg_val, ARRAY_SIZE(arr_reg_val)); -} - -void dpp2_program_input_csc( - struct dpp *dpp_base, - enum dc_color_space color_space, - enum dcn20_input_csc_select input_select, - const struct out_csc_color_matrix *tbl_entry) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - int i; - int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix); - const uint16_t *regval = NULL; - uint32_t cur_select = 0; - enum dcn20_input_csc_select select; - struct color_matrices_reg icsc_regs; - - if (input_select == DCN2_ICSC_SELECT_BYPASS) { - REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); - return; - } - - if (tbl_entry == NULL) { - for (i = 0; i < arr_size; i++) - if (dpp_input_csc_matrix[i].color_space == color_space) { - regval = dpp_input_csc_matrix[i].regval; - break; - } - - if (regval == NULL) { - BREAK_TO_DEBUGGER(); - return; - } - } else { - regval = tbl_entry->regval; - } - - /* determine which CSC coefficients (A or B) we are using - * currently. select the alternate set to double buffer - * the CSC update so CSC is updated on frame boundary - */ - IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA, - CM_TEST_DEBUG_DATA_STATUS_IDX, - CM_TEST_DEBUG_DATA_ICSC_MODE, &cur_select); - - if (cur_select != DCN2_ICSC_SELECT_ICSC_A) - select = DCN2_ICSC_SELECT_ICSC_A; - else - select = DCN2_ICSC_SELECT_ICSC_B; - - icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; - icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; - icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; - icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; - - if (select == DCN2_ICSC_SELECT_ICSC_A) { - - icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); - icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); - - } else { - - icsc_regs.csc_c11_c12 = REG(CM_ICSC_B_C11_C12); - icsc_regs.csc_c33_c34 = REG(CM_ICSC_B_C33_C34); - - } - - cm_helper_program_color_matrices( - dpp->base.ctx, - regval, - &icsc_regs); - - REG_SET(CM_ICSC_CONTROL, 0, - CM_ICSC_MODE, select); -} - -static void dpp20_power_on_blnd_lut( - struct dpp *dpp_base, - bool power_on) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_SET(CM_MEM_PWR_CTRL, 0, - BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0:1); - -} - -static void dpp20_configure_blnd_lut( - struct dpp *dpp_base, - bool is_ram_a) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK, - CM_BLNDGAM_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK, - CM_BLNDGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); - REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); -} - -static void dpp20_program_blnd_pwl( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num) -{ - uint32_t i; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0 ; i < num; i++) { - REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); - - REG_SET(CM_BLNDGAM_LUT_DATA, 0, - CM_BLNDGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, - CM_BLNDGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, - CM_BLNDGAM_LUT_DATA, rgb[i].delta_blue_reg); - - } - -} - -static void dcn20_dpp_cm_get_reg_field( - struct dcn20_dpp *dpp, - struct xfer_func_reg *reg) -{ - reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - - reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; - reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; - reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; - reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; - reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; - reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; - reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; - reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; - reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; - reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; - reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; - reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; -} - -/*program blnd lut RAM A*/ -static void dpp20_program_blnd_luta_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - struct xfer_func_reg gam_regs; - - dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); - - gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); - gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); - gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); - gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_B); - gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_G); - gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R); - gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); - gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); - gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); - gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); - gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); - gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); - gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); - gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); - - cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); -} - -/*program blnd lut RAM B*/ -static void dpp20_program_blnd_lutb_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - struct xfer_func_reg gam_regs; - - dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); - - gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); - gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); - gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); - gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_B); - gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_G); - gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R); - gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); - gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); - gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); - gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); - gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); - gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); - gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); - gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); - - cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); -} - -static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base) -{ - enum dc_lut_mode mode; - uint32_t state_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, &state_mode); - - switch (state_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - - return mode; -} - -bool dpp20_program_blnd_lut( - struct dpp *dpp_base, const struct pwl_params *params) -{ - enum dc_lut_mode current_mode; - enum dc_lut_mode next_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - if (params == NULL) { - REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, 0); - return false; - } - current_mode = dpp20_get_blndgam_current(dpp_base); - if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) - next_mode = LUT_RAM_B; - else - next_mode = LUT_RAM_A; - - dpp20_power_on_blnd_lut(dpp_base, true); - dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A); - - if (next_mode == LUT_RAM_A) - dpp20_program_blnd_luta_settings(dpp_base, params); - else - dpp20_program_blnd_lutb_settings(dpp_base, params); - - dpp20_program_blnd_pwl( - dpp_base, params->rgb_resulted, params->hw_points_num); - - REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, - next_mode == LUT_RAM_A ? 1:2); - - return true; -} - - -static void dpp20_program_shaper_lut( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num) -{ - uint32_t i, red, green, blue; - uint32_t red_delta, green_delta, blue_delta; - uint32_t red_value, green_value, blue_value; - - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0 ; i < num; i++) { - - red = rgb[i].red_reg; - green = rgb[i].green_reg; - blue = rgb[i].blue_reg; - - red_delta = rgb[i].delta_red_reg; - green_delta = rgb[i].delta_green_reg; - blue_delta = rgb[i].delta_blue_reg; - - red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); - green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); - blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); - - REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); - REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); - REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); - } - -} - -static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base) -{ - enum dc_lut_mode mode; - uint32_t state_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, &state_mode); - - switch (state_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - - return mode; -} - -static void dpp20_configure_shaper_lut( - struct dpp *dpp_base, - bool is_ram_a) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, - CM_SHAPER_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, - CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); - REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); -} - -/*program shaper RAM A*/ - -static void dpp20_program_shaper_luta_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, - CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); - REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, - CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0); - REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, - CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, - CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, - CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, - CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); - - curve = params->arr_curve_points; - REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, - CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, - CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, - CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, - CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, - CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, - CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, - CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, - CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, - CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, - CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0, - CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0, - CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0, - CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0, - CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0, - CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0, - CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0, - CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); -} - -/*program shaper RAM B*/ -static void dpp20_program_shaper_lutb_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, - CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); - REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, - CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0); - REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, - CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, - CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, - CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, - CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); - - curve = params->arr_curve_points; - REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, - CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, - CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, - CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, - CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0, - CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0, - CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0, - CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0, - CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0, - CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0, - CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0, - CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0, - CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0, - CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0, - CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0, - CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0, - CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0, - CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); - -} - - -bool dpp20_program_shaper( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - enum dc_lut_mode current_mode; - enum dc_lut_mode next_mode; - - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - if (params == NULL) { - REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); - return false; - } - current_mode = dpp20_get_shaper_current(dpp_base); - - if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) - next_mode = LUT_RAM_B; - else - next_mode = LUT_RAM_A; - - dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A); - - if (next_mode == LUT_RAM_A) - dpp20_program_shaper_luta_settings(dpp_base, params); - else - dpp20_program_shaper_lutb_settings(dpp_base, params); - - dpp20_program_shaper_lut( - dpp_base, params->rgb_resulted, params->hw_points_num); - - REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); - - return true; - -} - -static enum dc_lut_mode get3dlut_config( - struct dpp *dpp_base, - bool *is_17x17x17, - bool *is_12bits_color_channel) -{ - uint32_t i_mode, i_enable_10bits, lut_size; - enum dc_lut_mode mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL, - CM_3DLUT_CONFIG_STATUS, &i_mode, - CM_3DLUT_30BIT_EN, &i_enable_10bits); - - switch (i_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - if (i_enable_10bits > 0) - *is_12bits_color_channel = false; - else - *is_12bits_color_channel = true; - - REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); - - if (lut_size == 0) - *is_17x17x17 = true; - else - *is_17x17x17 = false; - - return mode; -} -/* - * select ramA or ramB, or bypass - * select color channel size 10 or 12 bits - * select 3dlut size 17x17x17 or 9x9x9 - */ -static void dpp20_set_3dlut_mode( - struct dpp *dpp_base, - enum dc_lut_mode mode, - bool is_color_channel_12bits, - bool is_lut_size17x17x17) -{ - uint32_t lut_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - if (mode == LUT_BYPASS) - lut_mode = 0; - else if (mode == LUT_RAM_A) - lut_mode = 1; - else - lut_mode = 2; - - REG_UPDATE_2(CM_3DLUT_MODE, - CM_3DLUT_MODE, lut_mode, - CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); -} - -static void dpp20_select_3dlut_ram( - struct dpp *dpp_base, - enum dc_lut_mode mode, - bool is_color_channel_12bits) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL, - CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, - CM_3DLUT_30BIT_EN, - is_color_channel_12bits == true ? 0:1); -} - - - -static void dpp20_set3dlut_ram12( - struct dpp *dpp_base, - const struct dc_rgb *lut, - uint32_t entries) -{ - uint32_t i, red, green, blue, red1, green1, blue1; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0 ; i < entries; i += 2) { - red = lut[i].red<<4; - green = lut[i].green<<4; - blue = lut[i].blue<<4; - red1 = lut[i+1].red<<4; - green1 = lut[i+1].green<<4; - blue1 = lut[i+1].blue<<4; - - REG_SET_2(CM_3DLUT_DATA, 0, - CM_3DLUT_DATA0, red, - CM_3DLUT_DATA1, red1); - - REG_SET_2(CM_3DLUT_DATA, 0, - CM_3DLUT_DATA0, green, - CM_3DLUT_DATA1, green1); - - REG_SET_2(CM_3DLUT_DATA, 0, - CM_3DLUT_DATA0, blue, - CM_3DLUT_DATA1, blue1); - - } -} - -/* - * load selected lut with 10 bits color channels - */ -static void dpp20_set3dlut_ram10( - struct dpp *dpp_base, - const struct dc_rgb *lut, - uint32_t entries) -{ - uint32_t i, red, green, blue, value; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0; i < entries; i++) { - red = lut[i].red; - green = lut[i].green; - blue = lut[i].blue; - - value = (red<<20) | (green<<10) | blue; - - REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); - } - -} - - -static void dpp20_select_3dlut_ram_mask( - struct dpp *dpp_base, - uint32_t ram_selection_mask) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, - ram_selection_mask); - REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); -} - -bool dpp20_program_3dlut( - struct dpp *dpp_base, - struct tetrahedral_params *params) -{ - enum dc_lut_mode mode; - bool is_17x17x17; - bool is_12bits_color_channel; - struct dc_rgb *lut0; - struct dc_rgb *lut1; - struct dc_rgb *lut2; - struct dc_rgb *lut3; - int lut_size0; - int lut_size; - - if (params == NULL) { - dpp20_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); - return false; - } - mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); - - if (mode == LUT_BYPASS || mode == LUT_RAM_B) - mode = LUT_RAM_A; - else - mode = LUT_RAM_B; - - is_17x17x17 = !params->use_tetrahedral_9; - is_12bits_color_channel = params->use_12bits; - if (is_17x17x17) { - lut0 = params->tetrahedral_17.lut0; - lut1 = params->tetrahedral_17.lut1; - lut2 = params->tetrahedral_17.lut2; - lut3 = params->tetrahedral_17.lut3; - lut_size0 = sizeof(params->tetrahedral_17.lut0)/ - sizeof(params->tetrahedral_17.lut0[0]); - lut_size = sizeof(params->tetrahedral_17.lut1)/ - sizeof(params->tetrahedral_17.lut1[0]); - } else { - lut0 = params->tetrahedral_9.lut0; - lut1 = params->tetrahedral_9.lut1; - lut2 = params->tetrahedral_9.lut2; - lut3 = params->tetrahedral_9.lut3; - lut_size0 = sizeof(params->tetrahedral_9.lut0)/ - sizeof(params->tetrahedral_9.lut0[0]); - lut_size = sizeof(params->tetrahedral_9.lut1)/ - sizeof(params->tetrahedral_9.lut1[0]); - } - - dpp20_select_3dlut_ram(dpp_base, mode, - is_12bits_color_channel); - dpp20_select_3dlut_ram_mask(dpp_base, 0x1); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut0, lut_size0); - else - dpp20_set3dlut_ram10(dpp_base, lut0, lut_size0); - - dpp20_select_3dlut_ram_mask(dpp_base, 0x2); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut1, lut_size); - else - dpp20_set3dlut_ram10(dpp_base, lut1, lut_size); - - dpp20_select_3dlut_ram_mask(dpp_base, 0x4); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut2, lut_size); - else - dpp20_set3dlut_ram10(dpp_base, lut2, lut_size); - - dpp20_select_3dlut_ram_mask(dpp_base, 0x8); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut3, lut_size); - else - dpp20_set3dlut_ram10(dpp_base, lut3, lut_size); - - - dpp20_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, - is_17x17x17); - - return true; -} - -void dpp2_set_hdr_multiplier( - struct dpp *dpp_base, - uint32_t multiplier) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier); -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c index f8667be57046..80779e85e2c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c @@ -299,6 +299,17 @@ void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params) } } + + if (dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL) { + /* Swap double buffered coefficient set */ + uint32_t wbscl_mode = REG_READ(WBSCL_MODE); + bool coef_ram_current = get_reg_field_value_ex( + wbscl_mode, dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL_CURRENT, + dwbc20->dwbc_shift->WBSCL_COEF_RAM_SEL_CURRENT); + + REG_UPDATE(WBSCL_MODE, WBSCL_COEF_RAM_SEL, !coef_ram_current); + } + } static const struct dwbc_funcs dcn20_dwbc_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c index 6eebcb22e317..c6f859871d11 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c @@ -570,7 +570,7 @@ void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub, static bool hubbub2_program_watermarks( struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, + union dcn_watermark_set *watermarks, unsigned int refclk_mhz, bool safe_to_lower) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h index 2f6146bf1d32..24a9c45988ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h @@ -85,7 +85,7 @@ struct dcn20_hubbub { const struct dcn_hubbub_shift *shifts; const struct dcn_hubbub_mask *masks; unsigned int debug_test_index_pstate; - struct dcn_watermark_set watermarks; + union dcn_watermark_set watermarks; int num_vmid; struct dcn20_vmid vmid[16]; unsigned int detile_buf_size; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c index 89c3bf0fe0c9..6bba020ad6fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c @@ -1331,6 +1331,12 @@ void hubp2_read_state(struct hubp *hubp) SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); + if (REG(DCHUBP_CNTL)) + s->hubp_cntl = REG_READ(DCHUBP_CNTL); + + if (REG(DCSURF_FLIP_CONTROL)) + s->flip_control = REG_READ(DCSURF_FLIP_CONTROL); + } static void hubp2_validate_dml_output(struct hubp *hubp, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h index efa2adf4f83d..8da3084d933f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h @@ -147,7 +147,7 @@ uint32_t DCN_CUR1_TTU_CNTL1;\ uint32_t VMID_SETTINGS_0 - +/*shared with dcn3.x*/ #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \ uint32_t FLIP_PARAMETERS_3;\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h index b2b266953d18..c34e04cac9a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h @@ -147,7 +147,8 @@ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh) + LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\ + LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh) #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\ DPCS_MASK_SH_LIST(mask_sh),\ @@ -231,6 +232,8 @@ SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \ SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \ SRI(DPCSTX_TX_CNTL, DPCSTX, id), \ + SRI(DPCSTX_DEBUG_CONFIG, DPCSTX, id), \ + SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \ SR(RDPCSTX0_RDPCSTX_SCRATCH) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c index 16b5ff208d14..ea73473b970a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c @@ -395,9 +395,12 @@ static void mpc20_program_ogam_pwl( MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg); REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg); - } + REG_SEQ_SUBMIT(); + PERF_TRACE(); + REG_SEQ_WAIT_DONE(); + PERF_TRACE(); } static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id, @@ -501,11 +504,6 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) ASSERT(!mpc_disabled); ASSERT(!mpc_idle); } - - REG_SEQ_SUBMIT(); - PERF_TRACE(); - REG_SEQ_WAIT_DONE(); - PERF_TRACE(); } static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) |