diff options
| author | Zhan Liu <zhan.liu@amd.com> | 2020-08-28 14:18:56 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-09-15 17:52:41 -0400 |
| commit | 48e48e5984782171ac8d2ec09b7e688e141d7c86 (patch) | |
| tree | b26bd4317d68f07f562a99c909c3382d8f5a4823 /drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | |
| parent | bd80d584cd8e2502b6be48544a14970016c86aa4 (diff) | |
drm/amd/display: Disable idle optimization when PSR is enabled
[Why]
Idle optimization and PSR conflict each other. If both enabled
at the same time, display flickering will be observed.
[How]
Disable idle optimization when PSR is enabled.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 1390ff1ce7be..7886c32d8315 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -690,26 +690,23 @@ void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx) bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) { - unsigned int surface_size; - if (!dc->ctx->dmub_srv) return false; if (enable) { - if (dc->current_state - && dc->current_state->stream_count == 1 // single display only - && dc->current_state->stream_status[0].plane_count == 1 // single surface only - && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM - // Only 8 and 16 bit formats - && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F - && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) { - - surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch * - dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height * - (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); - + if (dc->current_state) { + int i; + + /* First, check no-memory-requests case */ + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->stream_status[i] + .plane_count) + /* Fail eligibility on a visible stream */ + break; + } } + /* No applicable optimizations */ return false; } |