diff options
| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2018-07-24 13:19:49 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 11:09:49 -0500 |
| commit | 4e60536d093f486229bb8d86c739e8ef6446df85 (patch) | |
| tree | 957a153a089efa40e9c42386fb201cda08521bbb /drivers/gpu/drm/amd/display/include | |
| parent | 2cb3bcdb33c0a18b25a23e7081de8c9a1698a80e (diff) | |
drm/amd/display: Set DFS bypass flags for dce110
[Why]
While there is support for using and quering DFS bypass clocks the
hardware is never notified to enter DFS bypass mode for dce110.
[How]
Add a flag that can be set when programming the display engine PLL
to enable DFS bypass mode. If this flag is set then the hardware is
notified to enter DFS bypass mode and the correct display engine clock
frequency can be acquired.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/bios_parser_types.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index 0840f69cde99..f8dbfa5b89f2 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -234,6 +234,8 @@ struct bp_pixel_clock_parameters { uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1; /* Use external reference clock (refDivSrc for PLL) */ uint32_t SET_EXTERNAL_REF_DIV_SRC:1; + /* Use DFS bypass for Display clock. */ + uint32_t SET_DISPCLK_DFS_BYPASS:1; /* Force program PHY PLL only */ uint32_t PROGRAM_PHY_PLL_ONLY:1; /* Support for YUV420 */ |