diff options
| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2021-05-19 12:37:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-04 16:39:18 -0400 |
| commit | bf62221e9d0e1e4ba50ab2b331a0008c15de97be (patch) | |
| tree | 74a12b8a2ac3ee32fecede6819fb1f65651d3272 /drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | |
| parent | 809fe88d83434b88899425511e86e7edf354ce6d (diff) | |
drm/amd/display: Add DCN3.1 HDCP support
New DTM interface is V3 and we need to extend our existing support
to enable HDCP on DCN3.1.
Version the helpers and fallback to the older versions on failure
in the new interfaces.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h index acbeada5215b..2197c269e0a7 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -97,6 +97,9 @@ enum mod_hdcp_status { MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST, MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE, MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE, +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE, +#endif }; struct mod_hdcp_displayport { @@ -120,6 +123,13 @@ enum mod_hdcp_display_state { MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED }; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) +struct mod_hdcp_psp_caps { + uint8_t dtm_v3_supported; + uint8_t opm_state_query_supported; +}; + +#endif enum mod_hdcp_display_disable_option { MOD_HDCP_DISPLAY_NOT_DISABLE = 0, MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION, @@ -152,6 +162,9 @@ struct mod_hdcp_ddc { struct mod_hdcp_psp { void *handle; void *funcs; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + struct mod_hdcp_psp_caps caps; +#endif }; struct mod_hdcp_display_adjustment { @@ -227,6 +240,9 @@ struct mod_hdcp_display { uint8_t index; uint8_t controller; uint8_t dig_fe; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + uint8_t stream_enc_idx; +#endif union { uint8_t vc_id; }; @@ -239,6 +255,11 @@ struct mod_hdcp_link { enum mod_hdcp_operation_mode mode; uint8_t dig_be; uint8_t ddc_line; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + uint8_t link_enc_idx; + uint8_t phy_idx; + uint8_t hdcp_supported_informational; +#endif union { struct mod_hdcp_displayport dp; struct mod_hdcp_hdmi hdmi; |