diff options
| author | Tao Zhou <tao.zhou1@amd.com> | 2018-10-09 11:30:36 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-10-10 14:47:32 -0500 |
| commit | 04e7580f892688aff140c574dbefa707977375e7 (patch) | |
| tree | c52a03b93290c60605827edd529798e19a08132f /drivers/gpu/drm/amd/include/asic_reg/gc | |
| parent | 66f34aeec2510b755e8b928b0d8aec8a4095a227 (diff) | |
drm/amdgpu: add CP_DEBUG register definition for GC9.0
Add CP_DEBUG register definition.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/gc')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index 4ce090db7ef7..529b37db274c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -2449,6 +2449,8 @@ #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 #define mmGB_EDC_MODE 0x107e #define mmGB_EDC_MODE_BASE_IDX 0 +#define mmCP_DEBUG 0x107f +#define mmCP_DEBUG_BASE_IDX 0 #define mmCP_CPF_DEBUG 0x1080 #define mmCP_PQ_WPTR_POLL_CNTL 0x1083 #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 |