diff options
| author | Feifei Xu <Feifei.Xu@amd.com> | 2020-11-19 18:12:26 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 22:54:49 -0400 |
| commit | 5c03e5843e6bd1e6f2271a54c9b30524ba78bb8f (patch) | |
| tree | b82f270e2f490bdcc81dc3d98e146c13911dccb0 /drivers/gpu/drm/amd/pm/inc | |
| parent | 4c2e5f513e950038c594df04ae2cc511fa854ccb (diff) | |
drm/amdgpu:add smu mode1/2 support for aldebaran
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h | 25 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/smu_v13_0.h | 1 |
4 files changed, 28 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h index 302888376c7c..433dd1e9ec4f 100644 --- a/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h @@ -36,7 +36,7 @@ // Message Definitions: #define PPSMC_MSG_TestMessage 0x1 #define PPSMC_MSG_GetSmuVersion 0x2 -#define PPSMC_MSG_Mode1Reset 0x3 +#define PPSMC_MSG_GfxDriverReset 0x3 #define PPSMC_MSG_GetDriverIfVersion 0x4 #define PPSMC_MSG_spare1 0x5 #define PPSMC_MSG_spare2 0x6 @@ -70,8 +70,8 @@ #define PPSMC_MSG_SetPptLimit 0x22 #define PPSMC_MSG_GetPptLimit 0x23 #define PPSMC_MSG_PrepareMp1ForUnload 0x24 -#define PPSMC_MSG_PrepareMp1ForReset 0x25 -#define PPSMC_MSG_SoftReset 0x26 +#define PPSMC_MSG_PrepareMp1ForReset 0x25 //retired in 68.07 +#define PPSMC_MSG_SoftReset 0x26 //retired in 68.07 #define PPSMC_MSG_RunDcBtc 0x27 #define PPSMC_MSG_DramLogSetDramAddrHigh 0x28 #define PPSMC_MSG_DramLogSetDramAddrLow 0x29 @@ -92,7 +92,24 @@ #define PPSMC_MSG_DisableDeterminism 0x3A #define PPSMC_MSG_SetUclkDpmMode 0x3B -#define PPSMC_Message_Count 0x3C +//STB to dram log +#define PPSMC_MSG_DumpSTBtoDram 0x3C +#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3D +#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3E +#define PPSMC_MSG_STBtoDramLogSetDramSize 0x3F +#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x40 +#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41 + +#define PPSMC_Message_Count 0x42 + +//PPSMC Reset Types +#define PPSMC_RESET_TYPE_WARM_RESET 0x00 +#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x01 //driver msg argument should be 1 for mode-1 +#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET 0x02 //and 2 for mode-2 +#define PPSMC_RESET_TYPE_PCIE_LINK_RESET 0x03 +#define PPSMC_RESET_TYPE_BIF_LINK_RESET 0x04 +#define PPSMC_RESET_TYPE_PF0_FLR_RESET 0x05 + typedef enum { GFXOFF_ERROR_NO_ERROR, diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 2b4308c025dd..c02ffbd1df76 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -1044,6 +1044,10 @@ struct pptable_funcs { * @mode1_reset_is_support: Check if GPU supports mode1 reset. */ bool (*mode1_reset_is_support)(struct smu_context *smu); + /** + * @mode2_reset_is_support: Check if GPU supports mode2 reset. + */ + bool (*mode2_reset_is_support)(struct smu_context *smu); /** * @mode1_reset: Perform mode1 reset. @@ -1279,6 +1283,7 @@ int smu_baco_set_state(void *handle, int state); bool smu_mode1_reset_is_support(struct smu_context *smu); +bool smu_mode2_reset_is_support(struct smu_context *smu); int smu_mode1_reset(struct smu_context *smu); int smu_mode2_reset(void *handle); diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index e9a0bda98fd7..207d5d923c9e 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -184,6 +184,7 @@ __SMU_DUMMY_MAP(GET_UMC_FW_WA), \ __SMU_DUMMY_MAP(Mode1Reset), \ __SMU_DUMMY_MAP(RlcPowerNotify), \ + __SMU_DUMMY_MAP(GfxDriverReset), \ __SMU_DUMMY_MAP(SetHardMinIspiclkByFreq), \ __SMU_DUMMY_MAP(SetHardMinIspxclkByFreq), \ __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \ diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h index 699b656bbd71..ef9dad9a51ff 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h @@ -220,6 +220,7 @@ int smu_v13_0_baco_enter(struct smu_context *smu); int smu_v13_0_baco_exit(struct smu_context *smu); int smu_v13_0_mode1_reset(struct smu_context *smu); +int smu_v13_0_mode2_reset(struct smu_context *smu); int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); |