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authorEvan Quan <evan.quan@amd.com>2020-06-10 16:15:26 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-15 12:42:46 -0400
commit62cc9dd1826f85c037df706315172854c7d1cd10 (patch)
tree97a1c3e68fbc7b97088c41ee0dc10898b60df480 /drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
parentb64d86889f1e66190fa54a9626a1333dd653bad6 (diff)
drm/amd/powerplay: update UMD pstate clock settings
Preparing for coming code sharing around performance level setting. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/arcturus_ppt.c')
-rw-r--r--drivers/gpu/drm/amd/powerplay/arcturus_ppt.c47
1 files changed, 32 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a3747ab4af32..33d472ffb2be 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -548,27 +548,44 @@ static int arcturus_run_btc(struct smu_context *smu)
static int arcturus_populate_umd_state_clk(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
- struct arcturus_dpm_table *dpm_table = NULL;
- struct arcturus_single_dpm_table *gfx_table = NULL;
- struct arcturus_single_dpm_table *mem_table = NULL;
+ struct smu_11_0_dpm_context *dpm_context =
+ smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_table =
+ &dpm_context->dpm_tables.gfx_table;
+ struct smu_11_0_dpm_table *mem_table =
+ &dpm_context->dpm_tables.uclk_table;
+ struct smu_11_0_dpm_table *soc_table =
+ &dpm_context->dpm_tables.soc_table;
+ struct smu_umd_pstate_table *pstate_table =
+ &smu->pstate_table;
+
+ pstate_table->gfxclk_pstate.min = gfx_table->min;
+ pstate_table->gfxclk_pstate.peak = gfx_table->max;
- dpm_table = smu_dpm->dpm_context;
- gfx_table = &(dpm_table->gfx_table);
- mem_table = &(dpm_table->mem_table);
+ pstate_table->uclk_pstate.min = mem_table->min;
+ pstate_table->uclk_pstate.peak = mem_table->max;
- smu->pstate_sclk = gfx_table->dpm_levels[0].value;
- smu->pstate_mclk = mem_table->dpm_levels[0].value;
+ pstate_table->socclk_pstate.min = soc_table->min;
+ pstate_table->socclk_pstate.peak = soc_table->max;
if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
- mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
- smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
- smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+ mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
+ soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
+ pstate_table->gfxclk_pstate.standard =
+ gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
+ pstate_table->uclk_pstate.standard =
+ mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+ pstate_table->socclk_pstate.standard =
+ soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
+ } else {
+ pstate_table->gfxclk_pstate.standard =
+ pstate_table->gfxclk_pstate.min;
+ pstate_table->uclk_pstate.standard =
+ pstate_table->uclk_pstate.min;
+ pstate_table->socclk_pstate.standard =
+ pstate_table->socclk_pstate.min;
}
- smu->pstate_sclk = smu->pstate_sclk * 100;
- smu->pstate_mclk = smu->pstate_mclk * 100;
-
return 0;
}