diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2018-02-24 19:53:41 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-06 13:12:38 -0500 |
commit | a5278e511dce23349e71d681dfa7e8c600d19603 (patch) | |
tree | d6c0db8c32e0de35300c7d7e2db6f6a9b6905613 /drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | |
parent | 180a8bebdd50fc8ce4677e579d49d9b73880caa7 (diff) |
drm/amd/pp: Revert gfx/compute profile switch sysfs
The gfx/compute profiling mode switch is only for internally
test. Not a complete solution and unexpectly upstream.
so revert it.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 86 |
1 files changed, 0 insertions, 86 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 1596fd84627a..d90a0f1dbb55 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -2408,34 +2408,6 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) return result; } -static int vega10_save_default_power_profile(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); - uint32_t min_level; - - hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; - hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; - - /* Optimize compute power profile: Use only highest - * 2 power levels (if more than 2 are available) - */ - if (dpm_table->count > 2) - min_level = dpm_table->count - 2; - else if (dpm_table->count == 2) - min_level = 1; - else - min_level = 0; - - hwmgr->default_compute_power_profile.min_sclk = - dpm_table->dpm_levels[min_level].value; - - hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; - hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; - - return 0; -} - /** * Initializes the SMC table and uploads it * @@ -2579,7 +2551,6 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", return result); vega10_acg_enable(hwmgr); - vega10_save_default_power_profile(hwmgr); return 0; } @@ -4754,62 +4725,6 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) return result; } -static void vega10_find_min_clock_index(struct pp_hwmgr *hwmgr, - uint32_t *sclk_idx, uint32_t *mclk_idx, - uint32_t min_sclk, uint32_t min_mclk) -{ - struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - struct vega10_dpm_table *dpm_table = &(data->dpm_table); - uint32_t i; - - for (i = 0; i < dpm_table->gfx_table.count; i++) { - if (dpm_table->gfx_table.dpm_levels[i].enabled && - dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { - *sclk_idx = i; - break; - } - } - - for (i = 0; i < dpm_table->mem_table.count; i++) { - if (dpm_table->mem_table.dpm_levels[i].enabled && - dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { - *mclk_idx = i; - break; - } - } -} - -static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, - struct amd_pp_profile *request) -{ - struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - uint32_t sclk_idx = ~0, mclk_idx = ~0; - - if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) - return -EINVAL; - - vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx, - request->min_sclk, request->min_mclk); - - if (sclk_idx != ~0) { - if (!data->registry_data.sclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter( - hwmgr, - PPSMC_MSG_SetSoftMinGfxclkByIndex, - sclk_idx); - } - - if (mclk_idx != ~0) { - if (!data->registry_data.mclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter( - hwmgr, - PPSMC_MSG_SetSoftMinUclkByIndex, - mclk_idx); - } - - return 0; -} - static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); @@ -5103,7 +5018,6 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = { vega10_check_smc_update_required_for_display_configuration, .power_off_asic = vega10_power_off_asic, .disable_smc_firmware_ctf = vega10_thermal_disable_alert, - .set_power_profile_state = vega10_set_power_profile_state, .get_sclk_od = vega10_get_sclk_od, .set_sclk_od = vega10_set_sclk_od, .get_mclk_od = vega10_get_mclk_od, |