diff options
| author | Rex Zhu <Rex.Zhu@amd.com> | 2018-02-22 17:20:53 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-26 23:09:40 -0500 |
| commit | d246cd53fd6a6bffc9e4dcf045d8031f445353fb (patch) | |
| tree | 1dfb49a231a3f97a9a64ffb3ad109d921c2b00a7 /drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | |
| parent | baeb7721b1a60ab86164ed746db522591c4540cb (diff) | |
drm/amd/pp: Remove dead error checking code on Vega10
when smu failed, print out the error info immediately
for debug. smum_send_msg_to_smu always return true,
so no need to check return value.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c index 981c9e5431da..f5ed171d6940 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c @@ -850,7 +850,6 @@ static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) { uint32_t data; - int result; uint32_t en = (enable ? 1 : 0); uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; @@ -924,11 +923,10 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) } } - if (enable) { - /* For Vega10, SMC does not support any mask yet. */ - result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); - PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!"); - } + /* For Vega10, SMC does not support any mask yet. */ + if (enable) + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); + } static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) @@ -1344,7 +1342,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) (struct vega10_hwmgr *)(hwmgr->backend); if (data->registry_data.enable_pkg_pwr_tracking_feature) - return smum_send_msg_to_smc_with_parameter(hwmgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetPptLimit, n); return 0; @@ -1406,24 +1404,24 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) return 0; } -static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, +static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, uint32_t adjust_percent) { - return smum_send_msg_to_smc_with_parameter(hwmgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_OverDriveSetPercentage, adjust_percent); } int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) { - int adjust_percent, result = 0; + int adjust_percent; if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? hwmgr->platform_descriptor.TDPAdjustment : (-1 * hwmgr->platform_descriptor.TDPAdjustment); - result = vega10_set_overdrive_target_percentage(hwmgr, + vega10_set_overdrive_target_percentage(hwmgr, (uint32_t)adjust_percent); } - return result; + return 0; } |