diff options
author | Evan Quan <evan.quan@amd.com> | 2020-08-13 16:39:25 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-14 16:22:41 -0400 |
commit | e098bc9612c2b60f94920461d71c92962a916e73 (patch) | |
tree | 9523440f73a9db1943a4102da7b5ef4c5fb15ca4 /drivers/gpu/drm/amd/powerplay/hwmgr | |
parent | e9372d23715d6802fd6d3763cb19c5a0c07ad641 (diff) |
drm/amd/pm: optimize the power related source code layout
The target is to provide a clear entry point(for power routines).
Also this can help to maintain a clear view about the frameworks
used on different ASICs. Hopefully all these can make power part
more friendly to play with.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr')
84 files changed, 0 insertions, 46022 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile deleted file mode 100644 index 2773966ae434..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2017 Advanced Micro Devices, Inc. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -# OTHER DEALINGS IN THE SOFTWARE. -# -# -# Makefile for the 'hw manager' sub-component of powerplay. -# It provides the hardware management services for the driver. - -HARDWARE_MGR = hwmgr.o processpptables.o \ - hardwaremanager.o smu8_hwmgr.o \ - pppcielanes.o\ - process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \ - smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ - smu7_clockpowergating.o \ - vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \ - vega10_thermal.o smu10_hwmgr.o pp_psm.o\ - vega12_processpptables.o vega12_hwmgr.o \ - vega12_thermal.o \ - pp_overdriver.o smu_helper.o \ - vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ - vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \ - vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \ - ci_baco.o smu7_baco.o - -AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) - -AMD_POWERPLAY_FILES += $(AMD_PP_HWMGR) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c deleted file mode 100644 index 3be40114e63d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "ci_baco.h" - -#include "gmc/gmc_7_1_d.h" -#include "gmc/gmc_7_1_sh_mask.h" - -#include "bif/bif_4_1_d.h" -#include "bif/bif_4_1_sh_mask.h" - -#include "dce/dce_8_0_d.h" -#include "dce/dce_8_0_sh_mask.h" - -#include "smu/smu_7_0_1_d.h" -#include "smu/smu_7_0_1_sh_mask.h" - -#include "gca/gfx_7_2_d.h" -#include "gca/gfx_7_2_sh_mask.h" - -static const struct baco_cmd_entry gpio_tbl[] = -{ - { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, - { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, - { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, - { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } -}; - -static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, - { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } -}; - -static const struct baco_cmd_entry use_bclk_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 } -}; - -static const struct baco_cmd_entry turn_off_plls_tbl[] = -{ - { CMD_READMODIFYWRITE, mmDISPPLL_BG_CNTL, DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK, DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_DC }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__OSC_EN_MASK, CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK, CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_RESET_MASK, PLL_CNTL__PLL_RESET__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_POWER_DOWN_MASK, PLL_CNTL__PLL_POWER_DOWN__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_BYPASS_CAL_MASK, PLL_CNTL__PLL_BYPASS_CAL__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 }, - { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT, 0, 0x2 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x2 } -}; - -static const struct baco_cmd_entry enter_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } -}; - -#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK - -static const struct baco_cmd_entry exit_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, - { CMD_DELAY_MS, 0, 0, 0, 20, 0 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x20 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x10 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } -}; - -static const struct baco_cmd_entry clean_baco_tbl[] = -{ - { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, - { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 } -}; - -int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - enum BACO_STATE cur_state; - - smu7_baco_get_state(hwmgr, &cur_state); - - if (cur_state == state) - /* aisc already in the target state */ - return 0; - - if (state == BACO_STATE_IN) { - baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); - baco_program_registers(hwmgr, enable_fb_req_rej_tbl, - ARRAY_SIZE(enable_fb_req_rej_tbl)); - baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); - baco_program_registers(hwmgr, turn_off_plls_tbl, - ARRAY_SIZE(turn_off_plls_tbl)); - if (baco_program_registers(hwmgr, enter_baco_tbl, - ARRAY_SIZE(enter_baco_tbl))) - return 0; - - } else if (state == BACO_STATE_OUT) { - /* HW requires at least 20ms between regulator off and on */ - msleep(20); - /* Execute Hardware BACO exit sequence */ - if (baco_program_registers(hwmgr, exit_baco_tbl, - ARRAY_SIZE(exit_baco_tbl))) { - if (baco_program_registers(hwmgr, clean_baco_tbl, - ARRAY_SIZE(clean_baco_tbl))) - return 0; - } - } - - return -EINVAL; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h deleted file mode 100644 index 17041f187020..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __CI_BACO_H__ -#define __CI_BACO_H__ -#include "smu7_baco.h" - -extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c deleted file mode 100644 index 1c73776bd606..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "common_baco.h" - - -static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - u32 timeout = 5000, data; - - do { - msleep(1); - data = RREG32(reg); - timeout--; - } while (value != (data & mask) && (timeout != 0)); - - if (timeout == 0) - return false; - - return true; -} - -static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask, - u32 shift, u32 value, u32 timeout) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - u32 data; - bool ret = true; - - switch (command) { - case CMD_WRITE: - WREG32(reg, value << shift); - break; - case CMD_READMODIFYWRITE: - data = RREG32(reg); - data = (data & (~mask)) | (value << shift); - WREG32(reg, data); - break; - case CMD_WAITFOR: - ret = baco_wait_register(hwmgr, reg, mask, value); - break; - case CMD_DELAY_MS: - if (timeout) - /* Delay in milli Seconds */ - msleep(timeout); - break; - case CMD_DELAY_US: - if (timeout) - /* Delay in micro Seconds */ - udelay(timeout); - break; - - default: - dev_warn(adev->dev, "Invalid BACO command.\n"); - ret = false; - } - - return ret; -} - -bool baco_program_registers(struct pp_hwmgr *hwmgr, - const struct baco_cmd_entry *entry, - const u32 array_size) -{ - u32 i, reg = 0; - - for (i = 0; i < array_size; i++) { - if ((entry[i].cmd == CMD_WRITE) || - (entry[i].cmd == CMD_READMODIFYWRITE) || - (entry[i].cmd == CMD_WAITFOR)) - reg = entry[i].reg_offset; - if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask, - entry[i].shift, entry[i].val, entry[i].timeout)) - return false; - } - - return true; -} - -bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr, - const struct soc15_baco_cmd_entry *entry, - const u32 array_size) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - u32 i, reg = 0; - - for (i = 0; i < array_size; i++) { - if ((entry[i].cmd == CMD_WRITE) || - (entry[i].cmd == CMD_READMODIFYWRITE) || - (entry[i].cmd == CMD_WAITFOR)) - reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] - + entry[i].reg_offset; - if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask, - entry[i].shift, entry[i].val, entry[i].timeout)) - return false; - } - - return true; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h deleted file mode 100644 index 8393eb62706d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __COMMON_BOCO_H__ -#define __COMMON_BOCO_H__ -#include "hwmgr.h" - - -enum baco_cmd_type { - CMD_WRITE = 0, - CMD_READMODIFYWRITE, - CMD_WAITFOR, - CMD_DELAY_MS, - CMD_DELAY_US, -}; - -struct baco_cmd_entry { - enum baco_cmd_type cmd; - uint32_t reg_offset; - uint32_t mask; - uint32_t shift; - uint32_t timeout; - uint32_t val; -}; - -struct soc15_baco_cmd_entry { - enum baco_cmd_type cmd; - uint32_t hwip; - uint32_t inst; - uint32_t seg; - uint32_t reg_offset; - uint32_t mask; - uint32_t shift; - uint32_t timeout; - uint32_t val; -}; - -extern bool baco_program_registers(struct pp_hwmgr *hwmgr, - const struct baco_cmd_entry *entry, - const u32 array_size); -extern bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr, - const struct soc15_baco_cmd_entry *entry, - const u32 array_size); -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c deleted file mode 100644 index c0368f2dfb21..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "fiji_baco.h" - -#include "gmc/gmc_8_1_d.h" -#include "gmc/gmc_8_1_sh_mask.h" - -#include "bif/bif_5_0_d.h" -#include "bif/bif_5_0_sh_mask.h" - -#include "dce/dce_10_0_d.h" -#include "dce/dce_10_0_sh_mask.h" - -#include "smu/smu_7_1_3_d.h" -#include "smu/smu_7_1_3_sh_mask.h" - - -static const struct baco_cmd_entry gpio_tbl[] = -{ - { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, - { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, - { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, - { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } -}; - -static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, - { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } -}; - -static const struct baco_cmd_entry use_bclk_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 } -}; - -static const struct baco_cmd_entry turn_off_plls_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 } -}; - -static const struct baco_cmd_entry clk_req_b_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 } -}; - -static const struct baco_cmd_entry enter_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } -}; - -#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK - -static const struct baco_cmd_entry exit_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } -}; - -static const struct baco_cmd_entry clean_baco_tbl[] = -{ - { CMD_WRITE, mmBIOS_SCRATCH_0, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_1, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_2, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_3, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_4, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_5, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_8, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_9, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_10, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_11, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_12, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_13, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_14, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 } -}; - -int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - enum BACO_STATE cur_state; - - smu7_baco_get_state(hwmgr, &cur_state); - - if (cur_state == state) - /* aisc already in the target state */ - return 0; - - if (state == BACO_STATE_IN) { - baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); - baco_program_registers(hwmgr, enable_fb_req_rej_tbl, - ARRAY_SIZE(enable_fb_req_rej_tbl)); - baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); - baco_program_registers(hwmgr, turn_off_plls_tbl, - ARRAY_SIZE(turn_off_plls_tbl)); - baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl)); - if (baco_program_registers(hwmgr, enter_baco_tbl, - ARRAY_SIZE(enter_baco_tbl))) - return 0; - - } else if (state == BACO_STATE_OUT) { - /* HW requires at least 20ms between regulator off and on */ - msleep(20); - /* Execute Hardware BACO exit sequence */ - if (baco_program_registers(hwmgr, exit_baco_tbl, - ARRAY_SIZE(exit_baco_tbl))) { - if (baco_program_registers(hwmgr, clean_baco_tbl, - ARRAY_SIZE(clean_baco_tbl))) - return 0; - } - } - - return -EINVAL; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h deleted file mode 100644 index 47f402900bdb..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __FIJI_BACO_H__ -#define __FIJI_BACO_H__ -#include "smu7_baco.h" - -extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c deleted file mode 100644 index 9454ab50f9a1..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include <linux/errno.h> -#include "hwmgr.h" -#include "hardwaremanager.h" -#include "power_state.h" - - -#define TEMP_RANGE_MIN (0) -#define TEMP_RANGE_MAX (80 * 1000) - -#define PHM_FUNC_CHECK(hw) \ - do { \ - if ((hw) == NULL || (hw)->hwmgr_func == NULL) \ - return -EINVAL; \ - } while (0) - -int phm_setup_asic(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (NULL != hwmgr->hwmgr_func->asic_setup) - return hwmgr->hwmgr_func->asic_setup(hwmgr); - - return 0; -} - -int phm_power_down_asic(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (NULL != hwmgr->hwmgr_func->power_off_asic) - return hwmgr->hwmgr_func->power_off_asic(hwmgr); - - return 0; -} - -int phm_set_power_state(struct pp_hwmgr *hwmgr, - const struct pp_hw_power_state *pcurrent_state, - const struct pp_hw_power_state *pnew_power_state) -{ - struct phm_set_power_state_input states; - - PHM_FUNC_CHECK(hwmgr); - - states.pcurrent_state = pcurrent_state; - states.pnew_state = pnew_power_state; - - if (NULL != hwmgr->hwmgr_func->power_state_set) - return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); - - return 0; -} - -int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = NULL; - int ret = -EINVAL; - PHM_FUNC_CHECK(hwmgr); - adev = hwmgr->adev; - - /* Skip for suspend/resume case */ - if (!hwmgr->pp_one_vf && smum_is_dpm_running(hwmgr) - && !amdgpu_passthrough(adev) && adev->in_suspend) { - pr_info("dpm has been enabled\n"); - return 0; - } - - if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) - ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); - - return ret; -} - -int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) -{ - int ret = -EINVAL; - - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->not_vf) - return 0; - - if (!smum_is_dpm_running(hwmgr)) { - pr_info("dpm has been disabled\n"); - return 0; - } - - if (hwmgr->hwmgr_func->dynamic_state_management_disable) - ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); - - return ret; -} - -int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) -{ - int ret = 0; - - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->force_dpm_level != NULL) - ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); - - return ret; -} - -int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, - struct pp_power_state *adjusted_ps, - const struct pp_power_state *current_ps) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL) - return hwmgr->hwmgr_func->apply_state_adjust_rules( - hwmgr, - adjusted_ps, - current_ps); - return 0; -} - -int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL) - return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr); - return 0; -} - -int phm_powerdown_uvd(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->powerdown_uvd != NULL) - return hwmgr->hwmgr_func->powerdown_uvd(hwmgr); - return 0; -} - - -int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) - return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); - - return 0; -} - -int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (NULL != hwmgr->hwmgr_func->pre_display_config_changed) - hwmgr->hwmgr_func->pre_display_config_changed(hwmgr); - - return 0; - -} - -int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (NULL != hwmgr->hwmgr_func->display_config_changed) - hwmgr->hwmgr_func->display_config_changed(hwmgr); - - return 0; -} - -int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) - hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); - - return 0; -} - -int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->not_vf) - return 0; - - if (hwmgr->hwmgr_func->stop_thermal_controller == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr); -} - -int phm_register_irq_handlers(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->register_irq_handlers != NULL) - return hwmgr->hwmgr_func->register_irq_handlers(hwmgr); - - return 0; -} - -/** -* Initializes the thermal controller subsystem. -* -* @param pHwMgr the address of the powerplay hardware manager. -* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher. -*/ -int phm_start_thermal_controller(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - struct PP_TemperatureRange range = { - TEMP_RANGE_MIN, - TEMP_RANGE_MAX, - TEMP_RANGE_MAX, - TEMP_RANGE_MIN, - TEMP_RANGE_MAX, - TEMP_RANGE_MAX, - TEMP_RANGE_MIN, - TEMP_RANGE_MAX, - TEMP_RANGE_MAX}; - struct amdgpu_device *adev = hwmgr->adev; - - if (!hwmgr->not_vf) - return 0; - - if (hwmgr->hwmgr_func->get_thermal_temperature_range) - hwmgr->hwmgr_func->get_thermal_temperature_range( - hwmgr, &range); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController) - && hwmgr->hwmgr_func->start_thermal_controller != NULL) - ret = hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range); - - adev->pm.dpm.thermal.min_temp = range.min; - adev->pm.dpm.thermal.max_temp = range.max; - adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max; - adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; - adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max; - adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max; - adev->pm.dpm.thermal.min_mem_temp = range.mem_min; - adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max; - adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max; - - return ret; -} - - -bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - if (hwmgr->pp_one_vf) - return false; - - if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL) - return false; - - return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr); -} - - -int phm_check_states_equal(struct pp_hwmgr *hwmgr, - const struct pp_hw_power_state *pstate1, - const struct pp_hw_power_state *pstate2, - bool *equal) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->check_states_equal == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal); -} - -int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, - const struct amd_pp_display_configuration *display_config) -{ - int index = 0; - int number_of_active_display = 0; - - PHM_FUNC_CHECK(hwmgr); - - if (display_config == NULL) - return -EINVAL; - - if (NULL != hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk) - hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); - - for (index = 0; index < display_config->num_path_including_non_display; index++) { - if (display_config->displays[index].controller_id != 0) - number_of_active_display++; - } - - if (NULL != hwmgr->hwmgr_func->set_active_display_count) - hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display); - - if (hwmgr->hwmgr_func->store_cc6_data == NULL) - return -EINVAL; - - /* TODO: pass other display configuration in the future */ - - if (hwmgr->hwmgr_func->store_cc6_data) - hwmgr->hwmgr_func->store_cc6_data(hwmgr, - display_config->cpu_pstate_separation_time, - display_config->cpu_cc6_disable, - display_config->cpu_pstate_disable, - display_config->nb_pstate_switch_disable); - - return 0; -} - -int phm_get_dal_power_level(struct pp_hwmgr *hwmgr, - struct amd_pp_simple_clock_info *info) -{ - PHM_FUNC_CHECK(hwmgr); - - if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL) - return -EINVAL; - return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info); -} - -int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->set_cpu_power_state != NULL) - return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr); - - return 0; -} - - -int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, - PHM_PerformanceLevelDesignation designation, uint32_t index, - PHM_PerformanceLevel *level) -{ - PHM_FUNC_CHECK(hwmgr); - if (hwmgr->hwmgr_func->get_performance_level == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level); - - -} - - -/** -* Gets Clock Info. -* -* @param pHwMgr the address of the powerplay hardware manager. -* @param pPowerState the address of the Power State structure. -* @param pClockInfo the address of PP_ClockInfo structure where the result will be returned. -* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end. -*/ -int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info, - PHM_PerformanceLevelDesignation designation) -{ - int result; - PHM_PerformanceLevel performance_level = {0}; - - PHM_FUNC_CHECK(hwmgr); - - PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL); - PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL); - - result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level); - - PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result); - - - pclock_info->min_mem_clk = performance_level.memory_clock; - pclock_info->min_eng_clk = performance_level.coreClock; - pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth; - - - result = phm_get_performance_level(hwmgr, state, designation, - (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level); - - PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result); - - pclock_info->max_mem_clk = performance_level.memory_clock; - pclock_info->max_eng_clk = performance_level.coreClock; - pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth; - - return 0; -} - -int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info); - -} - -int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->get_clock_by_type == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks); - -} - -int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks); - -} - -int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks); - -} - -int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, - void *clock_ranges) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges) - return -EINVAL; - - return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr, - clock_ranges); -} - -int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr, - struct pp_display_clock_request *clock) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->hwmgr_func->display_clock_voltage_request) - return -EINVAL; - - return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock); -} - -int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->get_max_high_clocks == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks); -} - -int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->not_vf) - return 0; - - if (hwmgr->hwmgr_func->disable_smc_firmware_ctf == NULL) - return -EINVAL; - - return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr); -} - -int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->hwmgr_func->set_active_display_count) - return -EINVAL; - - return hwmgr->hwmgr_func->set_active_display_count(hwmgr, count); -} - -int phm_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk) - return -EINVAL; - - return hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); -} - -int phm_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq) - return -EINVAL; - - return hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); -} - -int phm_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) -{ - PHM_FUNC_CHECK(hwmgr); - - if (!hwmgr->hwmgr_func->set_hard_min_fclk_by_freq) - return -EINVAL; - - return hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c deleted file mode 100644 index f48fdc7f0382..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ /dev/null @@ -1,564 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "pp_debug.h" -#include <linux/delay.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <drm/amdgpu_drm.h> -#include "power_state.h" -#include "hwmgr.h" -#include "ppsmc.h" -#include "amd_acpi.h" -#include "pp_psm.h" - -extern const struct pp_smumgr_func ci_smu_funcs; -extern const struct pp_smumgr_func smu8_smu_funcs; -extern const struct pp_smumgr_func iceland_smu_funcs; -extern const struct pp_smumgr_func tonga_smu_funcs; -extern const struct pp_smumgr_func fiji_smu_funcs; -extern const struct pp_smumgr_func polaris10_smu_funcs; -extern const struct pp_smumgr_func vegam_smu_funcs; -extern const struct pp_smumgr_func vega10_smu_funcs; -extern const struct pp_smumgr_func vega12_smu_funcs; -extern const struct pp_smumgr_func smu10_smu_funcs; -extern const struct pp_smumgr_func vega20_smu_funcs; - -extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr); -extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr); -extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr); -extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr); -extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr); -extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr); - -static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr); -static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr); -static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr); -static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr); -static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr); -static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr); -static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr); - - -static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr) -{ - hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; - hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; - hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; - hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; - hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; - hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; - - hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; - hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; - hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; - hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; - hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; -} - -int hwmgr_early_init(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev; - - if (!hwmgr) - return -EINVAL; - - hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; - hwmgr->pp_table_version = PP_TABLE_V1; - hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; - hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; - hwmgr_init_default_caps(hwmgr); - hwmgr_set_user_specify_caps(hwmgr); - hwmgr->fan_ctrl_is_in_default_mode = true; - hwmgr_init_workload_prority(hwmgr); - hwmgr->gfxoff_state_changed_by_workload = false; - - adev = hwmgr->adev; - - switch (hwmgr->chip_family) { - case AMDGPU_FAMILY_CI: - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; - hwmgr->smumgr_funcs = &ci_smu_funcs; - ci_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | - PP_ENABLE_GFX_CG_THRU_SMU | - PP_GFXOFF_MASK); - hwmgr->pp_table_version = PP_TABLE_V0; - hwmgr->od_enabled = false; - smu7_init_function_pointers(hwmgr); - break; - case AMDGPU_FAMILY_CZ: - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; - hwmgr->od_enabled = false; - hwmgr->smumgr_funcs = &smu8_smu_funcs; - hwmgr->feature_mask &= ~PP_GFXOFF_MASK; - smu8_init_function_pointers(hwmgr); - break; - case AMDGPU_FAMILY_VI: - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; - hwmgr->feature_mask &= ~PP_GFXOFF_MASK; - switch (hwmgr->chip_id) { - case CHIP_TOPAZ: - hwmgr->smumgr_funcs = &iceland_smu_funcs; - topaz_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | - PP_ENABLE_GFX_CG_THRU_SMU); - hwmgr->pp_table_version = PP_TABLE_V0; - hwmgr->od_enabled = false; - break; - case CHIP_TONGA: - hwmgr->smumgr_funcs = &tonga_smu_funcs; - tonga_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; - break; - case CHIP_FIJI: - hwmgr->smumgr_funcs = &fiji_smu_funcs; - fiji_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | - PP_ENABLE_GFX_CG_THRU_SMU); - break; - case CHIP_POLARIS11: - case CHIP_POLARIS10: - case CHIP_POLARIS12: - hwmgr->smumgr_funcs = &polaris10_smu_funcs; - polaris_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); - break; - case CHIP_VEGAM: - hwmgr->smumgr_funcs = &vegam_smu_funcs; - polaris_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); - break; - default: - return -EINVAL; - } - smu7_init_function_pointers(hwmgr); - break; - case AMDGPU_FAMILY_AI: - switch (hwmgr->chip_id) { - case CHIP_VEGA10: - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; - hwmgr->feature_mask &= ~PP_GFXOFF_MASK; - hwmgr->smumgr_funcs = &vega10_smu_funcs; - vega10_hwmgr_init(hwmgr); - break; - case CHIP_VEGA12: - hwmgr->smumgr_funcs = &vega12_smu_funcs; - vega12_hwmgr_init(hwmgr); - break; - case CHIP_VEGA20: - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; - hwmgr->feature_mask &= ~PP_GFXOFF_MASK; - hwmgr->smumgr_funcs = &vega20_smu_funcs; - vega20_hwmgr_init(hwmgr); - break; - default: - return -EINVAL; - } - break; - case AMDGPU_FAMILY_RV: - switch (hwmgr->chip_id) { - case CHIP_RAVEN: - hwmgr->od_enabled = false; - hwmgr->smumgr_funcs = &smu10_smu_funcs; - smu10_init_function_pointers(hwmgr); - break; - default: - return -EINVAL; - } - break; - default: - return -EINVAL; - } - - return 0; -} - -int hwmgr_sw_init(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init) - return -EINVAL; - - phm_register_irq_handlers(hwmgr); - pr_info("hwmgr_sw_init smu backed is %s\n", hwmgr->smumgr_funcs->name); - - return hwmgr->smumgr_funcs->smu_init(hwmgr); -} - - -int hwmgr_sw_fini(struct pp_hwmgr *hwmgr) -{ - if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini) - hwmgr->smumgr_funcs->smu_fini(hwmgr); - - return 0; -} - -int hwmgr_hw_init(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - - hwmgr->pp_one_vf = amdgpu_sriov_is_pp_one_vf((struct amdgpu_device *)hwmgr->adev); - hwmgr->pm_en = (amdgpu_dpm && (hwmgr->not_vf || hwmgr->pp_one_vf)) - ? true : false; - if (!hwmgr->pm_en) - return 0; - - if (!hwmgr->pptable_func || - !hwmgr->pptable_func->pptable_init || - !hwmgr->hwmgr_func->backend_init) { - hwmgr->pm_en = false; - pr_info("dpm not supported \n"); - return 0; - } - - ret = hwmgr->pptable_func->pptable_init(hwmgr); - if (ret) - goto err; - - ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan = - hwmgr->thermal_controller.fanInfo.bNoFan; - - ret = hwmgr->hwmgr_func->backend_init(hwmgr); - if (ret) - goto err1; - /* make sure dc limits are valid */ - if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || - (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) - hwmgr->dyn_state.max_clock_voltage_on_dc = - hwmgr->dyn_state.max_clock_voltage_on_ac; - - ret = psm_init_power_state_table(hwmgr); - if (ret) - goto err2; - - ret = phm_setup_asic(hwmgr); - if (ret) - goto err2; - - ret = phm_enable_dynamic_state_management(hwmgr); - if (ret) - goto err2; - ret = phm_start_thermal_controller(hwmgr); - ret |= psm_set_performance_states(hwmgr); - if (ret) - goto err2; - - ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true; - - return 0; -err2: - if (hwmgr->hwmgr_func->backend_fini) - hwmgr->hwmgr_func->backend_fini(hwmgr); -err1: - if (hwmgr->pptable_func->pptable_fini) - hwmgr->pptable_func->pptable_fini(hwmgr); -err: - return ret; -} - -int hwmgr_hw_fini(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf) - return 0; - - phm_stop_thermal_controller(hwmgr); - psm_set_boot_states(hwmgr); - psm_adjust_power_state_dynamic(hwmgr, true, NULL); - phm_disable_dynamic_state_management(hwmgr); - phm_disable_clock_power_gatings(hwmgr); - - if (hwmgr->hwmgr_func->backend_fini) - hwmgr->hwmgr_func->backend_fini(hwmgr); - if (hwmgr->pptable_func->pptable_fini) - hwmgr->pptable_func->pptable_fini(hwmgr); - return psm_fini_power_state_table(hwmgr); -} - -int hwmgr_suspend(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - - if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf) - return 0; - - phm_disable_smc_firmware_ctf(hwmgr); - ret = psm_set_boot_states(hwmgr); - if (ret) - return ret; - ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); - if (ret) - return ret; - ret = phm_power_down_asic(hwmgr); - - return ret; -} - -int hwmgr_resume(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - - if (!hwmgr) - return -EINVAL; - - if (!hwmgr->not_vf || !hwmgr->pm_en) - return 0; - - ret = phm_setup_asic(hwmgr); - if (ret) - return ret; - - ret = phm_enable_dynamic_state_management(hwmgr); - if (ret) - return ret; - ret = phm_start_thermal_controller(hwmgr); - ret |= psm_set_performance_states(hwmgr); - if (ret) - return ret; - - ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); - - return ret; -} - -static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) -{ - switch (state) { - case POWER_STATE_TYPE_BATTERY: - return PP_StateUILabel_Battery; - case POWER_STATE_TYPE_BALANCED: - return PP_StateUILabel_Balanced; - case POWER_STATE_TYPE_PERFORMANCE: - return PP_StateUILabel_Performance; - default: - return PP_StateUILabel_None; - } -} - -int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id, - enum amd_pm_state_type *user_state) -{ - int ret = 0; - - if (hwmgr == NULL) - return -EINVAL; - - switch (task_id) { - case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: - if (!hwmgr->not_vf) - return ret; - ret = phm_pre_display_configuration_changed(hwmgr); - if (ret) - return ret; - ret = phm_set_cpu_power_state(hwmgr); - if (ret) - return ret; - ret = psm_set_performance_states(hwmgr); - if (ret) - return ret; - ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); - break; - case AMD_PP_TASK_ENABLE_USER_STATE: - { - enum PP_StateUILabel requested_ui_label; - struct pp_power_state *requested_ps = NULL; - - if (!hwmgr->not_vf) - return ret; - if (user_state == NULL) { - ret = -EINVAL; - break; - } - - requested_ui_label = power_state_convert(*user_state); - ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps); - if (ret) - return ret; - ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps); - break; - } - case AMD_PP_TASK_COMPLETE_INIT: - case AMD_PP_TASK_READJUST_POWER_STATE: - ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); - break; - default: - break; - } - return ret; -} - -void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) -{ - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM); - -#if defined(CONFIG_ACPI) - if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev)) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest); -#endif - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPatchPowerState); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableSMU7ThermalManagement); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPowerManagement); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMC); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicUVDState); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM); - return; -} - -int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep); - else - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep); - - if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - } else { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - } - - if (hwmgr->feature_mask & PP_OVERDRIVE_MASK) - hwmgr->od_enabled = true; - - return 0; -} - -int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) -{ - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EVV); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - - if (hwmgr->chip_id != CHIP_POLARIS10) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SPLLShutdownSupport); - - if (hwmgr->chip_id != CHIP_POLARIS11) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - } - return 0; -} - -int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) -{ - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EVV); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - return 0; -} - -int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) -{ - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EVV); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); - return 0; -} - -int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) -{ - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EVV); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - return 0; -} - -int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr) -{ - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MemorySpreadSpectrumSupport); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EngineSpreadSpectrumSupport); - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h deleted file mode 100644 index c0193e09d58a..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef PP_HWMGR_PPT_H -#define PP_HWMGR_PPT_H - -#include "hardwaremanager.h" -#include "smumgr.h" -#include "atom-types.h" - -struct phm_ppt_v1_clock_voltage_dependency_record { - uint32_t clk; - uint8_t vddInd; - uint8_t vddciInd; - uint8_t mvddInd; - uint16_t vdd_offset; - uint16_t vddc; - uint16_t vddgfx; - uint16_t vddci; - uint16_t mvdd; - uint8_t phases; - uint8_t cks_enable; - uint8_t cks_voffset; - uint32_t sclk_offset; -}; - -typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record; - -struct phm_ppt_v1_clock_voltage_dependency_table { - uint32_t count; /* Number of entries. */ - phm_ppt_v1_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ -}; - -typedef struct phm_ppt_v1_clock_voltage_dependency_table phm_ppt_v1_clock_voltage_dependency_table; - - -/* Multimedia Clock Voltage Dependency records and table */ -struct phm_ppt_v1_mm_clock_voltage_dependency_record { - uint32_t dclk; /* UVD D-clock */ - uint32_t vclk; /* UVD V-clock */ - uint32_t eclk; /* VCE clock */ - uint32_t aclk; /* ACP clock */ - uint32_t samclock; /* SAMU clock */ - uint8_t vddcInd; - uint16_t vddgfx_offset; - uint16_t vddc; - uint16_t vddgfx; - uint8_t phases; -}; -typedef struct phm_ppt_v1_mm_clock_voltage_dependency_record phm_ppt_v1_mm_clock_voltage_dependency_record; - -struct phm_ppt_v1_mm_clock_voltage_dependency_table { - uint32_t count; /* Number of entries. */ - phm_ppt_v1_mm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ -}; -typedef struct phm_ppt_v1_mm_clock_voltage_dependency_table phm_ppt_v1_mm_clock_voltage_dependency_table; - -struct phm_ppt_v1_voltage_lookup_record { - uint16_t us_calculated; - uint16_t us_vdd; /* Base voltage */ - uint16_t us_cac_low; - uint16_t us_cac_mid; - uint16_t us_cac_high; -}; -typedef struct phm_ppt_v1_voltage_lookup_record phm_ppt_v1_voltage_lookup_record; - -struct phm_ppt_v1_voltage_lookup_table { - uint32_t count; - phm_ppt_v1_voltage_lookup_record entries[1]; /* Dynamically allocate count entries. */ -}; -typedef struct phm_ppt_v1_voltage_lookup_table phm_ppt_v1_voltage_lookup_table; - -/* PCIE records and Table */ - -struct phm_ppt_v1_pcie_record { - uint8_t gen_speed; - uint8_t lane_width; - uint16_t usreserved; - uint16_t reserved; - uint32_t pcie_sclk; -}; -typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record; - -struct phm_ppt_v1_pcie_table { - uint32_t count; /* Number of entries. */ - phm_ppt_v1_pcie_record entries[1]; /* Dynamically allocate count entries. */ -}; -typedef struct phm_ppt_v1_pcie_table phm_ppt_v1_pcie_table; - -struct phm_ppt_v1_gpio_table { - uint8_t vrhot_triggered_sclk_dpm_index; /* SCLK DPM level index to switch to when VRHot is triggered */ -}; -typedef struct phm_ppt_v1_gpio_table phm_ppt_v1_gpio_table; - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c deleted file mode 100644 index 8f8e296f2fe9..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "polaris_baco.h" - -#include "gmc/gmc_8_1_d.h" -#include "gmc/gmc_8_1_sh_mask.h" - -#include "bif/bif_5_0_d.h" -#include "bif/bif_5_0_sh_mask.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" - -#include "smu/smu_7_1_3_d.h" -#include "smu/smu_7_1_3_sh_mask.h" - -static const struct baco_cmd_entry gpio_tbl[] = -{ - { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, - { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, - { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, - { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } -}; - -static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, - { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } -}; - -static const struct baco_cmd_entry use_bclk_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 } -}; - -static const struct baco_cmd_entry turn_off_plls_tbl[] = -{ - { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 }, - { CMD_DELAY_US, 0, 0, 0, 1, 0x0 }, - { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, - { CMD_READMODIFYWRITE, 0xda2, 0x40, 0x6, 0, 0x0 }, - { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, - { CMD_READMODIFYWRITE, 0xda2, 0x8, 0x3, 0, 0x0 }, - { CMD_READMODIFYWRITE, 0xda2, 0x3fff00, 0x8, 0, 0x32 }, - { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, - { CMD_READMODIFYWRITE, mmMPLL_FUNC_CNTL_2, MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK, MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT, 0, 0x0 }, - { CMD_DELAY_US, 0, 0, 0, 5, 0x0 } -}; - -static const struct baco_cmd_entry clk_req_b_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 } -}; - -static const struct baco_cmd_entry enter_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } -}; - -#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK - -static const struct baco_cmd_entry exit_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } -}; - -static const struct baco_cmd_entry clean_baco_tbl[] = -{ - { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } -}; - -static const struct baco_cmd_entry use_bclk_tbl_vg[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 } -}; - -static const struct baco_cmd_entry turn_off_plls_tbl_vg[] = -{ - { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 }, - { CMD_DELAY_US, 0, 0, 0, 1, 0x0 }, - { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, - { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, - { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, - { CMD_DELAY_US, 0, 0, 0, 5, 0x0 } -}; - -int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - enum BACO_STATE cur_state; - - smu7_baco_get_state(hwmgr, &cur_state); - - if (cur_state == state) - /* aisc already in the target state */ - return 0; - - if (state == BACO_STATE_IN) { - baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); - baco_program_registers(hwmgr, enable_fb_req_rej_tbl, - ARRAY_SIZE(enable_fb_req_rej_tbl)); - if (hwmgr->chip_id == CHIP_VEGAM) { - baco_program_registers(hwmgr, use_bclk_tbl_vg, ARRAY_SIZE(use_bclk_tbl_vg)); - baco_program_registers(hwmgr, turn_off_plls_tbl_vg, - ARRAY_SIZE(turn_off_plls_tbl_vg)); - } else { - baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); - baco_program_registers(hwmgr, turn_off_plls_tbl, - ARRAY_SIZE(turn_off_plls_tbl)); - } - baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl)); - if (baco_program_registers(hwmgr, enter_baco_tbl, - ARRAY_SIZE(enter_baco_tbl))) - return 0; - - } else if (state == BACO_STATE_OUT) { - /* HW requires at least 20ms between regulator off and on */ - msleep(20); - /* Execute Hardware BACO exit sequence */ - if (baco_program_registers(hwmgr, exit_baco_tbl, - ARRAY_SIZE(exit_baco_tbl))) { - if (baco_program_registers(hwmgr, clean_baco_tbl, - ARRAY_SIZE(clean_baco_tbl))) - return 0; - } - } - - return -EINVAL; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h deleted file mode 100644 index 87a5fa0a157a..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __POLARIS_BACO_H__ -#define __POLARIS_BACO_H__ -#include "smu7_baco.h" - -extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c deleted file mode 100644 index 8de384bf9a8f..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c +++ /dev/null @@ -1,1288 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "pp_overdriver.h" -#include <linux/errno.h> - -static const struct phm_fuses_default vega10_fuses_default[] = { - { 0x0213EA94DE0E4964, 0x00003C96, 0xFFFFE226, 0x00000656, 0x00002203, 0xFFFFF201, 0x000003FF, 0x00002203, 0xFFFFF201, 0x000003FF }, - { 0x0213EA94DE0A1884, 0x00003CC5, 0xFFFFE23A, 0x0000064E, 0x00002258, 0xFFFFF1F7, 0x000003FC, 0x00002258, 0xFFFFF1F7, 0x000003FC }, - { 0x0213EA94DE0E31A4, 0x00003CAF, 0xFFFFE36E, 0x00000602, 0x00001E98, 0xFFFFF569, 0x00000357, 0x00001E98, 0xFFFFF569, 0x00000357 }, - { 0x0213EA94DE2C1144, 0x0000391A, 0xFFFFE548, 0x000005C9, 0x00001B98, 0xFFFFF707, 0x00000324, 0x00001B98, 0xFFFFF707, 0x00000324 }, - { 0x0213EA94DE2C18C4, 0x00003821, 0xFFFFE674, 0x00000597, 0x00002196, 0xFFFFF361, 0x000003C0, 0x00002196, 0xFFFFF361, 0x000003C0 }, - { 0x0213EA94DE263884, 0x000044A2, 0xFFFFDCB7, 0x00000738, 0x0000325C, 0xFFFFE6A7, 0x000005E6, 0x0000325C, 0xFFFFE6A7, 0x000005E6 }, - { 0x0213EA94DE082924, 0x00004057, 0xFFFFE1CF, 0x0000063C, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00002E2E, 0xFFFFEB62, 0x000004FD }, - { 0x0213EA94DE284924, 0x00003FD0, 0xFFFFDF0F, 0x000006E5, 0x0000267C, 0xFFFFEE2D, 0x000004AB, 0x0000267C, 0xFFFFEE2D, 0x000004AB }, - { 0x0213EA94DE280904, 0x00003F13, 0xFFFFE010, 0x000006AD, 0x000020E7, 0xFFFFF266, 0x000003EC, 0x000020E7, 0xFFFFF266, 0x000003EC }, - { 0x0213EA94DE082044, 0x00004088, 0xFFFFDFAB, 0x000006B6, 0x0000252B, 0xFFFFEFDB, 0x00000458, 0x0000252B, 0xFFFFEFDB, 0x00000458 }, - { 0x0213EA94DE283884, 0x00003EF6, 0xFFFFE017, 0x000006AA, 0x00001F67, 0xFFFFF369, 0x000003BE, 0x00001F67, 0xFFFFF369, 0x000003BE }, - { 0x0213EA94DE2C2184, 0x00003CDD, 0xFFFFE2A7, 0x0000063C, 0x000026C6, 0xFFFFEF38, 0x00000478, 0x000026C6, 0xFFFFEF38, 0x00000478 }, - { 0x0213EA94DE105124, 0x00003FA8, 0xFFFFDF02, 0x000006F0, 0x000027FE, 0xFFFFECF6, 0x000004EA, 0x000027FE, 0xFFFFECF6, 0x000004EA }, - { 0x0213EA94DE2638C4, 0x00004670, 0xFFFFDC40, 0x00000742, 0x00003A7A, 0xFFFFE1A7, 0x000006B6, 0x00003A7A, 0xFFFFE1A7, 0x000006B6 }, - { 0x0213EA94DE2C3024, 0x00003CDC, 0xFFFFE18C, 0x00000683, 0x00002A69, 0xFFFFEBE7, 0x00000515, 0x00002A69, 0xFFFFEBE7, 0x00000515 }, - { 0x0213EA94DE0E38C4, 0x00003CEC, 0xFFFFE38E, 0x00000601, 0x00002752, 0xFFFFEFA7, 0x00000453, 0x00002752, 0xFFFFEFA7, 0x00000453 }, - { 0x0213EA94DE2C1124, 0x000037D0, 0xFFFFE634, 0x000005A7, 0x00001CD2, 0xFFFFF644, 0x00000348, 0x00001CD2, 0xFFFFF644, 0x00000348 }, - { 0x0213EA94DE283964, 0x00003DF5, 0xFFFFE0A5, 0x00000698, 0x00001FD5, 0xFFFFF30E, 0x000003D1, 0x00001FD5, 0xFFFFF30E, 0x000003D1 }, - { 0x0213EA94DE0828C4, 0x00004201, 0xFFFFE03E, 0x00000688, 0x00003206, 0xFFFFE852, 0x0000058A, 0x00003206, 0xFFFFE852, 0x0000058A }, - { 0x0213EA94DE2C1864, 0x00003BED, 0xFFFFE2F5, 0x00000638, 0x0000270D, 0xFFFFEED0, 0x0000048E, 0x0000270D, 0xFFFFEED0, 0x0000048E }, - { 0x0213EA94DE0A1904, 0x00003E82, 0xFFFFE1BE, 0x00000654, 0x000025FB, 0xFFFFEFFA, 0x00000448, 0x000025FB, 0xFFFFEFFA, 0x00000448 }, - { 0x0213EA94DE2C40C4, 0x00003962, 0xFFFFE4B9, 0x000005EF, 0x00002385, 0xFFFFF156, 0x00000423, 0x00002385, 0xFFFFF156, 0x00000423 }, - { 0x0213EA94DE2C0944, 0x00003D88, 0xFFFFE21A, 0x00000655, 0x0000295A, 0xFFFFED68, 0x000004C4, 0x0000295A, 0xFFFFED68, 0x000004C4 }, - { 0x0213EA94DE2C1104, 0x00003AA4, 0xFFFFE4A3, 0x000005E0, 0x000022EF, 0xFFFFF250, 0x000003EB, 0x000022EF, 0xFFFFF250, 0x000003EB }, - { 0x0213EA94DE0E29A4, 0x00003D97, 0xFFFFE30D, 0x0000060D, 0x0000205D, 0xFFFFF45D, 0x00000380, 0x0000205D, 0xFFFFF45D, 0x00000380 }, - { 0x0213EA94DE2C40A4, 0x000039B6, 0xFFFFE446, 0x00000605, 0x00002325, 0xFFFFF16C, 0x0000041F, 0x00002325, 0xFFFFF16C, 0x0000041F }, - { 0x0213EA94DE263904, 0x0000457E, 0xFFFFDCF6, 0x00000722, 0x00003972, 0xFFFFE27B, 0x0000068E, 0x00003972, 0xFFFFE27B, 0x0000068E }, - { 0x0213EA94DE0A1924, 0x00003FB8, 0xFFFFE101, 0x00000670, 0x00002787, 0xFFFFEEF5, 0x00000471, 0x00002787, 0xFFFFEEF5, 0x00000471 }, - { 0x0213EA94DE0E38A4, 0x00003BB2, 0xFFFFE430, 0x000005EA, 0x000024A5, 0xFFFFF162, 0x00000409, 0x000024A5, 0xFFFFF162, 0x00000409 }, - { 0x0213EA94DE082144, 0x00003EC5, 0xFFFFE1BD, 0x0000064F, 0x000022F0, 0xFFFFF227, 0x000003E8, 0x000022F0, 0xFFFFF227, 0x000003E8 }, - { 0x0213EA94DE2C3164, 0x000038A7, 0xFFFFE59F, 0x000005C1, 0x000021CC, 0xFFFFF2DF, 0x000003D9, 0x000021CC, 0xFFFFF2DF, 0x000003D9 }, - { 0x0213EA94DE324184, 0x00002995, 0xFFFFEF7A, 0x0000044C, 0x00001552, 0xFFFFFB5D, 0x00000292, 0x00001552, 0xFFFFFB5D, 0x00000292 }, - { 0x0213EA94DE2C4064, 0x00003B26, 0xFFFFE2D3, 0x00000649, 0x000023B4, 0xFFFFF09B, 0x00000449, 0x000023B4, 0xFFFFF09B, 0x00000449 }, - { 0x0213EA94DE081124, 0x000040D2, 0xFFFFE00A, 0x00000696, 0x000022DA, 0xFFFFF1E9, 0x000003F2, 0x000022DA, 0xFFFFF1E9, 0x000003F2 }, - { 0x0213EA94DE2C3924, 0x00003C98, 0xFFFFE365, 0x00000618, 0x00002D5D, 0xFFFFEB3A, 0x0000051D, 0x00002D5D, 0xFFFFEB3A, 0x0000051D }, - { 0x0213EA94DE2C10A4, 0x00003BBD, 0xFFFFE37E, 0x00000617, 0x0000252E, 0xFFFFF06E, 0x00000441, 0x0000252E, 0xFFFFF06E, 0x00000441 }, - { 0x0213EA94DE262924, 0x00004363, 0xFFFFDF7A, 0x000006A0, 0x000031F5, 0xFFFFE880, 0x0000057B, 0x000031F5, 0xFFFFE880, 0x0000057B }, - { 0x0213EA94DE0E3844, 0x00003CFC, 0xFFFFE2AF, 0x0000062E, 0x0000212A, 0xFFFFF335, 0x000003BF, 0x0000212A, 0xFFFFF335, 0x000003BF }, - { 0x0213EA94DE1C4924, 0x0000252D, 0xFFFFF31B, 0x000003C3, 0x00001A1A, 0xFFFFF882, 0x00000325, 0x00001A1A, 0xFFFFF882, 0x00000325 }, - { 0x0213EA94DE0A29A4, 0x00003FE2, 0xFFFFDFEF, 0x000006AC, 0x000025A2, 0xFFFFEF84, 0x00000462, 0x000025A2, 0xFFFFEF84, 0x00000462 }, - { 0x0213EA94DE0820E4, 0x000040A5, 0xFFFFE13B, 0x0000065B, 0x00002C13, 0xFFFFEC75, 0x000004D7, 0x00002C13, 0xFFFFEC75, 0x000004D7 }, - { 0x0213EA94DE0E48A4, 0x00003E42, 0xFFFFE1B3, 0x00000657, 0x0000221D, 0xFFFFF273, 0x000003DE, 0x0000221D, 0xFFFFF273, 0x000003DE }, - { 0x0213EA94DE0A20E4, 0x00003E7F, 0xFFFFE255, 0x00000638, 0x00002D30, 0xFFFFEB8A, 0x00000503, 0x00002D30, 0xFFFFEB8A, 0x00000503 }, - { 0x0213EA94DE2C29C4, 0x00003E56, 0xFFFFE16D, 0x00000670, 0x000028DC, 0xFFFFEDA0, 0x000004BA, 0x000028DC, 0xFFFFEDA0, 0x000004BA }, - { 0x0213EA94DE2630A4, 0x000044AD, 0xFFFFDE24, 0x000006DD, 0x000031AD, 0xFFFFE850, 0x00000585, 0x000031AD, 0xFFFFE850, 0x00000585 }, - { 0x0213EA94DE2C20E4, 0x00003AF3, 0xFFFFE5B0, 0x000005A6, 0x00002CF6, 0xFFFFEC75, 0x000004DD, 0x00002CF6, 0xFFFFEC75, 0x000004DD }, - { 0x0213EA94DE0A2084, 0x00003E66, 0xFFFFE19E, 0x0000065B, 0x00002332, 0xFFFFF1B9, 0x000003FD, 0x00002332, 0xFFFFF1B9, 0x000003FD }, - { 0x0213EA94DE082884, 0x00003FB4, 0xFFFFE0A5, 0x00000686, 0x0000253E, 0xFFFFF02E, 0x00000444, 0x0000253E, 0xFFFFF02E, 0x00000444 }, - { 0x0213EA94DE2818A4, 0x00003E28, 0xFFFFE14D, 0x0000066E, 0x00001FE2, 0xFFFFF39A, 0x000003B1, 0x00001FE2, 0xFFFFF39A, 0x000003B1 }, - { 0x0213EA94DE2C0904, 0x000039E6, 0xFFFFE44B, 0x000005FE, 0x0000210C, 0xFFFFF2F4, 0x000003DA, 0x0000210C, 0xFFFFF2F4, 0x000003DA }, - { 0x0213EA94DE2C5104, 0x00003A4D, 0xFFFFE252, 0x0000067A, 0x000027E2, 0xFFFFECED, 0x000004FA, 0x000027E2, 0xFFFFECED, 0x000004FA }, - { 0x0213EA94DE0A2964, 0x00004065, 0xFFFFE02F, 0x0000069B, 0x0000299D, 0xFFFFED38, 0x000004C2, 0x0000299D, 0xFFFFED38, 0x000004C2 }, - { 0x0213EA94DE0E20A4, 0x000039EE, 0xFFFFE603, 0x00000594, 0x0000214F, 0xFFFFF429, 0x0000038E, 0x0000214F, 0xFFFFF429, 0x0000038E }, - { 0x0213EA94DE0E48E4, 0x00003BD2, 0xFFFFE351, 0x00000618, 0x000020B8, 0xFFFFF377, 0x000003B4, 0x000020B8, 0xFFFFF377, 0x000003B4 }, - { 0x0213EA94DE0A3124, 0x00003FAA, 0xFFFFE183, 0x0000065E, 0x000032AE, 0xFFFFE7C2, 0x000005A6, 0x000032AE, 0xFFFFE7C2, 0x000005A6 }, - { 0x0213EA94DE2C2984, 0x00003AFB, 0xFFFFE3E4, 0x00000608, 0x00002293, 0xFFFFF21F, 0x000003FA, 0x00002293, 0xFFFFF21F, 0x000003FA }, - { 0x0213EA94DE262064, 0x0000448B, 0xFFFFDD5D, 0x0000070D, 0x00002E4E, 0xFFFFE9DF, 0x00000551, 0x00002E4E, 0xFFFFE9DF, 0x00000551 }, - { 0x0213EA94DE0E2184, 0x00003D46, 0xFFFFE39B, 0x000005F3, 0x0000218E, 0xFFFFF3CD, 0x00000398, 0x0000218E, 0xFFFFF3CD, 0x00000398 }, - { 0x0213EA94DE0848E4, 0x00003F01, 0xFFFFDFD9, 0x000006BF, 0x000023AF, 0xFFFFF04E, 0x0000044C, 0x000023AF, 0xFFFFF04E, 0x0000044C }, - { 0x0213EA94DE1029A4, 0x0000403D, 0xFFFFDF6B, 0x000006C9, 0x0000270D, 0xFFFFEE4B, 0x0000049E, 0x0000270D, 0xFFFFEE4B, 0x0000049E }, - { 0x0213EA94DE0E3964, 0x00003C11, 0xFFFFE35C, 0x00000613, 0x000020F9, 0xFFFFF365, 0x000003B9, 0x000020F9, 0xFFFFF365, 0x000003B9 }, - { 0x0213EA94DE2C3884, 0x00003B58, 0xFFFFE37D, 0x0000061F, 0x00002698, 0xFFFFEF46, 0x00000478, 0x00002698, 0xFFFFEF46, 0x00000478 }, - { 0x0213EA94DE2841A4, 0x00003EBC, 0xFFFFDF7A, 0x000006D6, 0x0000212B, 0xFFFFF195, 0x0000041B, 0x0000212B, 0xFFFFF195, 0x0000041B }, - { 0x0213EA94DE0848C4, 0x00004050, 0xFFFFDEB3, 0x000006FE, 0x00002D6C, 0xFFFFE961, 0x00000582, 0x00002D6C, 0xFFFFE961, 0x00000582 }, - { 0x0213EA94DE262044, 0x000043F0, 0xFFFFDD9C, 0x00000702, 0x00002B31, 0xFFFFEBEA, 0x000004F7, 0x00002B31, 0xFFFFEBEA, 0x000004F7 }, - { 0x0213EA94DE100924, 0x00003EFA, 0xFFFFE093, 0x00000696, 0x000026DB, 0xFFFFEEB3, 0x00000489, 0x000026DB, 0xFFFFEEB3, 0x00000489 }, - { 0x0213EA94DE082064, 0x0000425D, 0xFFFFDE8D, 0x000006E6, 0x00002CA4, 0xFFFFEAD2, 0x00000531, 0x00002CA4, 0xFFFFEAD2, 0x00000531 }, - { 0x0213EA94DE2639A4, 0x000043B0, 0xFFFFDD03, 0x00000728, 0x00002946, 0xFFFFECA6, 0x000004DE, 0x00002946, 0xFFFFECA6, 0x000004DE }, - { 0x0213EA94DE282864, 0x00003F6A, 0xFFFFE03A, 0x0000069D, 0x00002208, 0xFFFFF1F8, 0x000003F6, 0x00002208, 0xFFFFF1F8, 0x000003F6 }, - { 0x0213EA94DE2C2964, 0x00003A94, 0xFFFFE4A7, 0x000005E2, 0x000024D0, 0xFFFFF100, 0x00000426, 0x000024D0, 0xFFFFF100, 0x00000426 }, - { 0x0213EA94DE2810C4, 0x00003F2F, 0xFFFFE0A3, 0x00000688, 0x00002198, 0xFFFFF271, 0x000003E2, 0x00002198, 0xFFFFF271, 0x000003E2 }, - { 0x0213EA94DE1048E4, 0x00003EA5, 0xFFFFE032, 0x000006AE, 0x0000227C, 0xFFFFF130, 0x00000426, 0x0000227C, 0xFFFFF130, 0x00000426 }, - { 0x0213EA94DE264144, 0x0000442F, 0xFFFFDBC4, 0x0000078B, 0x00003CD6, 0xFFFFDE6C, 0x0000076C, 0x00003CD6, 0xFFFFDE6C, 0x0000076C }, - { 0x0213EA94DE282884, 0x00003DDE, 0xFFFFE174, 0x00000668, 0x00001FF4, 0xFFFFF38F, 0x000003B1, 0x00001FF4, 0xFFFFF38F, 0x000003B1 }, - { 0x0213EA94DE0A3144, 0x000040B0, 0xFFFFE016, 0x000006A0, 0x00002DBB, 0xFFFFEA7F, 0x00000537, 0x00002DBB, 0xFFFFEA7F, 0x00000537 }, - { 0x0213EA94DE2C3104, 0x00003429, 0xFFFFEA97, 0x000004DD, 0x000024D5, 0xFFFFF26F, 0x000003DF, 0x000024D5, 0xFFFFF26F, 0x000003DF }, - { 0x0213EA94DE0E1904, 0x00003AEB, 0xFFFFE590, 0x000005A3, 0x000022CB, 0xFFFFF347, 0x000003B2, 0x000022CB, 0xFFFFF347, 0x000003B2 }, - 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{ 0x0213F0FE992C1164, 0x000030B7, 0xFFFFEAF0, 0x000004F3, 0x00001AEC, 0xFFFFF7A9, 0x0000031B, 0x00001AEC, 0xFFFFF7A9, 0x0000031B }, - { 0x0213F0FE992C39A4, 0x00003078, 0xFFFFEBA4, 0x000004CF, 0x00001E7A, 0xFFFFF5AF, 0x0000036B, 0x00001E7A, 0xFFFFF5AF, 0x0000036B }, - { 0x0213F0FE99304124, 0x00003442, 0xFFFFE998, 0x00000518, 0x000025EA, 0xFFFFF0F3, 0x0000042B, 0x000025EA, 0xFFFFF0F3, 0x0000042B }, - { 0x0213F0FE993021A4, 0x000031CB, 0xFFFFEA80, 0x00000501, 0x000020A3, 0xFFFFF403, 0x000003B2, 0x000020A3, 0xFFFFF403, 0x000003B2 }, - { 0x0213F0FE992A2984, 0x00002947, 0xFFFFF018, 0x00000433, 0x00001BA5, 0xFFFFF75C, 0x00000340, 0x00001BA5, 0xFFFFF75C, 0x00000340 }, - { 0x0213F0FE992C3984, 0x000033F9, 0xFFFFE99D, 0x00000518, 0x00002231, 0xFFFFF358, 0x000003C5, 0x00002231, 0xFFFFF358, 0x000003C5 }, - { 0x0213F0FE99321124, 0x00003131, 0xFFFFEA45, 0x00000513, 0x00001973, 0xFFFFF85E, 0x00000301, 0x00001973, 0xFFFFF85E, 0x00000301 }, - { 0x0213F0FE991C29A4, 0x00003571, 0xFFFFE8AC, 0x00000539, 0x00002049, 0xFFFFF49C, 0x0000038D, 0x00002049, 0xFFFFF49C, 0x0000038D }, - { 0x0213F0FE992E3864, 0x0000309E, 0xFFFFEB1D, 0x000004E8, 0x000019ED, 0xFFFFF86E, 0x000002F8, 0x000019ED, 0xFFFFF86E, 0x000002F8 }, - { 0x0213F0FE99302984, 0x00003091, 0xFFFFEB9B, 0x000004CC, 0x00001D2C, 0xFFFFF6A2, 0x0000033D, 0x00001D2C, 0xFFFFF6A2, 0x0000033D }, - { 0x0213F0FE993008E4, 0x00003069, 0xFFFFEAFD, 0x000004F8, 0x00001E82, 0xFFFFF51C, 0x0000038D, 0x00001E82, 0xFFFFF51C, 0x0000038D }, - { 0x0213F0FE992210A4, 0x00003459, 0xFFFFE7F2, 0x00000572, 0x00001DA7, 0xFFFFF552, 0x0000037F, 0x00001DA7, 0xFFFFF552, 0x0000037F }, - { 0x0213F0FE99321104, 0x0000304B, 0xFFFFEAFB, 0x000004F4, 0x0000191E, 0xFFFFF8BD, 0x000002EE, 0x0000191E, 0xFFFFF8BD, 0x000002EE }, - { 0x0213F0FE993020C4, 0x0000346E, 0xFFFFEA07, 0x000004FD, 0x00002767, 0xFFFFF058, 0x00000440, 0x00002767, 0xFFFFF058, 0x00000440 }, - { 0x0213F0FE992E3084, 0x000030B5, 0xFFFFEBC1, 0x000004C1, 0x00001B3C, 0xFFFFF818, 0x000002FD, 0x00001B3C, 0xFFFFF818, 0x000002FD }, - { 0x0213F0FE99300904, 0x0000321F, 0xFFFFE9EA, 0x00000524, 0x00002380, 0xFFFFF1C2, 0x0000041A, 0x00002380, 0xFFFFF1C2, 0x0000041A }, - { 0x0213F0FE992E3044, 0x000030DF, 0xFFFFEB37, 0x000004E2, 0x00001E3C, 0xFFFFF5BB, 0x00000369, 0x00001E3C, 0xFFFFF5BB, 0x00000369 }, - { 0x0213F0FE992848A4, 0x000027E0, 0xFFFFF0E2, 0x00000416, 0x00001A6A, 0xFFFFF820, 0x00000321, 0x00001A6A, 0xFFFFF820, 0x00000321 }, - { 0x0213F0FE991A1084, 0x00002FA1, 0xFFFFEB63, 0x000004E7, 0x0000196B, 0xFFFFF880, 0x000002FB, 0x0000196B, 0xFFFFF880, 0x000002FB }, - { 0x0213F0FE991C1084, 0x0000310C, 0xFFFFEAAF, 0x000004FC, 0x000019EF, 0xFFFFF850, 0x000002FD, 0x000019EF, 0xFFFFF850, 0x000002FD }, - { 0x0213F0FE99323904, 0x0000334A, 0xFFFFEA07, 0x0000050B, 0x00002380, 0xFFFFF26F, 0x000003F0, 0x00002380, 0xFFFFF26F, 0x000003F0 }, - { 0x0213F0FE99302944, 0x00002FF9, 0xFFFFECDC, 0x00000492, 0x00002297, 0xFFFFF394, 0x000003BF, 0x00002297, 0xFFFFF394, 0x000003BF }, - { 0x0213F0FE992C2164, 0x0000354B, 0xFFFFE894, 0x00000546, 0x000024C4, 0xFFFFF16C, 0x0000041B, 0x000024C4, 0xFFFFF16C, 0x0000041B }, - { 0x0213F0FE99220924, 0x00003245, 0xFFFFE92F, 0x00000544, 0x00001829, 0xFFFFF8F1, 0x000002EA, 0x00001829, 0xFFFFF8F1, 0x000002EA }, - { 0x0213F0FE992E4884, 0x0000302F, 0xFFFFEB51, 0x000004E3, 0x0000199F, 0xFFFFF894, 0x000002F4, 0x0000199F, 0xFFFFF894, 0x000002F4 }, - { 0x0213F0FE992E18C4, 0x00002F54, 0xFFFFEC86, 0x000004A6, 0x00001A6F, 0xFFFFF891, 0x000002EC, 0x00001A6F, 0xFFFFF891, 0x000002EC }, - { 0x0213F0FE99284164, 0x00002908, 0xFFFFF0D8, 0x0000040A, 0x00001C9B, 0xFFFFF729, 0x00000342, 0x00001C9B, 0xFFFFF729, 0x00000342 }, - { 0x0213F0FE99302964, 0x000031D9, 0xFFFFEB40, 0x000004D7, 0x000023F5, 0xFFFFF259, 0x000003F4, 0x000023F5, 0xFFFFF259, 0x000003F4 }, - { 0x0213F0FE993048E4, 0x000034C8, 0xFFFFE8C6, 0x0000053F, 0x00002313, 0xFFFFF280, 0x000003EC, 0x00002313, 0xFFFFF280, 0x000003EC }, - { 0x0213F0FE993050C4, 0x000037D1, 0xFFFFE6A1, 0x0000059C, 0x00002C6A, 0xFFFFEBFF, 0x00000504, 0x00002C6A, 0xFFFFEBFF, 0x00000504 }, - { 0x0213F0FE99321964, 0x000030E9, 0xFFFFEA6B, 0x0000050F, 0x00001A2D, 0xFFFFF7DF, 0x00000316, 0x00001A2D, 0xFFFFF7DF, 0x00000316 }, - { 0x0213F0FE99302084, 0x0000323D, 0xFFFFEA95, 0x000004F4, 0x00001ED2, 0xFFFFF584, 0x0000036C, 0x00001ED2, 0xFFFFF584, 0x0000036C }, - { 0x0213F0FE992C3024, 0x000033D6, 0xFFFFE9DB, 0x00000510, 0x000027A7, 0xFFFFEFC7, 0x0000045E, 0x000027A7, 0xFFFFEFC7, 0x0000045E }, - { 0x0213F0FE991C3164, 0x00003444, 0xFFFFE98A, 0x00000517, 0x000020FD, 0xFFFFF43F, 0x0000039D, 0x000020FD, 0xFFFFF43F, 0x0000039D }, - { 0x0213F0FE992808E4, 0x00002987, 0xFFFFEFA1, 0x0000044B, 0x00001B06, 0xFFFFF788, 0x0000033C, 0x00001B06, 0xFFFFF788, 0x0000033C }, - { 0x0213F0FE992C28E4, 0x0000311D, 0xFFFFED20, 0x00000474, 0x000025DA, 0xFFFFF223, 0x000003F0, 0x000025DA, 0xFFFFF223, 0x000003F0 }, - { 0x0213F0FE992C1124, 0x000032A2, 0xFFFFEA0A, 0x0000050D, 0x00001D48, 0xFFFFF659, 0x0000034A, 0x00001D48, 0xFFFFF659, 0x0000034A }, - { 0x0213F0FE992208E4, 0x00003110, 0xFFFFE9EA, 0x00000529, 0x00001786, 0xFFFFF958, 0x000002DB, 0x00001786, 0xFFFFF958, 0x000002DB }, - { 0x0213F0FE992821A4, 0x000027F2, 0xFFFFF174, 0x000003F7, 0x00001C7A, 0xFFFFF72A, 0x00000348, 0x00001C7A, 0xFFFFF72A, 0x00000348 }, - { 0x0213F0FE991C10E4, 0x000031DB, 0xFFFFEA7D, 0x000004FB, 0x000019C4, 0xFFFFF8B1, 0x000002E6, 0x000019C4, 0xFFFFF8B1, 0x000002E6 }, - { 0x0213F0FE992C1104, 0x00003158, 0xFFFFEAAC, 0x000004FA, 0x00001BC1, 0xFFFFF737, 0x0000032B, 0x00001BC1, 0xFFFFF737, 0x0000032B }, - { 0x0213F0FE993010C4, 0x00002F36, 0xFFFFEBF9, 0x000004CA, 0x00001A2A, 0xFFFFF83F, 0x00000303, 0x00001A2A, 0xFFFFF83F, 0x00000303 }, - { 0x0213F0FE993238A4, 0x000032B4, 0xFFFFEA72, 0x000004FA, 0x000021FF, 0xFFFFF378, 0x000003C5, 0x000021FF, 0xFFFFF378, 0x000003C5 }, - { 0x0213F0FE99303164, 0x00003262, 0xFFFFEAFA, 0x000004DF, 0x00002441, 0xFFFFF237, 0x000003F6, 0x00002441, 0xFFFFF237, 0x000003F6 }, - { 0x0213F0FE99303924, 0x0000336A, 0xFFFFEAFB, 0x000004D1, 0x00002746, 0xFFFFF0B8, 0x0000042B, 0x00002746, 0xFFFFF0B8, 0x0000042B }, - { 0x0213F0FE991A4084, 0x000032E5, 0xFFFFE923, 0x00000541, 0x00001DF0, 0xFFFFF552, 0x00000380, 0x00001DF0, 0xFFFFF552, 0x00000380 }, - { 0x0213F0FE99304064, 0x000035D1, 0xFFFFE80B, 0x0000055F, 0x00002780, 0xFFFFEF74, 0x0000046F, 0x00002780, 0xFFFFEF74, 0x0000046F }, - { 0x0213F0FE993028A4, 0x000033EC, 0xFFFFEA48, 0x000004F4, 0x0000269F, 0xFFFFF0D8, 0x0000042A, 0x0000269F, 0xFFFFF0D8, 0x0000042A }, - { 0x0213F0FE99323884, 0x000030C4, 0xFFFFEB39, 0x000004E2, 0x00001B44, 0xFFFFF7AA, 0x00000318, 0x00001B44, 0xFFFFF7AA, 0x00000318 }, - { 0x0213F0FE99281144, 0x00002926, 0xFFFFF0AF, 0x0000040E, 0x0000194E, 0xFFFFF959, 0x000002E2, 0x0000194E, 0xFFFFF959, 0x000002E2 }, - { 0x0213F0FE992C10C4, 0x00003141, 0xFFFFEAAF, 0x000004F6, 0x00001864, 0xFFFFF97C, 0x000002C6, 0x00001864, 0xFFFFF97C, 0x000002C6 }, - { 0x0213F0FE99301064, 0x000030B2, 0xFFFFEB7C, 0x000004DB, 0x000022CE, 0xFFFFF2B5, 0x000003F0, 0x000022CE, 0xFFFFF2B5, 0x000003F0 }, - { 0x0213F0FE99301944, 0x0000318C, 0xFFFFEAC7, 0x000004F6, 0x00002113, 0xFFFFF3CA, 0x000003BD, 0x00002113, 0xFFFFF3CA, 0x000003BD }, - { 0x0213F0FE992E1104, 0x00002FD2, 0xFFFFEB8F, 0x000004D9, 0x00001996, 0xFFFFF89F, 0x000002F1, 0x00001996, 0xFFFFF89F, 0x000002F1 }, - { 0x0213F0FE991A28A4, 0x0000310D, 0xFFFFEB25, 0x000004E7, 0x00001F67, 0xFFFFF4EF, 0x0000038E, 0x00001F67, 0xFFFFF4EF, 0x0000038E }, - { 0x0213F0FE992A4964, 0x00002BBC, 0xFFFFEE68, 0x00000477, 0x00002050, 0xFFFFF41D, 0x000003C8, 0x00002050, 0xFFFFF41D, 0x000003C8 }, - { 0x0213F0FE99302104, 0x00003096, 0xFFFFECED, 0x00000486, 0x000024C9, 0xFFFFF278, 0x000003E7, 0x000024C9, 0xFFFFF278, 0x000003E7 }, - { 0x0213F0FE992C10A4, 0x00003401, 0xFFFFE8F1, 0x0000053C, 0x00001E75, 0xFFFFF55C, 0x00000376, 0x00001E75, 0xFFFFF55C, 0x00000376 }, - { 0x0213F0FE99302844, 0x0000319E, 0xFFFFEAB1, 0x000004F8, 0x00001EA3, 0xFFFFF567, 0x00000378, 0x00001EA3, 0xFFFFF567, 0x00000378 }, - { 0x0213F0FE99322964, 0x000030FD, 0xFFFFEB4C, 0x000004DB, 0x00001CA6, 0xFFFFF6E8, 0x00000335, 0x00001CA6, 0xFFFFF6E8, 0x00000335 }, - { 0x0213F0FE992E40A4, 0x000030D6, 0xFFFFEB1A, 0x000004E4, 0x00001A0D, 0xFFFFF87D, 0x000002EF, 0x00001A0D, 0xFFFFF87D, 0x000002EF }, - { 0x0213F0FE992C2124, 0x0000324B, 0xFFFFEB17, 0x000004D9, 0x00002225, 0xFFFFF3A8, 0x000003BA, 0x00002225, 0xFFFFF3A8, 0x000003BA }, - { 0x0213F0FE99284084, 0x00002A00, 0xFFFFF02E, 0x00000424, 0x00001E21, 0xFFFFF61D, 0x0000036C, 0x00001E21, 0xFFFFF61D, 0x0000036C }, - { 0x0213F0FE992A48A4, 0x000029CF, 0xFFFFEF53, 0x00000457, 0x00001B11, 0xFFFFF772, 0x0000033D, 0x00001B11, 0xFFFFF772, 0x0000033D }, - { 0x0213F0FE991A30A4, 0x000032A1, 0xFFFFEA63, 0x000004FB, 0x00001F83, 0xFFFFF516, 0x0000037E, 0x00001F83, 0xFFFFF516, 0x0000037E }, - { 0x0213F0FE992E20C4, 0x0000305C, 0xFFFFEC14, 0x000004B5, 0x00001D0B, 0xFFFFF6ED, 0x00000332, 0x00001D0B, 0xFFFFF6ED, 0x00000332 }, - { 0x0213F0FE992C1064, 0x00003467, 0xFFFFE8D5, 0x00000543, 0x0000243F, 0xFFFFF190, 0x00000418, 0x0000243F, 0xFFFFF190, 0x00000418 }, - { 0x0213F0FE992A2064, 0x00002796, 0xFFFFF133, 0x00000409, 0x00001903, 0xFFFFF91C, 0x000002FC, 0x00001903, 0xFFFFF91C, 0x000002FC }, - { 0x0213F0FE99302164, 0x000031F6, 0xFFFFEAB7, 0x000004F5, 0x000022B9, 0xFFFFF2D0, 0x000003E6, 0x000022B9, 0xFFFFF2D0, 0x000003E6 }, - { 0x0213F0FE992E5104, 0x00003196, 0xFFFFEA76, 0x00000503, 0x00001CC5, 0xFFFFF67D, 0x0000034A, 0x00001CC5, 0xFFFFF67D, 0x0000034A }, - { 0x0213F0FE99321144, 0x00002F9E, 0xFFFFEAD9, 0x00000505, 0x000017C1, 0xFFFFF93D, 0x000002DF, 0x000017C1, 0xFFFFF93D, 0x000002DF }, - { 0x0213F0FE992E2124, 0x00002FBC, 0xFFFFEC75, 0x000004A8, 0x00001D6D, 0xFFFFF6AC, 0x0000033D, 0x00001D6D, 0xFFFFF6AC, 0x0000033D }, - { 0x0213F0FE992C38A4, 0x00003541, 0xFFFFE921, 0x00000524, 0x00002662, 0xFFFFF0CB, 0x0000042B, 0x00002662, 0xFFFFF0CB, 0x0000042B }, - { 0x0213F0FE992A21A4, 0x00002953, 0xFFFFEF76, 0x00000459, 0x00001C05, 0xFFFFF6A0, 0x00000368, 0x00001C05, 0xFFFFF6A0, 0x00000368 }, - { 0x0213F0FE992C4924, 0x000034BC, 0xFFFFE8DD, 0x00000536, 0x0000210E, 0xFFFFF3F4, 0x000003A8, 0x0000210E, 0xFFFFF3F4, 0x000003A8 }, - { 0x0213F0FE992C29A4, 0x000034BE, 0xFFFFE916, 0x0000052F, 0x000024A1, 0xFFFFF1A6, 0x00000410, 0x000024A1, 0xFFFFF1A6, 0x00000410 }, - { 0x0213F0FE99304964, 0x000037B5, 0xFFFFE7A9, 0x0000055B, 0x000028A1, 0xFFFFEF51, 0x00000467, 0x000028A1, 0xFFFFEF51, 0x00000467 }, - { 0x0213F0FE99301104, 0x00002FC5, 0xFFFFEBBE, 0x000004D1, 0x00001BA5, 0xFFFFF757, 0x00000328, 0x00001BA5, 0xFFFFF757, 0x00000328 }, - { 0x0213F0FE993040A4, 0x000033CB, 0xFFFFE944, 0x0000052B, 0x00001FBE, 0xFFFFF4B1, 0x0000038C, 0x00001FBE, 0xFFFFF4B1, 0x0000038C }, - { 0x0213F0FE99301844, 0x000030AE, 0xFFFFEBA0, 0x000004D3, 0x00002268, 0xFFFFF316, 0x000003DD, 0x00002268, 0xFFFFF316, 0x000003DD }, - { 0x0213F0FE992C20A4, 0x00002F90, 0xFFFFEC5A, 0x000004B0, 0x00001C3A, 0xFFFFF752, 0x00000323, 0x00001C3A, 0xFFFFF752, 0x00000323 }, - { 0x0213F0FE992E38E4, 0x00003113, 0xFFFFEB91, 0x000004C8, 0x00001E3C, 0xFFFFF623, 0x0000034E, 0x00001E3C, 0xFFFFF623, 0x0000034E }, - { 0x0213F0FE99323984, 0x0000330B, 0xFFFFE94B, 0x00000539, 0x000020E7, 0xFFFFF37E, 0x000003CD, 0x000020E7, 0xFFFFF37E, 0x000003CD }, - { 0x0213F0FE992E2864, 0x000031D1, 0xFFFFEACB, 0x000004ED, 0x00001E82, 0xFFFFF5B2, 0x00000365, 0x00001E82, 0xFFFFF5B2, 0x00000365 }, - { 0x0213F0FE992A3984, 0x00002CD5, 0xFFFFEDC1, 0x0000048D, 0x000020F8, 0xFFFFF3C1, 0x000003D1, 0x000020F8, 0xFFFFF3C1, 0x000003D1 }, - { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } -}; - -int pp_override_get_default_fuse_value(uint64_t key, - struct phm_fuses_default *result) -{ - const struct phm_fuses_default *list = vega10_fuses_default; - uint32_t i; - - for (i = 0; list[i].key != 0; i++) { - if (key == list[i].key) { - result->key = list[i].key; - result->VFT2_m1 = list[i].VFT2_m1; - result->VFT2_m2 = list[i].VFT2_m2; - result->VFT2_b = list[i].VFT2_b; - result->VFT1_m1 = list[i].VFT1_m1; - result->VFT1_m2 = list[i].VFT1_m2; - result->VFT1_b = list[i].VFT1_b; - result->VFT0_m1 = list[i].VFT0_m1; - result->VFT0_m2 = list[i].VFT0_m2; - result->VFT0_b = list[i].VFT0_b; - return 0; - } - } - - return -EINVAL; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h deleted file mode 100644 index 4112a9398163..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _PP_OVERDRIVER_H_ -#define _PP_OVERDRIVER_H_ - -#include <linux/types.h> -#include <linux/kernel.h> - -struct phm_fuses_default { - uint64_t key; - uint32_t VFT2_m1; - uint32_t VFT2_m2; - uint32_t VFT2_b; - uint32_t VFT1_m1; - uint32_t VFT1_m2; - uint32_t VFT1_b; - uint32_t VFT0_m1; - uint32_t VFT0_m2; - uint32_t VFT0_b; -}; - -extern int pp_override_get_default_fuse_value(uint64_t key, - struct phm_fuses_default *result); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c deleted file mode 100644 index 31a32a79cfc2..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include "pp_psm.h" - -int psm_init_power_state_table(struct pp_hwmgr *hwmgr) -{ - int result; - unsigned int i; - unsigned int table_entries; - struct pp_power_state *state; - int size; - - if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL) - return 0; - - if (hwmgr->hwmgr_func->get_power_state_size == NULL) - return 0; - - hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr); - - hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) + - sizeof(struct pp_power_state); - - if (table_entries == 0 || size == 0) { - pr_warn("Please check whether power state management is supported on this asic\n"); - return 0; - } - - hwmgr->ps = kcalloc(table_entries, size, GFP_KERNEL); - if (hwmgr->ps == NULL) - return -ENOMEM; - - hwmgr->request_ps = kzalloc(size, GFP_KERNEL); - if (hwmgr->request_ps == NULL) { - kfree(hwmgr->ps); - hwmgr->ps = NULL; - return -ENOMEM; - } - - hwmgr->current_ps = kzalloc(size, GFP_KERNEL); - if (hwmgr->current_ps == NULL) { - kfree(hwmgr->request_ps); - kfree(hwmgr->ps); - hwmgr->request_ps = NULL; - hwmgr->ps = NULL; - return -ENOMEM; - } - - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state); - - if (state->classification.flags & PP_StateClassificationFlag_Boot) { - hwmgr->boot_ps = state; - memcpy(hwmgr->current_ps, state, size); - memcpy(hwmgr->request_ps, state, size); - } - - state->id = i + 1; /* assigned unique num for every power state id */ - - if (state->classification.flags & PP_StateClassificationFlag_Uvd) - hwmgr->uvd_ps = state; - state = (struct pp_power_state *)((unsigned long)state + size); - } - - return 0; -} - -int psm_fini_power_state_table(struct pp_hwmgr *hwmgr) -{ - if (hwmgr == NULL) - return -EINVAL; - - if (!hwmgr->ps) - return 0; - - kfree(hwmgr->current_ps); - kfree(hwmgr->request_ps); - kfree(hwmgr->ps); - hwmgr->request_ps = NULL; - hwmgr->ps = NULL; - hwmgr->current_ps = NULL; - return 0; -} - -static int psm_get_ui_state(struct pp_hwmgr *hwmgr, - enum PP_StateUILabel ui_label, - unsigned long *state_id) -{ - struct pp_power_state *state; - int table_entries; - int i; - - table_entries = hwmgr->num_ps; - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - if (state->classification.ui_label & ui_label) { - *state_id = state->id; - return 0; - } - state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); - } - return -EINVAL; -} - -static int psm_get_state_by_classification(struct pp_hwmgr *hwmgr, - enum PP_StateClassificationFlag flag, - unsigned long *state_id) -{ - struct pp_power_state *state; - int table_entries; - int i; - - table_entries = hwmgr->num_ps; - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - if (state->classification.flags & flag) { - *state_id = state->id; - return 0; - } - state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); - } - return -EINVAL; -} - -static int psm_set_states(struct pp_hwmgr *hwmgr, unsigned long state_id) -{ - struct pp_power_state *state; - int table_entries; - int i; - - table_entries = hwmgr->num_ps; - - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - if (state->id == state_id) { - memcpy(hwmgr->request_ps, state, hwmgr->ps_size); - return 0; - } - state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); - } - return -EINVAL; -} - -int psm_set_boot_states(struct pp_hwmgr *hwmgr) -{ - unsigned long state_id; - int ret = -EINVAL; - - if (!hwmgr->ps) - return 0; - - if (!psm_get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot, - &state_id)) - ret = psm_set_states(hwmgr, state_id); - - return ret; -} - -int psm_set_performance_states(struct pp_hwmgr *hwmgr) -{ - unsigned long state_id; - int ret = -EINVAL; - - if (!hwmgr->ps) - return 0; - - if (!psm_get_ui_state(hwmgr, PP_StateUILabel_Performance, - &state_id)) - ret = psm_set_states(hwmgr, state_id); - - return ret; -} - -int psm_set_user_performance_state(struct pp_hwmgr *hwmgr, - enum PP_StateUILabel label_id, - struct pp_power_state **state) -{ - int table_entries; - int i; - - if (!hwmgr->ps) - return 0; - - table_entries = hwmgr->num_ps; - *state = hwmgr->ps; - -restart_search: - for (i = 0; i < table_entries; i++) { - if ((*state)->classification.ui_label & label_id) - return 0; - *state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size); - } - - switch (label_id) { - case PP_StateUILabel_Battery: - case PP_StateUILabel_Balanced: - label_id = PP_StateUILabel_Performance; - goto restart_search; - default: - break; - } - return -EINVAL; -} - -static void power_state_management(struct pp_hwmgr *hwmgr, - struct pp_power_state *new_ps) -{ - struct pp_power_state *pcurrent; - struct pp_power_state *requested; - bool equal; - - if (new_ps != NULL) - requested = new_ps; - else - requested = hwmgr->request_ps; - - pcurrent = hwmgr->current_ps; - - phm_apply_state_adjust_rules(hwmgr, requested, pcurrent); - if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr, - &pcurrent->hardware, &requested->hardware, &equal))) - equal = false; - - if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) { - phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware); - memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size); - } -} - -int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_settings, - struct pp_power_state *new_ps) -{ - uint32_t index; - long workload; - - if (hwmgr->not_vf) { - if (!skip_display_settings) - phm_display_configuration_changed(hwmgr); - - if (hwmgr->ps) - power_state_management(hwmgr, new_ps); - else - /* - * for vega12/vega20 which does not support power state manager - * DAL clock limits should also be honoured - */ - phm_apply_clock_adjust_rules(hwmgr); - - if (!skip_display_settings) - phm_notify_smc_display_config_after_ps_adjustment(hwmgr); - } - - if (!phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level)) - hwmgr->dpm_level = hwmgr->request_dpm_level; - - if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { - index = fls(hwmgr->workload_mask); - index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0; - workload = hwmgr->workload_setting[index]; - - if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode) - hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0); - } - - return 0; -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h deleted file mode 100644 index b62d55f1f289..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef PP_PSM_H -#define PP_PSM_H - -#include "hwmgr.h" - -int psm_init_power_state_table(struct pp_hwmgr *hwmgr); -int psm_fini_power_state_table(struct pp_hwmgr *hwmgr); -int psm_set_boot_states(struct pp_hwmgr *hwmgr); -int psm_set_performance_states(struct pp_hwmgr *hwmgr); -int psm_set_user_performance_state(struct pp_hwmgr *hwmgr, - enum PP_StateUILabel label_id, - struct pp_power_state **state); -int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, - bool skip_display_settings, - struct pp_power_state *new_ps); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c deleted file mode 100644 index 01dc46dc9c8a..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c +++ /dev/null @@ -1,1562 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include "atom.h" -#include "ppatomctrl.h" -#include "atombios.h" -#include "cgs_common.h" -#include "ppevvmath.h" - -#define MEM_ID_MASK 0xff000000 -#define MEM_ID_SHIFT 24 -#define CLOCK_RANGE_MASK 0x00ffffff -#define CLOCK_RANGE_SHIFT 0 -#define LOW_NIBBLE_MASK 0xf -#define DATA_EQU_PREV 0 -#define DATA_FROM_TABLE 4 - -union voltage_object_info { - struct _ATOM_VOLTAGE_OBJECT_INFO v1; - struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; - struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; -}; - -static int atomctrl_retrieve_ac_timing( - uint8_t index, - ATOM_INIT_REG_BLOCK *reg_block, - pp_atomctrl_mc_reg_table *table) -{ - uint32_t i, j; - uint8_t tmem_id; - ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) - ((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize)); - - uint8_t num_ranges = 0; - - while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK && - num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES) { - tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); - - if (index == tmem_id) { - table->mc_reg_table_entry[num_ranges].mclk_max = - (uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >> - CLOCK_RANGE_SHIFT); - - for (i = 0, j = 1; i < table->last; i++) { - if ((table->mc_reg_address[i].uc_pre_reg_data & - LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { - table->mc_reg_table_entry[num_ranges].mc_data[i] = - (uint32_t)*((uint32_t *)reg_data + j); - j++; - } else if ((table->mc_reg_address[i].uc_pre_reg_data & - LOW_NIBBLE_MASK) == DATA_EQU_PREV) { - table->mc_reg_table_entry[num_ranges].mc_data[i] = - table->mc_reg_table_entry[num_ranges].mc_data[i-1]; - } - } - num_ranges++; - } - - reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) - ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ; - } - - PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK), - "Invalid VramInfo table.", return -1); - table->num_entries = num_ranges; - - return 0; -} - -/** - * Get memory clock AC timing registers index from VBIOS table - * VBIOS set end of memory clock AC timing registers by ucPreRegDataLength bit6 = 1 - * @param reg_block the address ATOM_INIT_REG_BLOCK - * @param table the address of MCRegTable - * @return 0 - */ -static int atomctrl_set_mc_reg_address_table( - ATOM_INIT_REG_BLOCK *reg_block, - pp_atomctrl_mc_reg_table *table) -{ - uint8_t i = 0; - uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize)) - / sizeof(ATOM_INIT_REG_INDEX_FORMAT)); - ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; - - num_entries--; /* subtract 1 data end mark entry */ - - PP_ASSERT_WITH_CODE((num_entries <= VBIOS_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -1); - - /* ucPreRegDataLength bit6 = 1 is the end of memory clock AC timing registers */ - while ((!(format->ucPreRegDataLength & ACCESS_PLACEHOLDER)) && - (i < num_entries)) { - table->mc_reg_address[i].s1 = - (uint16_t)(le16_to_cpu(format->usRegIndex)); - table->mc_reg_address[i].uc_pre_reg_data = - format->ucPreRegDataLength; - - i++; - format = (ATOM_INIT_REG_INDEX_FORMAT *) - ((uint8_t *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); - } - - table->last = i; - return 0; -} - -int atomctrl_initialize_mc_reg_table( - struct pp_hwmgr *hwmgr, - uint8_t module_index, - pp_atomctrl_mc_reg_table *table) -{ - ATOM_VRAM_INFO_HEADER_V2_1 *vram_info; - ATOM_INIT_REG_BLOCK *reg_block; - int result = 0; - u8 frev, crev; - u16 size; - - vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *) - smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev); - - if (module_index >= vram_info->ucNumOfVRAMModule) { - pr_err("Invalid VramInfo table."); - result = -1; - } else if (vram_info->sHeader.ucTableFormatRevision < 2) { - pr_err("Invalid VramInfo table."); - result = -1; - } - - if (0 == result) { - reg_block = (ATOM_INIT_REG_BLOCK *) - ((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset)); - result = atomctrl_set_mc_reg_address_table(reg_block, table); - } - - if (0 == result) { - result = atomctrl_retrieve_ac_timing(module_index, - reg_block, table); - } - - return result; -} - -/** - * Set DRAM timings based on engine clock and memory clock. - */ -int atomctrl_set_engine_dram_timings_rv770( - struct pp_hwmgr *hwmgr, - uint32_t engine_clock, - uint32_t memory_clock) -{ - struct amdgpu_device *adev = hwmgr->adev; - - SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters; - - /* They are both in 10KHz Units. */ - engine_clock_parameters.ulTargetEngineClock = - cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) | - ((COMPUTE_ENGINE_PLL_PARAM << 24))); - - /* in 10 khz units.*/ - engine_clock_parameters.sReserved.ulClock = - cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); - - return amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings), - (uint32_t *)&engine_clock_parameters); -} - -/** - * Private Function to get the PowerPlay Table Address. - * WARNING: The tabled returned by this function is in - * dynamically allocated memory. - * The caller has to release if by calling kfree. - */ -static ATOM_VOLTAGE_OBJECT_INFO *get_voltage_info_table(void *device) -{ - int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); - u8 frev, crev; - u16 size; - union voltage_object_info *voltage_info; - - voltage_info = (union voltage_object_info *) - smu_atom_get_data_table(device, index, - &size, &frev, &crev); - - if (voltage_info != NULL) - return (ATOM_VOLTAGE_OBJECT_INFO *) &(voltage_info->v3); - else - return NULL; -} - -static const ATOM_VOLTAGE_OBJECT_V3 *atomctrl_lookup_voltage_type_v3( - const ATOM_VOLTAGE_OBJECT_INFO_V3_1 * voltage_object_info_table, - uint8_t voltage_type, uint8_t voltage_mode) -{ - unsigned int size = le16_to_cpu(voltage_object_info_table->sHeader.usStructureSize); - unsigned int offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); - uint8_t *start = (uint8_t *)voltage_object_info_table; - - while (offset < size) { - const ATOM_VOLTAGE_OBJECT_V3 *voltage_object = - (const ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); - - if (voltage_type == voltage_object->asGpioVoltageObj.sHeader.ucVoltageType && - voltage_mode == voltage_object->asGpioVoltageObj.sHeader.ucVoltageMode) - return voltage_object; - - offset += le16_to_cpu(voltage_object->asGpioVoltageObj.sHeader.usSize); - } - - return NULL; -} - -/** atomctrl_get_memory_pll_dividers_si(). - * - * @param hwmgr input parameter: pointer to HwMgr - * @param clock_value input parameter: memory clock - * @param dividers output parameter: memory PLL dividers - * @param strobe_mode input parameter: 1 for strobe mode, 0 for performance mode - */ -int atomctrl_get_memory_pll_dividers_si( - struct pp_hwmgr *hwmgr, - uint32_t clock_value, - pp_atomctrl_memory_clock_param *mpll_param, - bool strobe_mode) -{ - struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters; - int result; - - mpll_parameters.ulClock = cpu_to_le32(clock_value); - mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam), - (uint32_t *)&mpll_parameters); - - if (0 == result) { - mpll_param->mpll_fb_divider.clk_frac = - le16_to_cpu(mpll_parameters.ulFbDiv.usFbDivFrac); - mpll_param->mpll_fb_divider.cl_kf = - le16_to_cpu(mpll_parameters.ulFbDiv.usFbDiv); - mpll_param->mpll_post_divider = - (uint32_t)mpll_parameters.ucPostDiv; - mpll_param->vco_mode = - (uint32_t)(mpll_parameters.ucPllCntlFlag & - MPLL_CNTL_FLAG_VCO_MODE_MASK); - mpll_param->yclk_sel = - (uint32_t)((mpll_parameters.ucPllCntlFlag & - MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0); - mpll_param->qdr = - (uint32_t)((mpll_parameters.ucPllCntlFlag & - MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0); - mpll_param->half_rate = - (uint32_t)((mpll_parameters.ucPllCntlFlag & - MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0); - mpll_param->dll_speed = - (uint32_t)(mpll_parameters.ucDllSpeed); - mpll_param->bw_ctrl = - (uint32_t)(mpll_parameters.ucBWCntl); - } - - return result; -} - -/** atomctrl_get_memory_pll_dividers_vi(). - * - * @param hwmgr input parameter: pointer to HwMgr - * @param clock_value input parameter: memory clock - * @param dividers output parameter: memory PLL dividers - */ -int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, - uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param) -{ - struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters; - int result; - - mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam), - (uint32_t *)&mpll_parameters); - - if (!result) - mpll_param->mpll_post_divider = - (uint32_t)mpll_parameters.ulClock.ucPostDiv; - - return result; -} - -int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, - uint32_t clock_value, - pp_atomctrl_memory_clock_param_ai *mpll_param) -{ - struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {{0}, 0, 0}; - int result; - - mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam), - (uint32_t *)&mpll_parameters); - - /* VEGAM's mpll takes sometime to finish computing */ - udelay(10); - - if (!result) { - mpll_param->ulMclk_fcw_int = - le16_to_cpu(mpll_parameters.usMclk_fcw_int); - mpll_param->ulMclk_fcw_frac = - le16_to_cpu(mpll_parameters.usMclk_fcw_frac); - mpll_param->ulClock = - le32_to_cpu(mpll_parameters.ulClock.ulClock); - mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv; - } - - return result; -} - -int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, - uint32_t clock_value, - pp_atomctrl_clock_dividers_kong *dividers) -{ - struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters; - int result; - - pll_parameters.ulClock = cpu_to_le32(clock_value); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), - (uint32_t *)&pll_parameters); - - if (0 == result) { - dividers->pll_post_divider = pll_parameters.ucPostDiv; - dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); - } - - return result; -} - -int atomctrl_get_engine_pll_dividers_vi( - struct pp_hwmgr *hwmgr, - uint32_t clock_value, - pp_atomctrl_clock_dividers_vi *dividers) -{ - struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters; - int result; - - pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value); - pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), - (uint32_t *)&pll_patameters); - - if (0 == result) { - dividers->pll_post_divider = - pll_patameters.ulClock.ucPostDiv; - dividers->real_clock = - le32_to_cpu(pll_patameters.ulClock.ulClock); - - dividers->ul_fb_div.ul_fb_div_frac = - le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac); - dividers->ul_fb_div.ul_fb_div = - le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv); - - dividers->uc_pll_ref_div = - pll_patameters.ucPllRefDiv; - dividers->uc_pll_post_div = - pll_patameters.ucPllPostDiv; - dividers->uc_pll_cntl_flag = - pll_patameters.ucPllCntlFlag; - } - - return result; -} - -int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, - uint32_t clock_value, - pp_atomctrl_clock_dividers_ai *dividers) -{ - struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters; - int result; - - pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value); - pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), - (uint32_t *)&pll_patameters); - - if (0 == result) { - dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac); - dividers->usSclk_fcw_int = le16_to_cpu(pll_patameters.usSclk_fcw_int); - dividers->ucSclkPostDiv = pll_patameters.ucSclkPostDiv; - dividers->ucSclkVcoMode = pll_patameters.ucSclkVcoMode; - dividers->ucSclkPllRange = pll_patameters.ucSclkPllRange; - dividers->ucSscEnable = pll_patameters.ucSscEnable; - dividers->usSsc_fcw1_frac = le16_to_cpu(pll_patameters.usSsc_fcw1_frac); - dividers->usSsc_fcw1_int = le16_to_cpu(pll_patameters.usSsc_fcw1_int); - dividers->usPcc_fcw_int = le16_to_cpu(pll_patameters.usPcc_fcw_int); - dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac); - dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac); - } - return result; -} - -int atomctrl_get_dfs_pll_dividers_vi( - struct pp_hwmgr *hwmgr, - uint32_t clock_value, - pp_atomctrl_clock_dividers_vi *dividers) -{ - struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters; - int result; - - pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value); - pll_patameters.ulClock.ucPostDiv = - COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), - (uint32_t *)&pll_patameters); - - if (0 == result) { - dividers->pll_post_divider = - pll_patameters.ulClock.ucPostDiv; - dividers->real_clock = - le32_to_cpu(pll_patameters.ulClock.ulClock); - - dividers->ul_fb_div.ul_fb_div_frac = - le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac); - dividers->ul_fb_div.ul_fb_div = - le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv); - - dividers->uc_pll_ref_div = - pll_patameters.ucPllRefDiv; - dividers->uc_pll_post_div = - pll_patameters.ucPllPostDiv; - dividers->uc_pll_cntl_flag = - pll_patameters.ucPllCntlFlag; - } - - return result; -} - -/** - * Get the reference clock in 10KHz - */ -uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr) -{ - ATOM_FIRMWARE_INFO *fw_info; - u8 frev, crev; - u16 size; - uint32_t clock; - - fw_info = (ATOM_FIRMWARE_INFO *) - smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, FirmwareInfo), - &size, &frev, &crev); - - if (fw_info == NULL) - clock = 2700; - else - clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock)); - - return clock; -} - -/** - * Returns true if the given voltage type is controlled by GPIO pins. - * voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC, - * SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ. - * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE - */ -bool atomctrl_is_voltage_controlled_by_gpio_v3( - struct pp_hwmgr *hwmgr, - uint8_t voltage_type, - uint8_t voltage_mode) -{ - ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info = - (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev); - bool ret; - - PP_ASSERT_WITH_CODE((NULL != voltage_info), - "Could not find Voltage Table in BIOS.", return false;); - - ret = (NULL != atomctrl_lookup_voltage_type_v3 - (voltage_info, voltage_type, voltage_mode)) ? true : false; - - return ret; -} - -int atomctrl_get_voltage_table_v3( - struct pp_hwmgr *hwmgr, - uint8_t voltage_type, - uint8_t voltage_mode, - pp_atomctrl_voltage_table *voltage_table) -{ - ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info = - (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev); - const ATOM_VOLTAGE_OBJECT_V3 *voltage_object; - unsigned int i; - - PP_ASSERT_WITH_CODE((NULL != voltage_info), - "Could not find Voltage Table in BIOS.", return -1;); - - voltage_object = atomctrl_lookup_voltage_type_v3 - (voltage_info, voltage_type, voltage_mode); - - if (voltage_object == NULL) - return -1; - - PP_ASSERT_WITH_CODE( - (voltage_object->asGpioVoltageObj.ucGpioEntryNum <= - PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES), - "Too many voltage entries!", - return -1; - ); - - for (i = 0; i < voltage_object->asGpioVoltageObj.ucGpioEntryNum; i++) { - voltage_table->entries[i].value = - le16_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].usVoltageValue); - voltage_table->entries[i].smio_low = - le32_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].ulVoltageId); - } - - voltage_table->mask_low = - le32_to_cpu(voltage_object->asGpioVoltageObj.ulGpioMaskVal); - voltage_table->count = - voltage_object->asGpioVoltageObj.ucGpioEntryNum; - voltage_table->phase_delay = - voltage_object->asGpioVoltageObj.ucPhaseDelay; - - return 0; -} - -static bool atomctrl_lookup_gpio_pin( - ATOM_GPIO_PIN_LUT * gpio_lookup_table, - const uint32_t pinId, - pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment) -{ - unsigned int size = le16_to_cpu(gpio_lookup_table->sHeader.usStructureSize); - unsigned int offset = offsetof(ATOM_GPIO_PIN_LUT, asGPIO_Pin[0]); - uint8_t *start = (uint8_t *)gpio_lookup_table; - - while (offset < size) { - const ATOM_GPIO_PIN_ASSIGNMENT *pin_assignment = - (const ATOM_GPIO_PIN_ASSIGNMENT *)(start + offset); - - if (pinId == pin_assignment->ucGPIO_ID) { - gpio_pin_assignment->uc_gpio_pin_bit_shift = - pin_assignment->ucGpioPinBitShift; - gpio_pin_assignment->us_gpio_pin_aindex = - le16_to_cpu(pin_assignment->usGpioPin_AIndex); - return true; - } - - offset += offsetof(ATOM_GPIO_PIN_ASSIGNMENT, ucGPIO_ID) + 1; - } - - return false; -} - -/** - * Private Function to get the PowerPlay Table Address. - * WARNING: The tabled returned by this function is in - * dynamically allocated memory. - * The caller has to release if by calling kfree. - */ -static ATOM_GPIO_PIN_LUT *get_gpio_lookup_table(void *device) -{ - u8 frev, crev; - u16 size; - void *table_address; - - table_address = (ATOM_GPIO_PIN_LUT *) - smu_atom_get_data_table(device, - GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT), - &size, &frev, &crev); - - PP_ASSERT_WITH_CODE((NULL != table_address), - "Error retrieving BIOS Table Address!", return NULL;); - - return (ATOM_GPIO_PIN_LUT *)table_address; -} - -/** - * Returns 1 if the given pin id find in lookup table. - */ -bool atomctrl_get_pp_assign_pin( - struct pp_hwmgr *hwmgr, - const uint32_t pinId, - pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment) -{ - bool bRet = false; - ATOM_GPIO_PIN_LUT *gpio_lookup_table = - get_gpio_lookup_table(hwmgr->adev); - - PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table), - "Could not find GPIO lookup Table in BIOS.", return false); - - bRet = atomctrl_lookup_gpio_pin(gpio_lookup_table, pinId, - gpio_pin_assignment); - - return bRet; -} - -int atomctrl_calculate_voltage_evv_on_sclk( - struct pp_hwmgr *hwmgr, - uint8_t voltage_type, - uint32_t sclk, - uint16_t virtual_voltage_Id, - uint16_t *voltage, - uint16_t dpm_level, - bool debug) -{ - ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo; - struct amdgpu_device *adev = hwmgr->adev; - EFUSE_LINEAR_FUNC_PARAM sRO_fuse; - EFUSE_LINEAR_FUNC_PARAM sCACm_fuse; - EFUSE_LINEAR_FUNC_PARAM sCACb_fuse; - EFUSE_LOGISTIC_FUNC_PARAM sKt_Beta_fuse; - EFUSE_LOGISTIC_FUNC_PARAM sKv_m_fuse; - EFUSE_LOGISTIC_FUNC_PARAM sKv_b_fuse; - EFUSE_INPUT_PARAMETER sInput_FuseValues; - READ_EFUSE_VALUE_PARAMETER sOutput_FuseValues; - - uint32_t ul_RO_fused, ul_CACb_fused, ul_CACm_fused, ul_Kt_Beta_fused, ul_Kv_m_fused, ul_Kv_b_fused; - fInt fSM_A0, fSM_A1, fSM_A2, fSM_A3, fSM_A4, fSM_A5, fSM_A6, fSM_A7; - fInt fMargin_RO_a, fMargin_RO_b, fMargin_RO_c, fMargin_fixed, fMargin_FMAX_mean, fMargin_Plat_mean, fMargin_FMAX_sigma, fMargin_Plat_sigma, fMargin_DC_sigma; - fInt fLkg_FT, repeat; - fInt fMicro_FMAX, fMicro_CR, fSigma_FMAX, fSigma_CR, fSigma_DC, fDC_SCLK, fSquared_Sigma_DC, fSquared_Sigma_CR, fSquared_Sigma_FMAX; - fInt fRLL_LoadLine, fPowerDPMx, fDerateTDP, fVDDC_base, fA_Term, fC_Term, fB_Term, fRO_DC_margin; - fInt fRO_fused, fCACm_fused, fCACb_fused, fKv_m_fused, fKv_b_fused, fKt_Beta_fused, fFT_Lkg_V0NORM; - fInt fSclk_margin, fSclk, fEVV_V; - fInt fV_min, fV_max, fT_prod, fLKG_Factor, fT_FT, fV_FT, fV_x, fTDP_Power, fTDP_Power_right, fTDP_Power_left, fTDP_Current, fV_NL; - uint32_t ul_FT_Lkg_V0NORM; - fInt fLn_MaxDivMin, fMin, fAverage, fRange; - fInt fRoots[2]; - fInt fStepSize = GetScaledFraction(625, 100000); - - int result; - - getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *) - smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo), - NULL, NULL, NULL); - - if (!getASICProfilingInfo) - return -1; - - if (getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 || - (getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 && - getASICProfilingInfo->asHeader.ucTableContentRevision < 4)) - return -1; - - /*----------------------------------------------------------- - *GETTING MULTI-STEP PARAMETERS RELATED TO CURRENT DPM LEVEL - *----------------------------------------------------------- - */ - fRLL_LoadLine = Divide(getASICProfilingInfo->ulLoadLineSlop, 1000); - - switch (dpm_level) { - case 1: - fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm1)); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM1), 1000); - break; - case 2: - fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm2)); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM2), 1000); - break; - case 3: - fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm3)); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM3), 1000); - break; - case 4: - fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm4)); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM4), 1000); - break; - case 5: - fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm5)); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM5), 1000); - break; - case 6: - fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm6)); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM6), 1000); - break; - case 7: - fPowerDPMx = Convert_ULONG_ToFraction(le16_to_cpu(getASICProfilingInfo->usPowerDpm7)); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM7), 1000); - break; - default: - pr_err("DPM Level not supported\n"); - fPowerDPMx = Convert_ULONG_ToFraction(1); - fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM0), 1000); - } - - /*------------------------- - * DECODING FUSE VALUES - * ------------------------ - */ - /*Decode RO_Fused*/ - sRO_fuse = getASICProfilingInfo->sRoFuse; - - sInput_FuseValues.usEfuseIndex = sRO_fuse.usEfuseIndex; - sInput_FuseValues.ucBitShift = sRO_fuse.ucEfuseBitLSB; - sInput_FuseValues.ucBitLength = sRO_fuse.ucEfuseLength; - - sOutput_FuseValues.sEfuse = sInput_FuseValues; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&sOutput_FuseValues); - - if (result) - return result; - - /* Finally, the actual fuse value */ - ul_RO_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue); - fMin = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseMin), 1); - fRange = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseEncodeRange), 1); - fRO_fused = fDecodeLinearFuse(ul_RO_fused, fMin, fRange, sRO_fuse.ucEfuseLength); - - sCACm_fuse = getASICProfilingInfo->sCACm; - - sInput_FuseValues.usEfuseIndex = sCACm_fuse.usEfuseIndex; - sInput_FuseValues.ucBitShift = sCACm_fuse.ucEfuseBitLSB; - sInput_FuseValues.ucBitLength = sCACm_fuse.ucEfuseLength; - - sOutput_FuseValues.sEfuse = sInput_FuseValues; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&sOutput_FuseValues); - - if (result) - return result; - - ul_CACm_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue); - fMin = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseMin), 1000); - fRange = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseEncodeRange), 1000); - - fCACm_fused = fDecodeLinearFuse(ul_CACm_fused, fMin, fRange, sCACm_fuse.ucEfuseLength); - - sCACb_fuse = getASICProfilingInfo->sCACb; - - sInput_FuseValues.usEfuseIndex = sCACb_fuse.usEfuseIndex; - sInput_FuseValues.ucBitShift = sCACb_fuse.ucEfuseBitLSB; - sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength; - sOutput_FuseValues.sEfuse = sInput_FuseValues; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&sOutput_FuseValues); - - if (result) - return result; - - ul_CACb_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue); - fMin = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseMin), 1000); - fRange = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseEncodeRange), 1000); - - fCACb_fused = fDecodeLinearFuse(ul_CACb_fused, fMin, fRange, sCACb_fuse.ucEfuseLength); - - sKt_Beta_fuse = getASICProfilingInfo->sKt_b; - - sInput_FuseValues.usEfuseIndex = sKt_Beta_fuse.usEfuseIndex; - sInput_FuseValues.ucBitShift = sKt_Beta_fuse.ucEfuseBitLSB; - sInput_FuseValues.ucBitLength = sKt_Beta_fuse.ucEfuseLength; - - sOutput_FuseValues.sEfuse = sInput_FuseValues; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&sOutput_FuseValues); - - if (result) - return result; - - ul_Kt_Beta_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue); - fAverage = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeAverage), 1000); - fRange = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeRange), 1000); - - fKt_Beta_fused = fDecodeLogisticFuse(ul_Kt_Beta_fused, - fAverage, fRange, sKt_Beta_fuse.ucEfuseLength); - - sKv_m_fuse = getASICProfilingInfo->sKv_m; - - sInput_FuseValues.usEfuseIndex = sKv_m_fuse.usEfuseIndex; - sInput_FuseValues.ucBitShift = sKv_m_fuse.ucEfuseBitLSB; - sInput_FuseValues.ucBitLength = sKv_m_fuse.ucEfuseLength; - - sOutput_FuseValues.sEfuse = sInput_FuseValues; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&sOutput_FuseValues); - if (result) - return result; - - ul_Kv_m_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue); - fAverage = GetScaledFraction(le32_to_cpu(sKv_m_fuse.ulEfuseEncodeAverage), 1000); - fRange = GetScaledFraction((le32_to_cpu(sKv_m_fuse.ulEfuseEncodeRange) & 0x7fffffff), 1000); - fRange = fMultiply(fRange, ConvertToFraction(-1)); - - fKv_m_fused = fDecodeLogisticFuse(ul_Kv_m_fused, - fAverage, fRange, sKv_m_fuse.ucEfuseLength); - - sKv_b_fuse = getASICProfilingInfo->sKv_b; - - sInput_FuseValues.usEfuseIndex = sKv_b_fuse.usEfuseIndex; - sInput_FuseValues.ucBitShift = sKv_b_fuse.ucEfuseBitLSB; - sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength; - sOutput_FuseValues.sEfuse = sInput_FuseValues; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&sOutput_FuseValues); - - if (result) - return result; - - ul_Kv_b_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue); - fAverage = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeAverage), 1000); - fRange = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeRange), 1000); - - fKv_b_fused = fDecodeLogisticFuse(ul_Kv_b_fused, - fAverage, fRange, sKv_b_fuse.ucEfuseLength); - - /* Decoding the Leakage - No special struct container */ - /* - * usLkgEuseIndex=56 - * ucLkgEfuseBitLSB=6 - * ucLkgEfuseLength=10 - * ulLkgEncodeLn_MaxDivMin=69077 - * ulLkgEncodeMax=1000000 - * ulLkgEncodeMin=1000 - * ulEfuseLogisticAlpha=13 - */ - - sInput_FuseValues.usEfuseIndex = getASICProfilingInfo->usLkgEuseIndex; - sInput_FuseValues.ucBitShift = getASICProfilingInfo->ucLkgEfuseBitLSB; - sInput_FuseValues.ucBitLength = getASICProfilingInfo->ucLkgEfuseLength; - - sOutput_FuseValues.sEfuse = sInput_FuseValues; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&sOutput_FuseValues); - - if (result) - return result; - - ul_FT_Lkg_V0NORM = le32_to_cpu(sOutput_FuseValues.ulEfuseValue); - fLn_MaxDivMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeLn_MaxDivMin), 10000); - fMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeMin), 10000); - - fFT_Lkg_V0NORM = fDecodeLeakageID(ul_FT_Lkg_V0NORM, - fLn_MaxDivMin, fMin, getASICProfilingInfo->ucLkgEfuseLength); - fLkg_FT = fFT_Lkg_V0NORM; - - /*------------------------------------------- - * PART 2 - Grabbing all required values - *------------------------------------------- - */ - fSM_A0 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A0), 1000000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A0_sign))); - fSM_A1 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A1), 1000000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A1_sign))); - fSM_A2 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A2), 100000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A2_sign))); - fSM_A3 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A3), 1000000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A3_sign))); - fSM_A4 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A4), 1000000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A4_sign))); - fSM_A5 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A5), 1000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A5_sign))); - fSM_A6 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A6), 1000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A6_sign))); - fSM_A7 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A7), 1000), - ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A7_sign))); - - fMargin_RO_a = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_a)); - fMargin_RO_b = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_b)); - fMargin_RO_c = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_c)); - - fMargin_fixed = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_fixed)); - - fMargin_FMAX_mean = GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_mean), 10000); - fMargin_Plat_mean = GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulMargin_plat_mean), 10000); - fMargin_FMAX_sigma = GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_sigma), 10000); - fMargin_Plat_sigma = GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulMargin_plat_sigma), 10000); - - fMargin_DC_sigma = GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulMargin_DC_sigma), 100); - fMargin_DC_sigma = fDivide(fMargin_DC_sigma, ConvertToFraction(1000)); - - fCACm_fused = fDivide(fCACm_fused, ConvertToFraction(100)); - fCACb_fused = fDivide(fCACb_fused, ConvertToFraction(100)); - fKt_Beta_fused = fDivide(fKt_Beta_fused, ConvertToFraction(100)); - fKv_m_fused = fNegate(fDivide(fKv_m_fused, ConvertToFraction(100))); - fKv_b_fused = fDivide(fKv_b_fused, ConvertToFraction(10)); - - fSclk = GetScaledFraction(sclk, 100); - - fV_max = fDivide(GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulMaxVddc), 1000), ConvertToFraction(4)); - fT_prod = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulBoardCoreTemp), 10); - fLKG_Factor = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulEvvLkgFactor), 100); - fT_FT = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLeakageTemp), 10); - fV_FT = fDivide(GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulLeakageVoltage), 1000), ConvertToFraction(4)); - fV_min = fDivide(GetScaledFraction( - le32_to_cpu(getASICProfilingInfo->ulMinVddc), 1000), ConvertToFraction(4)); - - /*----------------------- - * PART 3 - *----------------------- - */ - - fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4, fSclk), fSM_A5)); - fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b); - fC_Term = fAdd(fMargin_RO_c, - fAdd(fMultiply(fSM_A0, fLkg_FT), - fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT, fSclk)), - fAdd(fMultiply(fSM_A3, fSclk), - fSubtract(fSM_A7, fRO_fused))))); - - fVDDC_base = fSubtract(fRO_fused, - fSubtract(fMargin_RO_c, - fSubtract(fSM_A3, fMultiply(fSM_A1, fSclk)))); - fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0, fSclk), fSM_A2)); - - repeat = fSubtract(fVDDC_base, - fDivide(fMargin_DC_sigma, ConvertToFraction(1000))); - - fRO_DC_margin = fAdd(fMultiply(fMargin_RO_a, - fGetSquare(repeat)), - fAdd(fMultiply(fMargin_RO_b, repeat), - fMargin_RO_c)); - - fDC_SCLK = fSubtract(fRO_fused, - fSubtract(fRO_DC_margin, - fSubtract(fSM_A3, - fMultiply(fSM_A2, repeat)))); - fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0, repeat), fSM_A1)); - - fSigma_DC = fSubtract(fSclk, fDC_SCLK); - - fMicro_FMAX = fMultiply(fSclk, fMargin_FMAX_mean); - fMicro_CR = fMultiply(fSclk, fMargin_Plat_mean); - fSigma_FMAX = fMultiply(fSclk, fMargin_FMAX_sigma); - fSigma_CR = fMultiply(fSclk, fMargin_Plat_sigma); - - fSquared_Sigma_DC = fGetSquare(fSigma_DC); - fSquared_Sigma_CR = fGetSquare(fSigma_CR); - fSquared_Sigma_FMAX = fGetSquare(fSigma_FMAX); - - fSclk_margin = fAdd(fMicro_FMAX, - fAdd(fMicro_CR, - fAdd(fMargin_fixed, - fSqrt(fAdd(fSquared_Sigma_FMAX, - fAdd(fSquared_Sigma_DC, fSquared_Sigma_CR)))))); - /* - fA_Term = fSM_A4 * (fSclk + fSclk_margin) + fSM_A5; - fB_Term = fSM_A2 * (fSclk + fSclk_margin) + fSM_A6; - fC_Term = fRO_DC_margin + fSM_A0 * fLkg_FT + fSM_A1 * fLkg_FT * (fSclk + fSclk_margin) + fSM_A3 * (fSclk + fSclk_margin) + fSM_A7 - fRO_fused; - */ - - fA_Term = fAdd(fMultiply(fSM_A4, fAdd(fSclk, fSclk_margin)), fSM_A5); - fB_Term = fAdd(fMultiply(fSM_A2, fAdd(fSclk, fSclk_margin)), fSM_A6); - fC_Term = fAdd(fRO_DC_margin, - fAdd(fMultiply(fSM_A0, fLkg_FT), - fAdd(fMultiply(fMultiply(fSM_A1, fLkg_FT), - fAdd(fSclk, fSclk_margin)), - fAdd(fMultiply(fSM_A3, - fAdd(fSclk, fSclk_margin)), - fSubtract(fSM_A7, fRO_fused))))); - - SolveQuadracticEqn(fA_Term, fB_Term, fC_Term, fRoots); - - if (GreaterThan(fRoots[0], fRoots[1])) - fEVV_V = fRoots[1]; - else - fEVV_V = fRoots[0]; - - if (GreaterThan(fV_min, fEVV_V)) - fEVV_V = fV_min; - else if (GreaterThan(fEVV_V, fV_max)) - fEVV_V = fSubtract(fV_max, fStepSize); - - fEVV_V = fRoundUpByStepSize(fEVV_V, fStepSize, 0); - - /*----------------- - * PART 4 - *----------------- - */ - - fV_x = fV_min; - - while (GreaterThan(fAdd(fV_max, fStepSize), fV_x)) { - fTDP_Power_left = fMultiply(fMultiply(fMultiply(fAdd( - fMultiply(fCACm_fused, fV_x), fCACb_fused), fSclk), - fGetSquare(fV_x)), fDerateTDP); - - fTDP_Power_right = fMultiply(fFT_Lkg_V0NORM, fMultiply(fLKG_Factor, - fMultiply(fExponential(fMultiply(fAdd(fMultiply(fKv_m_fused, - fT_prod), fKv_b_fused), fV_x)), fV_x))); - fTDP_Power_right = fMultiply(fTDP_Power_right, fExponential(fMultiply( - fKt_Beta_fused, fT_prod))); - fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply( - fAdd(fMultiply(fKv_m_fused, fT_prod), fKv_b_fused), fV_FT))); - fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply( - fKt_Beta_fused, fT_FT))); - - fTDP_Power = fAdd(fTDP_Power_left, fTDP_Power_right); - - fTDP_Current = fDivide(fTDP_Power, fV_x); - - fV_NL = fAdd(fV_x, fDivide(fMultiply(fTDP_Current, fRLL_LoadLine), - ConvertToFraction(10))); - - fV_NL = fRoundUpByStepSize(fV_NL, fStepSize, 0); - - if (GreaterThan(fV_max, fV_NL) && - (GreaterThan(fV_NL, fEVV_V) || - Equal(fV_NL, fEVV_V))) { - fV_NL = fMultiply(fV_NL, ConvertToFraction(1000)); - - *voltage = (uint16_t)fV_NL.partial.real; - break; - } else - fV_x = fAdd(fV_x, fStepSize); - } - - return result; -} - -/** atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table. - * @param hwmgr input: pointer to hwManager - * @param voltage_type input: type of EVV voltage VDDC or VDDGFX - * @param sclk input: in 10Khz unit. DPM state SCLK frequency - * which is define in PPTable SCLK/VDDC dependence - * table associated with this virtual_voltage_Id - * @param virtual_voltage_Id input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08 - * @param voltage output: real voltage level in unit of mv - */ -int atomctrl_get_voltage_evv_on_sclk( - struct pp_hwmgr *hwmgr, - uint8_t voltage_type, - uint32_t sclk, uint16_t virtual_voltage_Id, - uint16_t *voltage) -{ - struct amdgpu_device *adev = hwmgr->adev; - GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space; - int result; - - get_voltage_info_param_space.ucVoltageType = - voltage_type; - get_voltage_info_param_space.ucVoltageMode = - ATOM_GET_VOLTAGE_EVV_VOLTAGE; - get_voltage_info_param_space.usVoltageLevel = - cpu_to_le16(virtual_voltage_Id); - get_voltage_info_param_space.ulSCLKFreq = - cpu_to_le32(sclk); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), - (uint32_t *)&get_voltage_info_param_space); - - *voltage = result ? 0 : - le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *) - (&get_voltage_info_param_space))->usVoltageLevel); - - return result; -} - -/** - * atomctrl_get_voltage_evv gets voltage via call to ATOM COMMAND table. - * @param hwmgr input: pointer to hwManager - * @param virtual_voltage_id input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08 - * @param voltage output: real voltage level in unit of mv - */ -int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, - uint16_t virtual_voltage_id, - uint16_t *voltage) -{ - struct amdgpu_device *adev = hwmgr->adev; - GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space; - int result; - int entry_id; - - /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ - for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { - if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { - /* found */ - break; - } - } - - if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { - pr_debug("Can't find requested voltage id in vddc_dependency_on_sclk table!\n"); - return -EINVAL; - } - - get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC; - get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; - get_voltage_info_param_space.usVoltageLevel = virtual_voltage_id; - get_voltage_info_param_space.ulSCLKFreq = - cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), - (uint32_t *)&get_voltage_info_param_space); - - if (0 != result) - return result; - - *voltage = le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *) - (&get_voltage_info_param_space))->usVoltageLevel); - - return result; -} - -/** - * Get the mpll reference clock in 10KHz - */ -uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr) -{ - ATOM_COMMON_TABLE_HEADER *fw_info; - uint32_t clock; - u8 frev, crev; - u16 size; - - fw_info = (ATOM_COMMON_TABLE_HEADER *) - smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, FirmwareInfo), - &size, &frev, &crev); - - if (fw_info == NULL) - clock = 2700; - else { - if ((fw_info->ucTableFormatRevision == 2) && - (le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V2_1))) { - ATOM_FIRMWARE_INFO_V2_1 *fwInfo_2_1 = - (ATOM_FIRMWARE_INFO_V2_1 *)fw_info; - clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock)); - } else { - ATOM_FIRMWARE_INFO *fwInfo_0_0 = - (ATOM_FIRMWARE_INFO *)fw_info; - clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock)); - } - } - - return clock; -} - -/** - * Get the asic internal spread spectrum table - */ -static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device) -{ - ATOM_ASIC_INTERNAL_SS_INFO *table = NULL; - u8 frev, crev; - u16 size; - - table = (ATOM_ASIC_INTERNAL_SS_INFO *) - smu_atom_get_data_table(device, - GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info), - &size, &frev, &crev); - - return table; -} - -/** - * Get the asic internal spread spectrum assignment - */ -static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr, - const uint8_t clockSource, - const uint32_t clockSpeed, - pp_atomctrl_internal_ss_info *ssEntry) -{ - ATOM_ASIC_INTERNAL_SS_INFO *table; - ATOM_ASIC_SS_ASSIGNMENT *ssInfo; - int entry_found = 0; - - memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info)); - - table = asic_internal_ss_get_ss_table(hwmgr->adev); - - if (NULL == table) - return -1; - - ssInfo = &table->asSpreadSpectrum[0]; - - while (((uint8_t *)ssInfo - (uint8_t *)table) < - le16_to_cpu(table->sHeader.usStructureSize)) { - if ((clockSource == ssInfo->ucClockIndication) && - ((uint32_t)clockSpeed <= le32_to_cpu(ssInfo->ulTargetClockRange))) { - entry_found = 1; - break; - } - - ssInfo = (ATOM_ASIC_SS_ASSIGNMENT *)((uint8_t *)ssInfo + - sizeof(ATOM_ASIC_SS_ASSIGNMENT)); - } - - if (entry_found) { - ssEntry->speed_spectrum_percentage = - le16_to_cpu(ssInfo->usSpreadSpectrumPercentage); - ssEntry->speed_spectrum_rate = le16_to_cpu(ssInfo->usSpreadRateInKhz); - - if (((GET_DATA_TABLE_MAJOR_REVISION(table) == 2) && - (GET_DATA_TABLE_MINOR_REVISION(table) >= 2)) || - (GET_DATA_TABLE_MAJOR_REVISION(table) == 3)) { - ssEntry->speed_spectrum_rate /= 100; - } - - switch (ssInfo->ucSpreadSpectrumMode) { - case 0: - ssEntry->speed_spectrum_mode = - pp_atomctrl_spread_spectrum_mode_down; - break; - case 1: - ssEntry->speed_spectrum_mode = - pp_atomctrl_spread_spectrum_mode_center; - break; - default: - ssEntry->speed_spectrum_mode = - pp_atomctrl_spread_spectrum_mode_down; - break; - } - } - - return entry_found ? 0 : 1; -} - -/** - * Get the memory clock spread spectrum info - */ -int atomctrl_get_memory_clock_spread_spectrum( - struct pp_hwmgr *hwmgr, - const uint32_t memory_clock, - pp_atomctrl_internal_ss_info *ssInfo) -{ - return asic_internal_ss_get_ss_asignment(hwmgr, - ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); -} -/** - * Get the engine clock spread spectrum info - */ -int atomctrl_get_engine_clock_spread_spectrum( - struct pp_hwmgr *hwmgr, - const uint32_t engine_clock, - pp_atomctrl_internal_ss_info *ssInfo) -{ - return asic_internal_ss_get_ss_asignment(hwmgr, - ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo); -} - -int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, - uint16_t end_index, uint32_t mask, uint32_t *efuse) -{ - struct amdgpu_device *adev = hwmgr->adev; - int result; - READ_EFUSE_VALUE_PARAMETER efuse_param; - - efuse_param.sEfuse.usEfuseIndex = cpu_to_le16((start_index / 32) * 4); - efuse_param.sEfuse.ucBitShift = (uint8_t) - (start_index - ((start_index / 32) * 32)); - efuse_param.sEfuse.ucBitLength = (uint8_t) - ((end_index - start_index) + 1); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), - (uint32_t *)&efuse_param); - *efuse = result ? 0 : le32_to_cpu(efuse_param.ulEfuseValue) & mask; - - return result; -} - -int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, - uint8_t level) -{ - struct amdgpu_device *adev = hwmgr->adev; - DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters; - int result; - - memory_clock_parameters.asDPMMCReg.ulClock.ulClockFreq = - memory_clock & SET_CLOCK_FREQ_MASK; - memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag = - ADJUST_MC_SETTING_PARAM; - memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings), - (uint32_t *)&memory_clock_parameters); - - return result; -} - -int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage) -{ - struct amdgpu_device *adev = hwmgr->adev; - int result; - GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space; - - get_voltage_info_param_space.ucVoltageType = voltage_type; - get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; - get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id); - get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk); - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), - (uint32_t *)&get_voltage_info_param_space); - - *voltage = result ? 0 : - le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel); - - return result; -} - -int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table) -{ - - int i; - u8 frev, crev; - u16 size; - - ATOM_SMU_INFO_V2_1 *psmu_info = - (ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, SMU_Info), - &size, &frev, &crev); - - - for (i = 0; i < psmu_info->ucSclkEntryNum; i++) { - table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting; - table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv; - table->entry[i].usFcw_pcc = - le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc); - table->entry[i].usFcw_trans_upper = - le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper); - table->entry[i].usRcw_trans_lower = - le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower); - } - - return 0; -} - -int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, - struct pp_atom_ctrl__avfs_parameters *param) -{ - ATOM_ASIC_PROFILING_INFO_V3_6 *profile = NULL; - - if (param == NULL) - return -EINVAL; - - profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *) - smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo), - NULL, NULL, NULL); - if (!profile) - return -1; - - param->ulAVFS_meanNsigma_Acontant0 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant0); - param->ulAVFS_meanNsigma_Acontant1 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant1); - param->ulAVFS_meanNsigma_Acontant2 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant2); - param->usAVFS_meanNsigma_DC_tol_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_DC_tol_sigma); - param->usAVFS_meanNsigma_Platform_mean = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_mean); - param->usAVFS_meanNsigma_Platform_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_sigma); - param->ulGB_VDROOP_TABLE_CKSOFF_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a0); - param->ulGB_VDROOP_TABLE_CKSOFF_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a1); - param->ulGB_VDROOP_TABLE_CKSOFF_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a2); - param->ulGB_VDROOP_TABLE_CKSON_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a0); - param->ulGB_VDROOP_TABLE_CKSON_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a1); - param->ulGB_VDROOP_TABLE_CKSON_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a2); - param->ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1); - param->usAVFSGB_FUSE_TABLE_CKSOFF_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2); - param->ulAVFSGB_FUSE_TABLE_CKSOFF_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b); - param->ulAVFSGB_FUSE_TABLE_CKSON_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_m1); - param->usAVFSGB_FUSE_TABLE_CKSON_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSON_m2); - param->ulAVFSGB_FUSE_TABLE_CKSON_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_b); - param->usMaxVoltage_0_25mv = le16_to_cpu(profile->usMaxVoltage_0_25mv); - param->ucEnableGB_VDROOP_TABLE_CKSOFF = profile->ucEnableGB_VDROOP_TABLE_CKSOFF; - param->ucEnableGB_VDROOP_TABLE_CKSON = profile->ucEnableGB_VDROOP_TABLE_CKSON; - param->ucEnableGB_FUSE_TABLE_CKSOFF = profile->ucEnableGB_FUSE_TABLE_CKSOFF; - param->ucEnableGB_FUSE_TABLE_CKSON = profile->ucEnableGB_FUSE_TABLE_CKSON; - param->usPSM_Age_ComFactor = le16_to_cpu(profile->usPSM_Age_ComFactor); - param->ucEnableApplyAVFS_CKS_OFF_Voltage = profile->ucEnableApplyAVFS_CKS_OFF_Voltage; - - return 0; -} - -int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint8_t *svd_gpio_id, uint8_t *svc_gpio_id, - uint16_t *load_line) -{ - ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info = - (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev); - - const ATOM_VOLTAGE_OBJECT_V3 *voltage_object; - - PP_ASSERT_WITH_CODE((NULL != voltage_info), - "Could not find Voltage Table in BIOS.", return -EINVAL); - - voltage_object = atomctrl_lookup_voltage_type_v3 - (voltage_info, voltage_type, VOLTAGE_OBJ_SVID2); - - *svd_gpio_id = voltage_object->asSVID2Obj.ucSVDGpioId; - *svc_gpio_id = voltage_object->asSVID2Obj.ucSVCGpioId; - *load_line = voltage_object->asSVID2Obj.usLoadLine_PSI; - - return 0; -} - -int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id) -{ - struct amdgpu_device *adev = hwmgr->adev; - SET_VOLTAGE_PS_ALLOCATION allocation; - SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters = - (SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage; - int result; - - voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID; - - result = amdgpu_atom_execute_table(adev->mode_info.atom_context, - GetIndexIntoMasterTable(COMMAND, SetVoltage), - (uint32_t *)voltage_parameters); - - *virtual_voltage_id = voltage_parameters->usVoltageLevel; - - return result; -} - -int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, - uint16_t *vddc, uint16_t *vddci, - uint16_t virtual_voltage_id, - uint16_t efuse_voltage_id) -{ - int i, j; - int ix; - u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; - ATOM_ASIC_PROFILING_INFO_V2_1 *profile; - - *vddc = 0; - *vddci = 0; - - ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); - - profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) - smu_atom_get_data_table(hwmgr->adev, - ix, - NULL, NULL, NULL); - if (!profile) - return -EINVAL; - - if ((profile->asHeader.ucTableFormatRevision >= 2) && - (profile->asHeader.ucTableContentRevision >= 1) && - (profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) { - leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset); - vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset); - vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset); - if (profile->ucElbVDDC_Num > 0) { - for (i = 0; i < profile->ucElbVDDC_Num; i++) { - if (vddc_id_buf[i] == virtual_voltage_id) { - for (j = 0; j < profile->ucLeakageBinNum; j++) { - if (efuse_voltage_id <= leakage_bin[j]) { - *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; - break; - } - } - break; - } - } - } - - vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset); - vddci_buf = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset); - if (profile->ucElbVDDCI_Num > 0) { - for (i = 0; i < profile->ucElbVDDCI_Num; i++) { - if (vddci_id_buf[i] == virtual_voltage_id) { - for (j = 0; j < profile->ucLeakageBinNum; j++) { - if (efuse_voltage_id <= leakage_bin[j]) { - *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; - break; - } - } - break; - } - } - } - } - - return 0; -} - -void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, - uint32_t *min_vddc) -{ - void *profile; - - profile = smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo), - NULL, NULL, NULL); - - if (profile) { - switch (hwmgr->chip_id) { - case CHIP_TONGA: - case CHIP_FIJI: - *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMaxVddc) / 4; - *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMinVddc) / 4; - return; - case CHIP_POLARIS11: - case CHIP_POLARIS10: - case CHIP_POLARIS12: - *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMaxVddc) / 100; - *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMinVddc) / 100; - return; - default: - break; - } - } - *max_vddc = 0; - *min_vddc = 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h deleted file mode 100644 index 76ed2e413594..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef PP_ATOMVOLTAGECTRL_H -#define PP_ATOMVOLTAGECTRL_H - -#include "hwmgr.h" - -/* As returned from PowerConnectorDetectionTable. */ -#define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80 -#define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40 -#define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20 -#define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F - -/* New functions for Evergreen and beyond. */ -#define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32 - -struct pp_atomctrl_clock_dividers { - uint32_t pll_post_divider; - uint32_t pll_feedback_divider; - uint32_t pll_ref_divider; - bool enable_post_divider; -}; - -typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers; - -union pp_atomctrl_tcipll_fb_divider { - struct { - uint32_t ul_fb_div_frac : 14; - uint32_t ul_fb_div : 12; - uint32_t un_used : 6; - }; - uint32_t ul_fb_divider; -}; - -typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider; - -struct pp_atomctrl_clock_dividers_rv730 { - uint32_t pll_post_divider; - pp_atomctrl_tcipll_fb_divider mpll_feedback_divider; - uint32_t pll_ref_divider; - bool enable_post_divider; - bool enable_dithen; - uint32_t vco_mode; -}; -typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730; - - -struct pp_atomctrl_clock_dividers_kong { - uint32_t pll_post_divider; - uint32_t real_clock; -}; -typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong; - -struct pp_atomctrl_clock_dividers_ci { - uint32_t pll_post_divider; /* post divider value */ - uint32_t real_clock; - pp_atomctrl_tcipll_fb_divider ul_fb_div; /* Output Parameter: PLL FB divider */ - uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */ - uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */ - uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ -}; -typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci; - -struct pp_atomctrl_clock_dividers_vi { - uint32_t pll_post_divider; /* post divider value */ - uint32_t real_clock; - pp_atomctrl_tcipll_fb_divider ul_fb_div; /*Output Parameter: PLL FB divider */ - uint8_t uc_pll_ref_div; /*Output Parameter: PLL ref divider */ - uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */ - uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ -}; -typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi; - -struct pp_atomctrl_clock_dividers_ai { - u16 usSclk_fcw_frac; - u16 usSclk_fcw_int; - u8 ucSclkPostDiv; - u8 ucSclkVcoMode; - u8 ucSclkPllRange; - u8 ucSscEnable; - u16 usSsc_fcw1_frac; - u16 usSsc_fcw1_int; - u16 usReserved; - u16 usPcc_fcw_int; - u16 usSsc_fcw_slew_frac; - u16 usPcc_fcw_slew_frac; -}; -typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai; - - -union pp_atomctrl_s_mpll_fb_divider { - struct { - uint32_t cl_kf : 12; - uint32_t clk_frac : 12; - uint32_t un_used : 8; - }; - uint32_t ul_fb_divider; -}; -typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider; - -enum pp_atomctrl_spread_spectrum_mode { - pp_atomctrl_spread_spectrum_mode_down = 0, - pp_atomctrl_spread_spectrum_mode_center -}; -typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode; - -struct pp_atomctrl_memory_clock_param { - pp_atomctrl_s_mpll_fb_divider mpll_fb_divider; - uint32_t mpll_post_divider; - uint32_t bw_ctrl; - uint32_t dll_speed; - uint32_t vco_mode; - uint32_t yclk_sel; - uint32_t qdr; - uint32_t half_rate; -}; -typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param; - -struct pp_atomctrl_memory_clock_param_ai { - uint32_t ulClock; - uint32_t ulPostDiv; - uint16_t ulMclk_fcw_frac; - uint16_t ulMclk_fcw_int; -}; -typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai; - -struct pp_atomctrl_internal_ss_info { - uint32_t speed_spectrum_percentage; /* in 1/100 percentage */ - uint32_t speed_spectrum_rate; /* in KHz */ - pp_atomctrl_spread_spectrum_mode speed_spectrum_mode; -}; -typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info; - -#ifndef NUMBER_OF_M3ARB_PARAMS -#define NUMBER_OF_M3ARB_PARAMS 3 -#endif - -#ifndef NUMBER_OF_M3ARB_PARAM_SETS -#define NUMBER_OF_M3ARB_PARAM_SETS 10 -#endif - -struct pp_atomctrl_kong_system_info { - uint32_t ul_bootup_uma_clock; /* in 10kHz unit */ - uint16_t us_max_nb_voltage; /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ - uint16_t us_min_nb_voltage; /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ - uint16_t us_bootup_nb_voltage; /* boot up NB voltage */ - uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */ - uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */ - /* 0: default 1: uvd 2: fs-3d */ - uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */ -}; -typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info; - -struct pp_atomctrl_memory_info { - uint8_t memory_vendor; - uint8_t memory_type; -}; -typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info; - -#define MAX_AC_TIMING_ENTRIES 16 - -struct pp_atomctrl_memory_clock_range_table { - uint8_t num_entries; - uint8_t rsv[3]; - - uint32_t mclk[MAX_AC_TIMING_ENTRIES]; -}; -typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table; - -struct pp_atomctrl_voltage_table_entry { - uint16_t value; - uint32_t smio_low; -}; - -typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry; - -struct pp_atomctrl_voltage_table { - uint32_t count; - uint32_t mask_low; - uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */ - pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES]; -}; - -typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table; - -#define VBIOS_MC_REGISTER_ARRAY_SIZE 32 -#define VBIOS_MAX_AC_TIMING_ENTRIES 20 - -struct pp_atomctrl_mc_reg_entry { - uint32_t mclk_max; - uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; -}; -typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry; - -struct pp_atomctrl_mc_register_address { - uint16_t s1; - uint8_t uc_pre_reg_data; -}; - -typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address; - -#define MAX_SCLK_RANGE 8 - -struct pp_atom_ctrl_sclk_range_table_entry{ - uint8_t ucVco_setting; - uint8_t ucPostdiv; - uint16_t usFcw_pcc; - uint16_t usFcw_trans_upper; - uint16_t usRcw_trans_lower; -}; - - -struct pp_atom_ctrl_sclk_range_table{ - struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE]; -}; - -struct pp_atomctrl_mc_reg_table { - uint8_t last; /* number of registers */ - uint8_t num_entries; /* number of AC timing entries */ - pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; - pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; -}; -typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table; - -struct pp_atomctrl_gpio_pin_assignment { - uint16_t us_gpio_pin_aindex; - uint8_t uc_gpio_pin_bit_shift; -}; -typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment; - -struct pp_atom_ctrl__avfs_parameters { - uint32_t ulAVFS_meanNsigma_Acontant0; - uint32_t ulAVFS_meanNsigma_Acontant1; - uint32_t ulAVFS_meanNsigma_Acontant2; - uint16_t usAVFS_meanNsigma_DC_tol_sigma; - uint16_t usAVFS_meanNsigma_Platform_mean; - uint16_t usAVFS_meanNsigma_Platform_sigma; - uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0; - uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1; - uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2; - uint32_t ulGB_VDROOP_TABLE_CKSON_a0; - uint32_t ulGB_VDROOP_TABLE_CKSON_a1; - uint32_t ulGB_VDROOP_TABLE_CKSON_a2; - uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1; - uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2; - uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b; - uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1; - uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2; - uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b; - uint16_t usMaxVoltage_0_25mv; - uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF; - uint8_t ucEnableGB_VDROOP_TABLE_CKSON; - uint8_t ucEnableGB_FUSE_TABLE_CKSOFF; - uint8_t ucEnableGB_FUSE_TABLE_CKSON; - uint16_t usPSM_Age_ComFactor; - uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage; - uint8_t ucReserved; -}; - -extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); -extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); -extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage); -extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); -extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); -extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); -extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table); -extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); -extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr); -extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); -extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); -extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); -extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode); -extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table); -extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, - uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); -extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, - uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param); -extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, - uint32_t clock_value, - pp_atomctrl_clock_dividers_kong *dividers); -extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, - uint16_t end_index, uint32_t mask, uint32_t *efuse); -extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); -extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers); -extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, - uint8_t level); -extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); -extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); - -extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param); - -extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint8_t *svd_gpio_id, uint8_t *svc_gpio_id, - uint16_t *load_line); - -extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, - uint16_t *vddc, uint16_t *vddci, - uint16_t virtual_voltage_id, - uint16_t efuse_voltage_id); -extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id); - -extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, - uint32_t *min_vddc); -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c deleted file mode 100644 index 615cf2c09e54..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +++ /dev/null @@ -1,710 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "ppatomfwctrl.h" -#include "atomfirmware.h" -#include "atom.h" -#include "pp_debug.h" - -static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4( - const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table, - uint8_t voltage_type, uint8_t voltage_mode) -{ - unsigned int size = le16_to_cpu( - voltage_object_info_table->table_header.structuresize); - unsigned int offset = - offsetof(struct atom_voltage_objects_info_v4_1, voltage_object[0]); - unsigned long start = (unsigned long)voltage_object_info_table; - - while (offset < size) { - const union atom_voltage_object_v4 *voltage_object = - (const union atom_voltage_object_v4 *)(start + offset); - - if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type && - voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode) - return voltage_object; - - offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size); - - } - - return NULL; -} - -static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table( - struct pp_hwmgr *hwmgr) -{ - const void *table_address; - uint16_t idx; - - idx = GetIndexIntoMasterDataTable(voltageobject_info); - table_address = smu_atom_get_data_table(hwmgr->adev, - idx, NULL, NULL, NULL); - - PP_ASSERT_WITH_CODE(table_address, - "Error retrieving BIOS Table Address!", - return NULL); - - return (struct atom_voltage_objects_info_v4_1 *)table_address; -} - -/** -* Returns TRUE if the given voltage type is controlled by GPIO pins. -* voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC, SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ. -* voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE -*/ -bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr, - uint8_t voltage_type, uint8_t voltage_mode) -{ - struct atom_voltage_objects_info_v4_1 *voltage_info = - (struct atom_voltage_objects_info_v4_1 *) - pp_atomfwctrl_get_voltage_info_table(hwmgr); - bool ret; - - /* If we cannot find the table do NOT try to control this voltage. */ - PP_ASSERT_WITH_CODE(voltage_info, - "Could not find Voltage Table in BIOS.", - return false); - - ret = (pp_atomfwctrl_lookup_voltage_type_v4(voltage_info, - voltage_type, voltage_mode)) ? true : false; - - return ret; -} - -int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, - uint8_t voltage_type, uint8_t voltage_mode, - struct pp_atomfwctrl_voltage_table *voltage_table) -{ - struct atom_voltage_objects_info_v4_1 *voltage_info = - (struct atom_voltage_objects_info_v4_1 *) - pp_atomfwctrl_get_voltage_info_table(hwmgr); - const union atom_voltage_object_v4 *voltage_object; - unsigned int i; - int result = 0; - - PP_ASSERT_WITH_CODE(voltage_info, - "Could not find Voltage Table in BIOS.", - return -1); - - voltage_object = pp_atomfwctrl_lookup_voltage_type_v4(voltage_info, - voltage_type, voltage_mode); - - if (!voltage_object) - return -1; - - voltage_table->count = 0; - if (voltage_mode == VOLTAGE_OBJ_GPIO_LUT) { - PP_ASSERT_WITH_CODE( - (voltage_object->gpio_voltage_obj.gpio_entry_num <= - PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES), - "Too many voltage entries!", - result = -1); - - if (!result) { - for (i = 0; i < voltage_object->gpio_voltage_obj. - gpio_entry_num; i++) { - voltage_table->entries[i].value = - le16_to_cpu(voltage_object->gpio_voltage_obj. - voltage_gpio_lut[i].voltage_level_mv); - voltage_table->entries[i].smio_low = - le32_to_cpu(voltage_object->gpio_voltage_obj. - voltage_gpio_lut[i].voltage_gpio_reg_val); - } - voltage_table->count = - voltage_object->gpio_voltage_obj.gpio_entry_num; - voltage_table->mask_low = - le32_to_cpu( - voltage_object->gpio_voltage_obj.gpio_mask_val); - voltage_table->phase_delay = - voltage_object->gpio_voltage_obj.phase_delay_us; - } - } else if (voltage_mode == VOLTAGE_OBJ_SVID2) { - voltage_table->psi1_enable = - (voltage_object->svid2_voltage_obj.loadline_psi1 & 0x20) >> 5; - voltage_table->psi0_enable = - voltage_object->svid2_voltage_obj.psi0_enable & 0x1; - voltage_table->max_vid_step = - voltage_object->svid2_voltage_obj.maxvstep; - voltage_table->telemetry_offset = - voltage_object->svid2_voltage_obj.telemetry_offset; - voltage_table->telemetry_slope = - voltage_object->svid2_voltage_obj.telemetry_gain; - } else - PP_ASSERT_WITH_CODE(false, - "Unsupported Voltage Object Mode!", - result = -1); - - return result; -} - - -static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table( - struct pp_hwmgr *hwmgr) -{ - const void *table_address; - uint16_t idx; - - idx = GetIndexIntoMasterDataTable(gpio_pin_lut); - table_address = smu_atom_get_data_table(hwmgr->adev, - idx, NULL, NULL, NULL); - PP_ASSERT_WITH_CODE(table_address, - "Error retrieving BIOS Table Address!", - return NULL); - - return (struct atom_gpio_pin_lut_v2_1 *)table_address; -} - -static bool pp_atomfwctrl_lookup_gpio_pin( - struct atom_gpio_pin_lut_v2_1 *gpio_lookup_table, - const uint32_t pin_id, - struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment) -{ - unsigned int size = le16_to_cpu( - gpio_lookup_table->table_header.structuresize); - unsigned int offset = - offsetof(struct atom_gpio_pin_lut_v2_1, gpio_pin[0]); - unsigned long start = (unsigned long)gpio_lookup_table; - - while (offset < size) { - const struct atom_gpio_pin_assignment *pin_assignment = - (const struct atom_gpio_pin_assignment *)(start + offset); - - if (pin_id == pin_assignment->gpio_id) { - gpio_pin_assignment->uc_gpio_pin_bit_shift = - pin_assignment->gpio_bitshift; - gpio_pin_assignment->us_gpio_pin_aindex = - le16_to_cpu(pin_assignment->data_a_reg_index); - return true; - } - offset += offsetof(struct atom_gpio_pin_assignment, gpio_id) + 1; - } - return false; -} - -/** -* Returns TRUE if the given pin id find in lookup table. -*/ -bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, - const uint32_t pin_id, - struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment) -{ - bool ret = false; - struct atom_gpio_pin_lut_v2_1 *gpio_lookup_table = - pp_atomfwctrl_get_gpio_lookup_table(hwmgr); - - /* If we cannot find the table do NOT try to control this voltage. */ - PP_ASSERT_WITH_CODE(gpio_lookup_table, - "Could not find GPIO lookup Table in BIOS.", - return false); - - ret = pp_atomfwctrl_lookup_gpio_pin(gpio_lookup_table, - pin_id, gpio_pin_assignment); - - return ret; -} - -/** -* Enter to SelfRefresh mode. -* @param hwmgr -*/ -int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr) -{ - /* 0 - no action - * 1 - leave power to video memory always on - */ - return 0; -} - -/** pp_atomfwctrl_get_gpu_pll_dividers_vega10(). - * - * @param hwmgr input parameter: pointer to HwMgr - * @param clock_type input parameter: Clock type: 1 - GFXCLK, 2 - UCLK, 0 - All other clocks - * @param clock_value input parameter: Clock - * @param dividers output parameter:Clock dividers - */ -int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr, - uint32_t clock_type, uint32_t clock_value, - struct pp_atomfwctrl_clock_dividers_soc15 *dividers) -{ - struct amdgpu_device *adev = hwmgr->adev; - struct compute_gpu_clock_input_parameter_v1_8 pll_parameters; - struct compute_gpu_clock_output_parameter_v1_8 *pll_output; - uint32_t idx; - - pll_parameters.gpuclock_10khz = (uint32_t)clock_value; - pll_parameters.gpu_clock_type = clock_type; - - idx = GetIndexIntoMasterCmdTable(computegpuclockparam); - - if (amdgpu_atom_execute_table( - adev->mode_info.atom_context, idx, (uint32_t *)&pll_parameters)) - return -EINVAL; - - pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *) - &pll_parameters; - dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); - dividers->ulDid = le32_to_cpu(pll_output->dfs_did); - dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); - dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); - dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); - dividers->ucPll_ss_enable = pll_output->pll_ss_enable; - - return 0; -} - -int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_avfs_parameters *param) -{ - uint16_t idx; - uint8_t format_revision, content_revision; - - struct atom_asic_profiling_info_v4_1 *profile; - struct atom_asic_profiling_info_v4_2 *profile_v4_2; - - idx = GetIndexIntoMasterDataTable(asic_profiling_info); - profile = (struct atom_asic_profiling_info_v4_1 *) - smu_atom_get_data_table(hwmgr->adev, - idx, NULL, NULL, NULL); - - if (!profile) - return -1; - - format_revision = ((struct atom_common_table_header *)profile)->format_revision; - content_revision = ((struct atom_common_table_header *)profile)->content_revision; - - if (format_revision == 4 && content_revision == 1) { - param->ulMaxVddc = le32_to_cpu(profile->maxvddc); - param->ulMinVddc = le32_to_cpu(profile->minvddc); - param->ulMeanNsigmaAcontant0 = - le32_to_cpu(profile->avfs_meannsigma_acontant0); - param->ulMeanNsigmaAcontant1 = - le32_to_cpu(profile->avfs_meannsigma_acontant1); - param->ulMeanNsigmaAcontant2 = - le32_to_cpu(profile->avfs_meannsigma_acontant2); - param->usMeanNsigmaDcTolSigma = - le16_to_cpu(profile->avfs_meannsigma_dc_tol_sigma); - param->usMeanNsigmaPlatformMean = - le16_to_cpu(profile->avfs_meannsigma_platform_mean); - param->usMeanNsigmaPlatformSigma = - le16_to_cpu(profile->avfs_meannsigma_platform_sigma); - param->ulGbVdroopTableCksoffA0 = - le32_to_cpu(profile->gb_vdroop_table_cksoff_a0); - param->ulGbVdroopTableCksoffA1 = - le32_to_cpu(profile->gb_vdroop_table_cksoff_a1); - param->ulGbVdroopTableCksoffA2 = - le32_to_cpu(profile->gb_vdroop_table_cksoff_a2); - param->ulGbVdroopTableCksonA0 = - le32_to_cpu(profile->gb_vdroop_table_ckson_a0); - param->ulGbVdroopTableCksonA1 = - le32_to_cpu(profile->gb_vdroop_table_ckson_a1); - param->ulGbVdroopTableCksonA2 = - le32_to_cpu(profile->gb_vdroop_table_ckson_a2); - param->ulGbFuseTableCksoffM1 = - le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m1); - param->ulGbFuseTableCksoffM2 = - le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m2); - param->ulGbFuseTableCksoffB = - le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b); - param->ulGbFuseTableCksonM1 = - le32_to_cpu(profile->avfsgb_fuse_table_ckson_m1); - param->ulGbFuseTableCksonM2 = - le32_to_cpu(profile->avfsgb_fuse_table_ckson_m2); - param->ulGbFuseTableCksonB = - le32_to_cpu(profile->avfsgb_fuse_table_ckson_b); - - param->ucEnableGbVdroopTableCkson = - profile->enable_gb_vdroop_table_ckson; - param->ucEnableGbFuseTableCkson = - profile->enable_gb_fuse_table_ckson; - param->usPsmAgeComfactor = - le16_to_cpu(profile->psm_age_comfactor); - - param->ulDispclk2GfxclkM1 = - le32_to_cpu(profile->dispclk2gfxclk_a); - param->ulDispclk2GfxclkM2 = - le32_to_cpu(profile->dispclk2gfxclk_b); - param->ulDispclk2GfxclkB = - le32_to_cpu(profile->dispclk2gfxclk_c); - param->ulDcefclk2GfxclkM1 = - le32_to_cpu(profile->dcefclk2gfxclk_a); - param->ulDcefclk2GfxclkM2 = - le32_to_cpu(profile->dcefclk2gfxclk_b); - param->ulDcefclk2GfxclkB = - le32_to_cpu(profile->dcefclk2gfxclk_c); - param->ulPixelclk2GfxclkM1 = - le32_to_cpu(profile->pixclk2gfxclk_a); - param->ulPixelclk2GfxclkM2 = - le32_to_cpu(profile->pixclk2gfxclk_b); - param->ulPixelclk2GfxclkB = - le32_to_cpu(profile->pixclk2gfxclk_c); - param->ulPhyclk2GfxclkM1 = - le32_to_cpu(profile->phyclk2gfxclk_a); - param->ulPhyclk2GfxclkM2 = - le32_to_cpu(profile->phyclk2gfxclk_b); - param->ulPhyclk2GfxclkB = - le32_to_cpu(profile->phyclk2gfxclk_c); - param->ulAcgGbVdroopTableA0 = 0; - param->ulAcgGbVdroopTableA1 = 0; - param->ulAcgGbVdroopTableA2 = 0; - param->ulAcgGbFuseTableM1 = 0; - param->ulAcgGbFuseTableM2 = 0; - param->ulAcgGbFuseTableB = 0; - param->ucAcgEnableGbVdroopTable = 0; - param->ucAcgEnableGbFuseTable = 0; - } else if (format_revision == 4 && content_revision == 2) { - profile_v4_2 = (struct atom_asic_profiling_info_v4_2 *)profile; - param->ulMaxVddc = le32_to_cpu(profile_v4_2->maxvddc); - param->ulMinVddc = le32_to_cpu(profile_v4_2->minvddc); - param->ulMeanNsigmaAcontant0 = - le32_to_cpu(profile_v4_2->avfs_meannsigma_acontant0); - param->ulMeanNsigmaAcontant1 = - le32_to_cpu(profile_v4_2->avfs_meannsigma_acontant1); - param->ulMeanNsigmaAcontant2 = - le32_to_cpu(profile_v4_2->avfs_meannsigma_acontant2); - param->usMeanNsigmaDcTolSigma = - le16_to_cpu(profile_v4_2->avfs_meannsigma_dc_tol_sigma); - param->usMeanNsigmaPlatformMean = - le16_to_cpu(profile_v4_2->avfs_meannsigma_platform_mean); - param->usMeanNsigmaPlatformSigma = - le16_to_cpu(profile_v4_2->avfs_meannsigma_platform_sigma); - param->ulGbVdroopTableCksoffA0 = - le32_to_cpu(profile_v4_2->gb_vdroop_table_cksoff_a0); - param->ulGbVdroopTableCksoffA1 = - le32_to_cpu(profile_v4_2->gb_vdroop_table_cksoff_a1); - param->ulGbVdroopTableCksoffA2 = - le32_to_cpu(profile_v4_2->gb_vdroop_table_cksoff_a2); - param->ulGbVdroopTableCksonA0 = - le32_to_cpu(profile_v4_2->gb_vdroop_table_ckson_a0); - param->ulGbVdroopTableCksonA1 = - le32_to_cpu(profile_v4_2->gb_vdroop_table_ckson_a1); - param->ulGbVdroopTableCksonA2 = - le32_to_cpu(profile_v4_2->gb_vdroop_table_ckson_a2); - param->ulGbFuseTableCksoffM1 = - le32_to_cpu(profile_v4_2->avfsgb_fuse_table_cksoff_m1); - param->ulGbFuseTableCksoffM2 = - le32_to_cpu(profile_v4_2->avfsgb_fuse_table_cksoff_m2); - param->ulGbFuseTableCksoffB = - le32_to_cpu(profile_v4_2->avfsgb_fuse_table_cksoff_b); - param->ulGbFuseTableCksonM1 = - le32_to_cpu(profile_v4_2->avfsgb_fuse_table_ckson_m1); - param->ulGbFuseTableCksonM2 = - le32_to_cpu(profile_v4_2->avfsgb_fuse_table_ckson_m2); - param->ulGbFuseTableCksonB = - le32_to_cpu(profile_v4_2->avfsgb_fuse_table_ckson_b); - - param->ucEnableGbVdroopTableCkson = - profile_v4_2->enable_gb_vdroop_table_ckson; - param->ucEnableGbFuseTableCkson = - profile_v4_2->enable_gb_fuse_table_ckson; - param->usPsmAgeComfactor = - le16_to_cpu(profile_v4_2->psm_age_comfactor); - - param->ulDispclk2GfxclkM1 = - le32_to_cpu(profile_v4_2->dispclk2gfxclk_a); - param->ulDispclk2GfxclkM2 = - le32_to_cpu(profile_v4_2->dispclk2gfxclk_b); - param->ulDispclk2GfxclkB = - le32_to_cpu(profile_v4_2->dispclk2gfxclk_c); - param->ulDcefclk2GfxclkM1 = - le32_to_cpu(profile_v4_2->dcefclk2gfxclk_a); - param->ulDcefclk2GfxclkM2 = - le32_to_cpu(profile_v4_2->dcefclk2gfxclk_b); - param->ulDcefclk2GfxclkB = - le32_to_cpu(profile_v4_2->dcefclk2gfxclk_c); - param->ulPixelclk2GfxclkM1 = - le32_to_cpu(profile_v4_2->pixclk2gfxclk_a); - param->ulPixelclk2GfxclkM2 = - le32_to_cpu(profile_v4_2->pixclk2gfxclk_b); - param->ulPixelclk2GfxclkB = - le32_to_cpu(profile_v4_2->pixclk2gfxclk_c); - param->ulPhyclk2GfxclkM1 = - le32_to_cpu(profile->phyclk2gfxclk_a); - param->ulPhyclk2GfxclkM2 = - le32_to_cpu(profile_v4_2->phyclk2gfxclk_b); - param->ulPhyclk2GfxclkB = - le32_to_cpu(profile_v4_2->phyclk2gfxclk_c); - param->ulAcgGbVdroopTableA0 = le32_to_cpu(profile_v4_2->acg_gb_vdroop_table_a0); - param->ulAcgGbVdroopTableA1 = le32_to_cpu(profile_v4_2->acg_gb_vdroop_table_a1); - param->ulAcgGbVdroopTableA2 = le32_to_cpu(profile_v4_2->acg_gb_vdroop_table_a2); - param->ulAcgGbFuseTableM1 = le32_to_cpu(profile_v4_2->acg_avfsgb_fuse_table_m1); - param->ulAcgGbFuseTableM2 = le32_to_cpu(profile_v4_2->acg_avfsgb_fuse_table_m2); - param->ulAcgGbFuseTableB = le32_to_cpu(profile_v4_2->acg_avfsgb_fuse_table_b); - param->ucAcgEnableGbVdroopTable = le32_to_cpu(profile_v4_2->enable_acg_gb_vdroop_table); - param->ucAcgEnableGbFuseTable = le32_to_cpu(profile_v4_2->enable_acg_gb_fuse_table); - } else { - pr_info("Invalid VBIOS AVFS ProfilingInfo Revision!\n"); - return -EINVAL; - } - - return 0; -} - -int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_gpio_parameters *param) -{ - struct atom_smu_info_v3_1 *info; - uint16_t idx; - - idx = GetIndexIntoMasterDataTable(smu_info); - info = (struct atom_smu_info_v3_1 *) - smu_atom_get_data_table(hwmgr->adev, - idx, NULL, NULL, NULL); - - if (!info) { - pr_info("Error retrieving BIOS smu_info Table Address!"); - return -1; - } - - param->ucAcDcGpio = info->ac_dc_gpio_bit; - param->ucAcDcPolarity = info->ac_dc_polarity; - param->ucVR0HotGpio = info->vr0hot_gpio_bit; - param->ucVR0HotPolarity = info->vr0hot_polarity; - param->ucVR1HotGpio = info->vr1hot_gpio_bit; - param->ucVR1HotPolarity = info->vr1hot_polarity; - param->ucFwCtfGpio = info->fw_ctf_gpio_bit; - param->ucFwCtfPolarity = info->fw_ctf_polarity; - - return 0; -} - -int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, - uint8_t clk_id, uint8_t syspll_id, - uint32_t *frequency) -{ - struct amdgpu_device *adev = hwmgr->adev; - struct atom_get_smu_clock_info_parameters_v3_1 parameters; - struct atom_get_smu_clock_info_output_parameters_v3_1 *output; - uint32_t ix; - - parameters.clk_id = clk_id; - parameters.syspll_id = syspll_id; - parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; - parameters.dfsdid = 0; - - ix = GetIndexIntoMasterCmdTable(getsmuclockinfo); - - if (amdgpu_atom_execute_table( - adev->mode_info.atom_context, ix, (uint32_t *)¶meters)) - return -EINVAL; - - output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)¶meters; - *frequency = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; - - return 0; -} - -static void pp_atomfwctrl_copy_vbios_bootup_values_3_2(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_bios_boot_up_values *boot_values, - struct atom_firmware_info_v3_2 *fw_info) -{ - uint32_t frequency = 0; - - boot_values->ulRevision = fw_info->firmware_revision; - boot_values->ulGfxClk = fw_info->bootup_sclk_in10khz; - boot_values->ulUClk = fw_info->bootup_mclk_in10khz; - boot_values->usVddc = fw_info->bootup_vddc_mv; - boot_values->usVddci = fw_info->bootup_vddci_mv; - boot_values->usMvddc = fw_info->bootup_mvddc_mv; - boot_values->usVddGfx = fw_info->bootup_vddgfx_mv; - boot_values->ucCoolingID = fw_info->coolingsolution_id; - boot_values->ulSocClk = 0; - boot_values->ulDCEFClk = 0; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, SMU11_SYSPLL0_ID, &frequency)) - boot_values->ulSocClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCEFCLK_ID, SMU11_SYSPLL0_ID, &frequency)) - boot_values->ulDCEFClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_ECLK_ID, SMU11_SYSPLL0_ID, &frequency)) - boot_values->ulEClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_VCLK_ID, SMU11_SYSPLL0_ID, &frequency)) - boot_values->ulVClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCLK_ID, SMU11_SYSPLL0_ID, &frequency)) - boot_values->ulDClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL1_0_FCLK_ID, SMU11_SYSPLL1_2_ID, &frequency)) - boot_values->ulFClk = frequency; -} - -static void pp_atomfwctrl_copy_vbios_bootup_values_3_1(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_bios_boot_up_values *boot_values, - struct atom_firmware_info_v3_1 *fw_info) -{ - uint32_t frequency = 0; - - boot_values->ulRevision = fw_info->firmware_revision; - boot_values->ulGfxClk = fw_info->bootup_sclk_in10khz; - boot_values->ulUClk = fw_info->bootup_mclk_in10khz; - boot_values->usVddc = fw_info->bootup_vddc_mv; - boot_values->usVddci = fw_info->bootup_vddci_mv; - boot_values->usMvddc = fw_info->bootup_mvddc_mv; - boot_values->usVddGfx = fw_info->bootup_vddgfx_mv; - boot_values->ucCoolingID = fw_info->coolingsolution_id; - boot_values->ulSocClk = 0; - boot_values->ulDCEFClk = 0; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, 0, &frequency)) - boot_values->ulSocClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, 0, &frequency)) - boot_values->ulDCEFClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_ECLK_ID, 0, &frequency)) - boot_values->ulEClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_VCLK_ID, 0, &frequency)) - boot_values->ulVClk = frequency; - - if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCLK_ID, 0, &frequency)) - boot_values->ulDClk = frequency; -} - -int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_bios_boot_up_values *boot_values) -{ - struct atom_firmware_info_v3_2 *fwinfo_3_2; - struct atom_firmware_info_v3_1 *fwinfo_3_1; - struct atom_common_table_header *info = NULL; - uint16_t ix; - - ix = GetIndexIntoMasterDataTable(firmwareinfo); - info = (struct atom_common_table_header *) - smu_atom_get_data_table(hwmgr->adev, - ix, NULL, NULL, NULL); - - if (!info) { - pr_info("Error retrieving BIOS firmwareinfo!"); - return -EINVAL; - } - - if ((info->format_revision == 3) && (info->content_revision == 2)) { - fwinfo_3_2 = (struct atom_firmware_info_v3_2 *)info; - pp_atomfwctrl_copy_vbios_bootup_values_3_2(hwmgr, - boot_values, fwinfo_3_2); - } else if ((info->format_revision == 3) && (info->content_revision == 1)) { - fwinfo_3_1 = (struct atom_firmware_info_v3_1 *)info; - pp_atomfwctrl_copy_vbios_bootup_values_3_1(hwmgr, - boot_values, fwinfo_3_1); - } else { - pr_info("Fw info table revision does not match!"); - return -EINVAL; - } - - return 0; -} - -int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_smc_dpm_parameters *param) -{ - struct atom_smc_dpm_info_v4_1 *info; - uint16_t ix; - - ix = GetIndexIntoMasterDataTable(smc_dpm_info); - info = (struct atom_smc_dpm_info_v4_1 *) - smu_atom_get_data_table(hwmgr->adev, - ix, NULL, NULL, NULL); - if (!info) { - pr_info("Error retrieving BIOS Table Address!"); - return -EINVAL; - } - - param->liquid1_i2c_address = info->liquid1_i2c_address; - param->liquid2_i2c_address = info->liquid2_i2c_address; - param->vr_i2c_address = info->vr_i2c_address; - param->plx_i2c_address = info->plx_i2c_address; - - param->liquid_i2c_linescl = info->liquid_i2c_linescl; - param->liquid_i2c_linesda = info->liquid_i2c_linesda; - param->vr_i2c_linescl = info->vr_i2c_linescl; - param->vr_i2c_linesda = info->vr_i2c_linesda; - - param->plx_i2c_linescl = info->plx_i2c_linescl; - param->plx_i2c_linesda = info->plx_i2c_linesda; - param->vrsensorpresent = info->vrsensorpresent; - param->liquidsensorpresent = info->liquidsensorpresent; - - param->maxvoltagestepgfx = info->maxvoltagestepgfx; - param->maxvoltagestepsoc = info->maxvoltagestepsoc; - - param->vddgfxvrmapping = info->vddgfxvrmapping; - param->vddsocvrmapping = info->vddsocvrmapping; - param->vddmem0vrmapping = info->vddmem0vrmapping; - param->vddmem1vrmapping = info->vddmem1vrmapping; - - param->gfxulvphasesheddingmask = info->gfxulvphasesheddingmask; - param->soculvphasesheddingmask = info->soculvphasesheddingmask; - - param->gfxmaxcurrent = info->gfxmaxcurrent; - param->gfxoffset = info->gfxoffset; - param->padding_telemetrygfx = info->padding_telemetrygfx; - - param->socmaxcurrent = info->socmaxcurrent; - param->socoffset = info->socoffset; - param->padding_telemetrysoc = info->padding_telemetrysoc; - - param->mem0maxcurrent = info->mem0maxcurrent; - param->mem0offset = info->mem0offset; - param->padding_telemetrymem0 = info->padding_telemetrymem0; - - param->mem1maxcurrent = info->mem1maxcurrent; - param->mem1offset = info->mem1offset; - param->padding_telemetrymem1 = info->padding_telemetrymem1; - - param->acdcgpio = info->acdcgpio; - param->acdcpolarity = info->acdcpolarity; - param->vr0hotgpio = info->vr0hotgpio; - param->vr0hotpolarity = info->vr0hotpolarity; - - param->vr1hotgpio = info->vr1hotgpio; - param->vr1hotpolarity = info->vr1hotpolarity; - param->padding1 = info->padding1; - param->padding2 = info->padding2; - - param->ledpin0 = info->ledpin0; - param->ledpin1 = info->ledpin1; - param->ledpin2 = info->ledpin2; - - param->pllgfxclkspreadenabled = info->pllgfxclkspreadenabled; - param->pllgfxclkspreadpercent = info->pllgfxclkspreadpercent; - param->pllgfxclkspreadfreq = info->pllgfxclkspreadfreq; - - param->uclkspreadenabled = info->uclkspreadenabled; - param->uclkspreadpercent = info->uclkspreadpercent; - param->uclkspreadfreq = info->uclkspreadfreq; - - param->socclkspreadenabled = info->socclkspreadenabled; - param->socclkspreadpercent = info->socclkspreadpercent; - param->socclkspreadfreq = info->socclkspreadfreq; - - param->acggfxclkspreadenabled = info->acggfxclkspreadenabled; - param->acggfxclkspreadpercent = info->acggfxclkspreadpercent; - param->acggfxclkspreadfreq = info->acggfxclkspreadfreq; - - param->Vr2_I2C_address = info->Vr2_I2C_address; - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h deleted file mode 100644 index b7e2651b570b..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef PP_ATOMFWCTRL_H -#define PP_ATOMFWCTRL_H - -#include "hwmgr.h" - -typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID; - -#define GetIndexIntoMasterCmdTable(FieldName) \ - (((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t)) -#define GetIndexIntoMasterDataTable(FieldName) \ - (((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t)) - -#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32 - -struct pp_atomfwctrl_voltage_table_entry { - uint16_t value; - uint32_t smio_low; -}; - -struct pp_atomfwctrl_voltage_table { - uint32_t count; - uint32_t mask_low; - uint32_t phase_delay; - uint8_t psi0_enable; - uint8_t psi1_enable; - uint8_t max_vid_step; - uint8_t telemetry_offset; - uint8_t telemetry_slope; - struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES]; -}; - -struct pp_atomfwctrl_gpio_pin_assignment { - uint16_t us_gpio_pin_aindex; - uint8_t uc_gpio_pin_bit_shift; -}; - -struct pp_atomfwctrl_clock_dividers_soc15 { - uint32_t ulClock; /* the actual clock */ - uint32_t ulDid; /* DFS divider */ - uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */ - uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */ - uint16_t usPll_ss_slew_frac; - uint8_t ucPll_ss_enable; - uint8_t ucReserve; - uint32_t ulReserve[2]; -}; - -struct pp_atomfwctrl_avfs_parameters { - uint32_t ulMaxVddc; - uint32_t ulMinVddc; - - uint32_t ulMeanNsigmaAcontant0; - uint32_t ulMeanNsigmaAcontant1; - uint32_t ulMeanNsigmaAcontant2; - uint16_t usMeanNsigmaDcTolSigma; - uint16_t usMeanNsigmaPlatformMean; - uint16_t usMeanNsigmaPlatformSigma; - uint32_t ulGbVdroopTableCksoffA0; - uint32_t ulGbVdroopTableCksoffA1; - uint32_t ulGbVdroopTableCksoffA2; - uint32_t ulGbVdroopTableCksonA0; - uint32_t ulGbVdroopTableCksonA1; - uint32_t ulGbVdroopTableCksonA2; - - uint32_t ulGbFuseTableCksoffM1; - uint32_t ulGbFuseTableCksoffM2; - uint32_t ulGbFuseTableCksoffB; - - uint32_t ulGbFuseTableCksonM1; - uint32_t ulGbFuseTableCksonM2; - uint32_t ulGbFuseTableCksonB; - - uint8_t ucEnableGbVdroopTableCkson; - uint8_t ucEnableGbFuseTableCkson; - uint16_t usPsmAgeComfactor; - - uint32_t ulDispclk2GfxclkM1; - uint32_t ulDispclk2GfxclkM2; - uint32_t ulDispclk2GfxclkB; - uint32_t ulDcefclk2GfxclkM1; - uint32_t ulDcefclk2GfxclkM2; - uint32_t ulDcefclk2GfxclkB; - uint32_t ulPixelclk2GfxclkM1; - uint32_t ulPixelclk2GfxclkM2; - uint32_t ulPixelclk2GfxclkB; - uint32_t ulPhyclk2GfxclkM1; - uint32_t ulPhyclk2GfxclkM2; - uint32_t ulPhyclk2GfxclkB; - uint32_t ulAcgGbVdroopTableA0; - uint32_t ulAcgGbVdroopTableA1; - uint32_t ulAcgGbVdroopTableA2; - uint32_t ulAcgGbFuseTableM1; - uint32_t ulAcgGbFuseTableM2; - uint32_t ulAcgGbFuseTableB; - uint32_t ucAcgEnableGbVdroopTable; - uint32_t ucAcgEnableGbFuseTable; -}; - -struct pp_atomfwctrl_gpio_parameters { - uint8_t ucAcDcGpio; - uint8_t ucAcDcPolarity; - uint8_t ucVR0HotGpio; - uint8_t ucVR0HotPolarity; - uint8_t ucVR1HotGpio; - uint8_t ucVR1HotPolarity; - uint8_t ucFwCtfGpio; - uint8_t ucFwCtfPolarity; -}; - -struct pp_atomfwctrl_bios_boot_up_values { - uint32_t ulRevision; - uint32_t ulGfxClk; - uint32_t ulUClk; - uint32_t ulSocClk; - uint32_t ulDCEFClk; - uint32_t ulEClk; - uint32_t ulVClk; - uint32_t ulDClk; - uint32_t ulFClk; - uint16_t usVddc; - uint16_t usVddci; - uint16_t usMvddc; - uint16_t usVddGfx; - uint8_t ucCoolingID; -}; - -struct pp_atomfwctrl_smc_dpm_parameters -{ - uint8_t liquid1_i2c_address; - uint8_t liquid2_i2c_address; - uint8_t vr_i2c_address; - uint8_t plx_i2c_address; - uint8_t liquid_i2c_linescl; - uint8_t liquid_i2c_linesda; - uint8_t vr_i2c_linescl; - uint8_t vr_i2c_linesda; - uint8_t plx_i2c_linescl; - uint8_t plx_i2c_linesda; - uint8_t vrsensorpresent; - uint8_t liquidsensorpresent; - uint16_t maxvoltagestepgfx; - uint16_t maxvoltagestepsoc; - uint8_t vddgfxvrmapping; - uint8_t vddsocvrmapping; - uint8_t vddmem0vrmapping; - uint8_t vddmem1vrmapping; - uint8_t gfxulvphasesheddingmask; - uint8_t soculvphasesheddingmask; - - uint16_t gfxmaxcurrent; - uint8_t gfxoffset; - uint8_t padding_telemetrygfx; - uint16_t socmaxcurrent; - uint8_t socoffset; - uint8_t padding_telemetrysoc; - uint16_t mem0maxcurrent; - uint8_t mem0offset; - uint8_t padding_telemetrymem0; - uint16_t mem1maxcurrent; - uint8_t mem1offset; - uint8_t padding_telemetrymem1; - - uint8_t acdcgpio; - uint8_t acdcpolarity; - uint8_t vr0hotgpio; - uint8_t vr0hotpolarity; - uint8_t vr1hotgpio; - uint8_t vr1hotpolarity; - uint8_t padding1; - uint8_t padding2; - - uint8_t ledpin0; - uint8_t ledpin1; - uint8_t ledpin2; - - uint8_t pllgfxclkspreadenabled; - uint8_t pllgfxclkspreadpercent; - uint16_t pllgfxclkspreadfreq; - - uint8_t uclkspreadenabled; - uint8_t uclkspreadpercent; - uint16_t uclkspreadfreq; - - uint8_t socclkspreadenabled; - uint8_t socclkspreadpercent; - uint16_t socclkspreadfreq; - - uint8_t acggfxclkspreadenabled; - uint8_t acggfxclkspreadpercent; - uint16_t acggfxclkspreadfreq; - - uint8_t Vr2_I2C_address; -}; - -int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr, - uint32_t clock_type, uint32_t clock_value, - struct pp_atomfwctrl_clock_dividers_soc15 *dividers); -int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr); -bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id, - struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment); - -int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table); -bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr, - uint8_t voltage_type, uint8_t voltage_mode); - -int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_avfs_parameters *param); -int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_gpio_parameters *param); - -int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_bios_boot_up_values *boot_values); -int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_smc_dpm_parameters *param); -int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, - uint8_t clk_id, uint8_t syspll_id, - uint32_t *frequency); - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h deleted file mode 100644 index 8f50a038396c..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h +++ /dev/null @@ -1,555 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include <asm/div64.h> - -#define SHIFT_AMOUNT 16 /* We multiply all original integers with 2^SHIFT_AMOUNT to get the fInt representation */ - -#define PRECISION 5 /* Change this value to change the number of decimal places in the final output - 5 is a good default */ - -#define SHIFTED_2 (2 << SHIFT_AMOUNT) -#define MAX (1 << (SHIFT_AMOUNT - 1)) - 1 /* 32767 - Might change in the future */ - -/* ------------------------------------------------------------------------------- - * NEW TYPE - fINT - * ------------------------------------------------------------------------------- - * A variable of type fInt can be accessed in 3 ways using the dot (.) operator - * fInt A; - * A.full => The full number as it is. Generally not easy to read - * A.partial.real => Only the integer portion - * A.partial.decimal => Only the fractional portion - */ -typedef union _fInt { - int full; - struct _partial { - unsigned int decimal: SHIFT_AMOUNT; /*Needs to always be unsigned*/ - int real: 32 - SHIFT_AMOUNT; - } partial; -} fInt; - -/* ------------------------------------------------------------------------------- - * Function Declarations - * ------------------------------------------------------------------------------- - */ -static fInt ConvertToFraction(int); /* Use this to convert an INT to a FINT */ -static fInt Convert_ULONG_ToFraction(uint32_t); /* Use this to convert an uint32_t to a FINT */ -static fInt GetScaledFraction(int, int); /* Use this to convert an INT to a FINT after scaling it by a factor */ -static int ConvertBackToInteger(fInt); /* Convert a FINT back to an INT that is scaled by 1000 (i.e. last 3 digits are the decimal digits) */ - -static fInt fNegate(fInt); /* Returns -1 * input fInt value */ -static fInt fAdd (fInt, fInt); /* Returns the sum of two fInt numbers */ -static fInt fSubtract (fInt A, fInt B); /* Returns A-B - Sometimes easier than Adding negative numbers */ -static fInt fMultiply (fInt, fInt); /* Returns the product of two fInt numbers */ -static fInt fDivide (fInt A, fInt B); /* Returns A/B */ -static fInt fGetSquare(fInt); /* Returns the square of a fInt number */ -static fInt fSqrt(fInt); /* Returns the Square Root of a fInt number */ - -static int uAbs(int); /* Returns the Absolute value of the Int */ -static int uPow(int base, int exponent); /* Returns base^exponent an INT */ - -static void SolveQuadracticEqn(fInt, fInt, fInt, fInt[]); /* Returns the 2 roots via the array */ -static bool Equal(fInt, fInt); /* Returns true if two fInts are equal to each other */ -static bool GreaterThan(fInt A, fInt B); /* Returns true if A > B */ - -static fInt fExponential(fInt exponent); /* Can be used to calculate e^exponent */ -static fInt fNaturalLog(fInt value); /* Can be used to calculate ln(value) */ - -/* Fuse decoding functions - * ------------------------------------------------------------------------------------- - */ -static fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength); -static fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength); -static fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength); - -/* Internal Support Functions - Use these ONLY for testing or adding to internal functions - * ------------------------------------------------------------------------------------- - * Some of the following functions take two INTs as their input - This is unsafe for a variety of reasons. - */ -static fInt Divide (int, int); /* Divide two INTs and return result as FINT */ -static fInt fNegate(fInt); - -static int uGetScaledDecimal (fInt); /* Internal function */ -static int GetReal (fInt A); /* Internal function */ - -/* ------------------------------------------------------------------------------------- - * TROUBLESHOOTING INFORMATION - * ------------------------------------------------------------------------------------- - * 1) ConvertToFraction - InputOutOfRangeException: Only accepts numbers smaller than MAX (default: 32767) - * 2) fAdd - OutputOutOfRangeException: Output bigger than MAX (default: 32767) - * 3) fMultiply - OutputOutOfRangeException: - * 4) fGetSquare - OutputOutOfRangeException: - * 5) fDivide - DivideByZeroException - * 6) fSqrt - NegativeSquareRootException: Input cannot be a negative number - */ - -/* ------------------------------------------------------------------------------------- - * START OF CODE - * ------------------------------------------------------------------------------------- - */ -static fInt fExponential(fInt exponent) /*Can be used to calculate e^exponent*/ -{ - uint32_t i; - bool bNegated = false; - - fInt fPositiveOne = ConvertToFraction(1); - fInt fZERO = ConvertToFraction(0); - - fInt lower_bound = Divide(78, 10000); - fInt solution = fPositiveOne; /*Starting off with baseline of 1 */ - fInt error_term; - - static const uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; - static const uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; - - if (GreaterThan(fZERO, exponent)) { - exponent = fNegate(exponent); - bNegated = true; - } - - while (GreaterThan(exponent, lower_bound)) { - for (i = 0; i < 11; i++) { - if (GreaterThan(exponent, GetScaledFraction(k_array[i], 10000))) { - exponent = fSubtract(exponent, GetScaledFraction(k_array[i], 10000)); - solution = fMultiply(solution, GetScaledFraction(expk_array[i], 10000)); - } - } - } - - error_term = fAdd(fPositiveOne, exponent); - - solution = fMultiply(solution, error_term); - - if (bNegated) - solution = fDivide(fPositiveOne, solution); - - return solution; -} - -static fInt fNaturalLog(fInt value) -{ - uint32_t i; - fInt upper_bound = Divide(8, 1000); - fInt fNegativeOne = ConvertToFraction(-1); - fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */ - fInt error_term; - - static const uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; - static const uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; - - while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) { - for (i = 0; i < 10; i++) { - if (GreaterThan(value, GetScaledFraction(k_array[i], 10000))) { - value = fDivide(value, GetScaledFraction(k_array[i], 10000)); - solution = fAdd(solution, GetScaledFraction(logk_array[i], 10000)); - } - } - } - - error_term = fAdd(fNegativeOne, value); - - return (fAdd(solution, error_term)); -} - -static fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength) -{ - fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value); - fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1); - - fInt f_decoded_value; - - f_decoded_value = fDivide(f_fuse_value, f_bit_max_value); - f_decoded_value = fMultiply(f_decoded_value, f_range); - f_decoded_value = fAdd(f_decoded_value, f_min); - - return f_decoded_value; -} - - -static fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength) -{ - fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value); - fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1); - - fInt f_CONSTANT_NEG13 = ConvertToFraction(-13); - fInt f_CONSTANT1 = ConvertToFraction(1); - - fInt f_decoded_value; - - f_decoded_value = fSubtract(fDivide(f_bit_max_value, f_fuse_value), f_CONSTANT1); - f_decoded_value = fNaturalLog(f_decoded_value); - f_decoded_value = fMultiply(f_decoded_value, fDivide(f_range, f_CONSTANT_NEG13)); - f_decoded_value = fAdd(f_decoded_value, f_average); - - return f_decoded_value; -} - -static fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength) -{ - fInt fLeakage; - fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1); - - fLeakage = fMultiply(ln_max_div_min, Convert_ULONG_ToFraction(leakageID_fuse)); - fLeakage = fDivide(fLeakage, f_bit_max_value); - fLeakage = fExponential(fLeakage); - fLeakage = fMultiply(fLeakage, f_min); - - return fLeakage; -} - -static fInt ConvertToFraction(int X) /*Add all range checking here. Is it possible to make fInt a private declaration? */ -{ - fInt temp; - - if (X <= MAX) - temp.full = (X << SHIFT_AMOUNT); - else - temp.full = 0; - - return temp; -} - -static fInt fNegate(fInt X) -{ - fInt CONSTANT_NEGONE = ConvertToFraction(-1); - return (fMultiply(X, CONSTANT_NEGONE)); -} - -static fInt Convert_ULONG_ToFraction(uint32_t X) -{ - fInt temp; - - if (X <= MAX) - temp.full = (X << SHIFT_AMOUNT); - else - temp.full = 0; - - return temp; -} - -static fInt GetScaledFraction(int X, int factor) -{ - int times_shifted, factor_shifted; - bool bNEGATED; - fInt fValue; - - times_shifted = 0; - factor_shifted = 0; - bNEGATED = false; - - if (X < 0) { - X = -1*X; - bNEGATED = true; - } - - if (factor < 0) { - factor = -1*factor; - bNEGATED = !bNEGATED; /*If bNEGATED = true due to X < 0, this will cover the case of negative cancelling negative */ - } - - if ((X > MAX) || factor > MAX) { - if ((X/factor) <= MAX) { - while (X > MAX) { - X = X >> 1; - times_shifted++; - } - - while (factor > MAX) { - factor = factor >> 1; - factor_shifted++; - } - } else { - fValue.full = 0; - return fValue; - } - } - - if (factor == 1) - return ConvertToFraction(X); - - fValue = fDivide(ConvertToFraction(X * uPow(-1, bNEGATED)), ConvertToFraction(factor)); - - fValue.full = fValue.full << times_shifted; - fValue.full = fValue.full >> factor_shifted; - - return fValue; -} - -/* Addition using two fInts */ -static fInt fAdd (fInt X, fInt Y) -{ - fInt Sum; - - Sum.full = X.full + Y.full; - - return Sum; -} - -/* Addition using two fInts */ -static fInt fSubtract (fInt X, fInt Y) -{ - fInt Difference; - - Difference.full = X.full - Y.full; - - return Difference; -} - -static bool Equal(fInt A, fInt B) -{ - if (A.full == B.full) - return true; - else - return false; -} - -static bool GreaterThan(fInt A, fInt B) -{ - if (A.full > B.full) - return true; - else - return false; -} - -static fInt fMultiply (fInt X, fInt Y) /* Uses 64-bit integers (int64_t) */ -{ - fInt Product; - int64_t tempProduct; - bool X_LessThanOne, Y_LessThanOne; - - X_LessThanOne = (X.partial.real == 0 && X.partial.decimal != 0 && X.full >= 0); - Y_LessThanOne = (Y.partial.real == 0 && Y.partial.decimal != 0 && Y.full >= 0); - - /*The following is for a very specific common case: Non-zero number with ONLY fractional portion*/ - /* TEMPORARILY DISABLED - CAN BE USED TO IMPROVE PRECISION - - if (X_LessThanOne && Y_LessThanOne) { - Product.full = X.full * Y.full; - return Product - }*/ - - tempProduct = ((int64_t)X.full) * ((int64_t)Y.full); /*Q(16,16)*Q(16,16) = Q(32, 32) - Might become a negative number! */ - tempProduct = tempProduct >> 16; /*Remove lagging 16 bits - Will lose some precision from decimal; */ - Product.full = (int)tempProduct; /*The int64_t will lose the leading 16 bits that were part of the integer portion */ - - return Product; -} - -static fInt fDivide (fInt X, fInt Y) -{ - fInt fZERO, fQuotient; - int64_t longlongX, longlongY; - - fZERO = ConvertToFraction(0); - - if (Equal(Y, fZERO)) - return fZERO; - - longlongX = (int64_t)X.full; - longlongY = (int64_t)Y.full; - - longlongX = longlongX << 16; /*Q(16,16) -> Q(32,32) */ - - div64_s64(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */ - - fQuotient.full = (int)longlongX; - return fQuotient; -} - -static int ConvertBackToInteger (fInt A) /*THIS is the function that will be used to check with the Golden settings table*/ -{ - fInt fullNumber, scaledDecimal, scaledReal; - - scaledReal.full = GetReal(A) * uPow(10, PRECISION-1); /* DOUBLE CHECK THISSSS!!! */ - - scaledDecimal.full = uGetScaledDecimal(A); - - fullNumber = fAdd(scaledDecimal,scaledReal); - - return fullNumber.full; -} - -static fInt fGetSquare(fInt A) -{ - return fMultiply(A,A); -} - -/* x_new = x_old - (x_old^2 - C) / (2 * x_old) */ -static fInt fSqrt(fInt num) -{ - fInt F_divide_Fprime, Fprime; - fInt test; - fInt twoShifted; - int seed, counter, error; - fInt x_new, x_old, C, y; - - fInt fZERO = ConvertToFraction(0); - - /* (0 > num) is the same as (num < 0), i.e., num is negative */ - - if (GreaterThan(fZERO, num) || Equal(fZERO, num)) - return fZERO; - - C = num; - - if (num.partial.real > 3000) - seed = 60; - else if (num.partial.real > 1000) - seed = 30; - else if (num.partial.real > 100) - seed = 10; - else - seed = 2; - - counter = 0; - - if (Equal(num, fZERO)) /*Square Root of Zero is zero */ - return fZERO; - - twoShifted = ConvertToFraction(2); - x_new = ConvertToFraction(seed); - - do { - counter++; - - x_old.full = x_new.full; - - test = fGetSquare(x_old); /*1.75*1.75 is reverting back to 1 when shifted down */ - y = fSubtract(test, C); /*y = f(x) = x^2 - C; */ - - Fprime = fMultiply(twoShifted, x_old); - F_divide_Fprime = fDivide(y, Fprime); - - x_new = fSubtract(x_old, F_divide_Fprime); - - error = ConvertBackToInteger(x_new) - ConvertBackToInteger(x_old); - - if (counter > 20) /*20 is already way too many iterations. If we dont have an answer by then, we never will*/ - return x_new; - - } while (uAbs(error) > 0); - - return (x_new); -} - -static void SolveQuadracticEqn(fInt A, fInt B, fInt C, fInt Roots[]) -{ - fInt *pRoots = &Roots[0]; - fInt temp, root_first, root_second; - fInt f_CONSTANT10, f_CONSTANT100; - - f_CONSTANT100 = ConvertToFraction(100); - f_CONSTANT10 = ConvertToFraction(10); - - while(GreaterThan(A, f_CONSTANT100) || GreaterThan(B, f_CONSTANT100) || GreaterThan(C, f_CONSTANT100)) { - A = fDivide(A, f_CONSTANT10); - B = fDivide(B, f_CONSTANT10); - C = fDivide(C, f_CONSTANT10); - } - - temp = fMultiply(ConvertToFraction(4), A); /* root = 4*A */ - temp = fMultiply(temp, C); /* root = 4*A*C */ - temp = fSubtract(fGetSquare(B), temp); /* root = b^2 - 4AC */ - temp = fSqrt(temp); /*root = Sqrt (b^2 - 4AC); */ - - root_first = fSubtract(fNegate(B), temp); /* b - Sqrt(b^2 - 4AC) */ - root_second = fAdd(fNegate(B), temp); /* b + Sqrt(b^2 - 4AC) */ - - root_first = fDivide(root_first, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */ - root_first = fDivide(root_first, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */ - - root_second = fDivide(root_second, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */ - root_second = fDivide(root_second, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */ - - *(pRoots + 0) = root_first; - *(pRoots + 1) = root_second; -} - -/* ----------------------------------------------------------------------------- - * SUPPORT FUNCTIONS - * ----------------------------------------------------------------------------- - */ - -/* Conversion Functions */ -static int GetReal (fInt A) -{ - return (A.full >> SHIFT_AMOUNT); -} - -static fInt Divide (int X, int Y) -{ - fInt A, B, Quotient; - - A.full = X << SHIFT_AMOUNT; - B.full = Y << SHIFT_AMOUNT; - - Quotient = fDivide(A, B); - - return Quotient; -} - -static int uGetScaledDecimal (fInt A) /*Converts the fractional portion to whole integers - Costly function */ -{ - int dec[PRECISION]; - int i, scaledDecimal = 0, tmp = A.partial.decimal; - - for (i = 0; i < PRECISION; i++) { - dec[i] = tmp / (1 << SHIFT_AMOUNT); - tmp = tmp - ((1 << SHIFT_AMOUNT)*dec[i]); - tmp *= 10; - scaledDecimal = scaledDecimal + dec[i]*uPow(10, PRECISION - 1 -i); - } - - return scaledDecimal; -} - -static int uPow(int base, int power) -{ - if (power == 0) - return 1; - else - return (base)*uPow(base, power - 1); -} - -static int uAbs(int X) -{ - if (X < 0) - return (X * -1); - else - return X; -} - -static fInt fRoundUpByStepSize(fInt A, fInt fStepSize, bool error_term) -{ - fInt solution; - - solution = fDivide(A, fStepSize); - solution.partial.decimal = 0; /*All fractional digits changes to 0 */ - - if (error_term) - solution.partial.real += 1; /*Error term of 1 added */ - - solution = fMultiply(solution, fStepSize); - solution = fAdd(solution, fStepSize); - - return solution; -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c deleted file mode 100644 index 186496a34cbe..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include <linux/types.h> -#include "atom-types.h" -#include "atombios.h" -#include "pppcielanes.h" - -/** \file - * Functions related to PCIe lane changes. - */ - -/* For converting from number of lanes to lane bits. */ -static const unsigned char pp_r600_encode_lanes[] = { - 0, /* 0 Not Supported */ - 1, /* 1 Lane */ - 2, /* 2 Lanes */ - 0, /* 3 Not Supported */ - 3, /* 4 Lanes */ - 0, /* 5 Not Supported */ - 0, /* 6 Not Supported */ - 0, /* 7 Not Supported */ - 4, /* 8 Lanes */ - 0, /* 9 Not Supported */ - 0, /* 10 Not Supported */ - 0, /* 11 Not Supported */ - 5, /* 12 Lanes (Not actually supported) */ - 0, /* 13 Not Supported */ - 0, /* 14 Not Supported */ - 0, /* 15 Not Supported */ - 6 /* 16 Lanes */ -}; - -static const unsigned char pp_r600_decoded_lanes[8] = { 16, 1, 2, 4, 8, 12, 16, }; - -uint8_t encode_pcie_lane_width(uint32_t num_lanes) -{ - return pp_r600_encode_lanes[num_lanes]; -} - -uint8_t decode_pcie_lane_width(uint32_t num_lanes) -{ - return pp_r600_decoded_lanes[num_lanes]; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h deleted file mode 100644 index 70b163b35570..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef PP_PCIELANES_H -#define PP_PCIELANES_H - -extern uint8_t encode_pcie_lane_width(uint32_t num_lanes); -extern uint8_t decode_pcie_lane_width(uint32_t num_lanes); - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h deleted file mode 100644 index 1e870f58dd12..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef TONGA_PPTABLE_H -#define TONGA_PPTABLE_H - -/** \file - * This is a PowerPlay table header file - */ -#pragma pack(push, 1) - -#include "hwmgr.h" - -#define ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f -#define ATOM_TONGA_PP_FANPARAMETERS_NOFAN 0x80 /* No fan is connected to this controller. */ - -#define ATOM_TONGA_PP_THERMALCONTROLLER_NONE 0 -#define ATOM_TONGA_PP_THERMALCONTROLLER_LM96163 17 -#define ATOM_TONGA_PP_THERMALCONTROLLER_TONGA 21 -#define ATOM_TONGA_PP_THERMALCONTROLLER_FIJI 22 - -/* - * Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. - * We probably should reserve the bit 0x80 for this use. - * To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). - * The driver can pick the correct internal controller based on the ASIC. - */ - -#define ATOM_TONGA_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 /* ADT7473 Fan Control + Internal Thermal Controller */ -#define ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D /* EMC2103 Fan Control + Internal Thermal Controller */ - -/*/* ATOM_TONGA_POWERPLAYTABLE::ulPlatformCaps */ -#define ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL 0x1 /* This cap indicates whether vddgfx will be a separated power rail. */ -#define ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY 0x2 /* This cap indicates whether this is a mobile part and CCC need to show Powerplay page. */ -#define ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x4 /* This cap indicates whether power source notificaiton is done by SBIOS directly. */ -#define ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND 0x8 /* Enable the option to overwrite voltage island feature to be disabled, regardless of VddGfx power rail support. */ -#define ____RETIRE16____ 0x10 -#define ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC 0x20 /* This cap indicates whether power source notificaiton is done by GPIO directly. */ -#define ____RETIRE64____ 0x40 -#define ____RETIRE128____ 0x80 -#define ____RETIRE256____ 0x100 -#define ____RETIRE512____ 0x200 -#define ____RETIRE1024____ 0x400 -#define ____RETIRE2048____ 0x800 -#define ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL 0x1000 /* This cap indicates dynamic MVDD is required. Uncheck to disable it. */ -#define ____RETIRE2000____ 0x2000 -#define ____RETIRE4000____ 0x4000 -#define ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 /* This cap indicates dynamic VDDCI is required. Uncheck to disable it. */ -#define ____RETIRE10000____ 0x10000 -#define ATOM_TONGA_PP_PLATFORM_CAP_BACO 0x20000 /* Enable to indicate the driver supports BACO state. */ - -#define ATOM_TONGA_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x100000 /* Enable to indicate the driver supports thermal2GPIO17. */ -#define ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x1000000 /* Enable to indicate if thermal and PCC are sharing the same GPIO */ -#define ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x2000000 - -/* ATOM_PPLIB_NONCLOCK_INFO::usClassification */ -#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 -#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 -#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 -#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 -#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 -#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 -/* 2, 4, 6, 7 are reserved */ - -#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 -#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 -#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 -#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 -#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 -#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 - -/* ATOM_PPLIB_NONCLOCK_INFO::usClassification2 */ -#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 - -#define ATOM_Tonga_DISALLOW_ON_DC 0x00004000 -#define ATOM_Tonga_ENABLE_VARIBRIGHT 0x00008000 - -#define ATOM_Tonga_TABLE_REVISION_TONGA 7 - -typedef struct _ATOM_Tonga_POWERPLAYTABLE { - ATOM_COMMON_TABLE_HEADER sHeader; - - UCHAR ucTableRevision; - USHORT usTableSize; /*the size of header structure */ - - ULONG ulGoldenPPID; - ULONG ulGoldenRevision; - USHORT usFormatID; - - USHORT usVoltageTime; /*in microseconds */ - ULONG ulPlatformCaps; /*See ATOM_Tonga_CAPS_* */ - - ULONG ulMaxODEngineClock; /*For Overdrive. */ - ULONG ulMaxODMemoryClock; /*For Overdrive. */ - - USHORT usPowerControlLimit; - USHORT usUlvVoltageOffset; /*in mv units */ - - USHORT usStateArrayOffset; /*points to ATOM_Tonga_State_Array */ - USHORT usFanTableOffset; /*points to ATOM_Tonga_Fan_Table */ - USHORT usThermalControllerOffset; /*points to ATOM_Tonga_Thermal_Controller */ - USHORT usReserv; /*CustomThermalPolicy removed for Tonga. Keep this filed as reserved. */ - - USHORT usMclkDependencyTableOffset; /*points to ATOM_Tonga_MCLK_Dependency_Table */ - USHORT usSclkDependencyTableOffset; /*points to ATOM_Tonga_SCLK_Dependency_Table */ - USHORT usVddcLookupTableOffset; /*points to ATOM_Tonga_Voltage_Lookup_Table */ - USHORT usVddgfxLookupTableOffset; /*points to ATOM_Tonga_Voltage_Lookup_Table */ - - USHORT usMMDependencyTableOffset; /*points to ATOM_Tonga_MM_Dependency_Table */ - - USHORT usVCEStateTableOffset; /*points to ATOM_Tonga_VCE_State_Table; */ - - USHORT usPPMTableOffset; /*points to ATOM_Tonga_PPM_Table */ - USHORT usPowerTuneTableOffset; /*points to ATOM_PowerTune_Table */ - - USHORT usHardLimitTableOffset; /*points to ATOM_Tonga_Hard_Limit_Table */ - - USHORT usPCIETableOffset; /*points to ATOM_Tonga_PCIE_Table */ - - USHORT usGPIOTableOffset; /*points to ATOM_Tonga_GPIO_Table */ - - USHORT usReserved[6]; /*TODO: modify reserved size to fit structure aligning */ -} ATOM_Tonga_POWERPLAYTABLE; - -typedef struct _ATOM_Tonga_State { - UCHAR ucEngineClockIndexHigh; - UCHAR ucEngineClockIndexLow; - - UCHAR ucMemoryClockIndexHigh; - UCHAR ucMemoryClockIndexLow; - - UCHAR ucPCIEGenLow; - UCHAR ucPCIEGenHigh; - - UCHAR ucPCIELaneLow; - UCHAR ucPCIELaneHigh; - - USHORT usClassification; - ULONG ulCapsAndSettings; - USHORT usClassification2; - UCHAR ucUnused[4]; -} ATOM_Tonga_State; - -typedef struct _ATOM_Tonga_State_Array { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_State entries[1]; /* Dynamically allocate entries. */ -} ATOM_Tonga_State_Array; - -typedef struct _ATOM_Tonga_MCLK_Dependency_Record { - UCHAR ucVddcInd; /* Vddc voltage */ - USHORT usVddci; - USHORT usVddgfxOffset; /* Offset relative to Vddc voltage */ - USHORT usMvdd; - ULONG ulMclk; - USHORT usReserved; -} ATOM_Tonga_MCLK_Dependency_Record; - -typedef struct _ATOM_Tonga_MCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_MCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Tonga_MCLK_Dependency_Table; - -typedef struct _ATOM_Tonga_SCLK_Dependency_Record { - UCHAR ucVddInd; /* Base voltage */ - USHORT usVddcOffset; /* Offset relative to base voltage */ - ULONG ulSclk; - USHORT usEdcCurrent; - UCHAR ucReliabilityTemperature; - UCHAR ucCKSVOffsetandDisable; /* Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level. */ -} ATOM_Tonga_SCLK_Dependency_Record; - -typedef struct _ATOM_Tonga_SCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Tonga_SCLK_Dependency_Table; - -typedef struct _ATOM_Polaris_SCLK_Dependency_Record { - UCHAR ucVddInd; /* Base voltage */ - USHORT usVddcOffset; /* Offset relative to base voltage */ - ULONG ulSclk; - USHORT usEdcCurrent; - UCHAR ucReliabilityTemperature; - UCHAR ucCKSVOffsetandDisable; /* Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level. */ - ULONG ulSclkOffset; -} ATOM_Polaris_SCLK_Dependency_Record; - -typedef struct _ATOM_Polaris_SCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Polaris_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Polaris_SCLK_Dependency_Table; - -typedef struct _ATOM_Tonga_PCIE_Record { - UCHAR ucPCIEGenSpeed; - UCHAR usPCIELaneWidth; - UCHAR ucReserved[2]; -} ATOM_Tonga_PCIE_Record; - -typedef struct _ATOM_Tonga_PCIE_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_PCIE_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Tonga_PCIE_Table; - -typedef struct _ATOM_Polaris10_PCIE_Record { - UCHAR ucPCIEGenSpeed; - UCHAR usPCIELaneWidth; - UCHAR ucReserved[2]; - ULONG ulPCIE_Sclk; -} ATOM_Polaris10_PCIE_Record; - -typedef struct _ATOM_Polaris10_PCIE_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Polaris10_PCIE_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Polaris10_PCIE_Table; - - -typedef struct _ATOM_Tonga_MM_Dependency_Record { - UCHAR ucVddcInd; /* VDDC voltage */ - USHORT usVddgfxOffset; /* Offset relative to VDDC voltage */ - ULONG ulDClk; /* UVD D-clock */ - ULONG ulVClk; /* UVD V-clock */ - ULONG ulEClk; /* VCE clock */ - ULONG ulAClk; /* ACP clock */ - ULONG ulSAMUClk; /* SAMU clock */ -} ATOM_Tonga_MM_Dependency_Record; - -typedef struct _ATOM_Tonga_MM_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_MM_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Tonga_MM_Dependency_Table; - -typedef struct _ATOM_Tonga_Voltage_Lookup_Record { - USHORT usVdd; /* Base voltage */ - USHORT usCACLow; - USHORT usCACMid; - USHORT usCACHigh; -} ATOM_Tonga_Voltage_Lookup_Record; - -typedef struct _ATOM_Tonga_Voltage_Lookup_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_Voltage_Lookup_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Tonga_Voltage_Lookup_Table; - -typedef struct _ATOM_Tonga_Fan_Table { - UCHAR ucRevId; /* Change this if the table format changes or version changes so that the other fields are not the same. */ - UCHAR ucTHyst; /* Temperature hysteresis. Integer. */ - USHORT usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ - USHORT usTMed; /* The middle temperature where we change slopes. */ - USHORT usTHigh; /* The high point above TMed for adjusting the second slope. */ - USHORT usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ - USHORT usPWMMed; /* The PWM value (in percent) at TMed. */ - USHORT usPWMHigh; /* The PWM value at THigh. */ - USHORT usTMax; /* The max temperature */ - UCHAR ucFanControlMode; /* Legacy or Fuzzy Fan mode */ - USHORT usFanPWMMax; /* Maximum allowed fan power in percent */ - USHORT usFanOutputSensitivity; /* Sensitivity of fan reaction to temepature changes */ - USHORT usFanRPMMax; /* The default value in RPM */ - ULONG ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ - UCHAR ucTargetTemperature; /* Advanced fan controller target temperature. */ - UCHAR ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ - USHORT usReserved; -} ATOM_Tonga_Fan_Table; - -typedef struct _ATOM_Fiji_Fan_Table { - UCHAR ucRevId; /* Change this if the table format changes or version changes so that the other fields are not the same. */ - UCHAR ucTHyst; /* Temperature hysteresis. Integer. */ - USHORT usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ - USHORT usTMed; /* The middle temperature where we change slopes. */ - USHORT usTHigh; /* The high point above TMed for adjusting the second slope. */ - USHORT usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ - USHORT usPWMMed; /* The PWM value (in percent) at TMed. */ - USHORT usPWMHigh; /* The PWM value at THigh. */ - USHORT usTMax; /* The max temperature */ - UCHAR ucFanControlMode; /* Legacy or Fuzzy Fan mode */ - USHORT usFanPWMMax; /* Maximum allowed fan power in percent */ - USHORT usFanOutputSensitivity; /* Sensitivity of fan reaction to temepature changes */ - USHORT usFanRPMMax; /* The default value in RPM */ - ULONG ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ - UCHAR ucTargetTemperature; /* Advanced fan controller target temperature. */ - UCHAR ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ - USHORT usFanGainEdge; - USHORT usFanGainHotspot; - USHORT usFanGainLiquid; - USHORT usFanGainVrVddc; - USHORT usFanGainVrMvdd; - USHORT usFanGainPlx; - USHORT usFanGainHbm; - USHORT usReserved; -} ATOM_Fiji_Fan_Table; - -typedef struct _ATOM_Tonga_Thermal_Controller { - UCHAR ucRevId; - UCHAR ucType; /* one of ATOM_TONGA_PP_THERMALCONTROLLER_* */ - UCHAR ucI2cLine; /* as interpreted by DAL I2C */ - UCHAR ucI2cAddress; - UCHAR ucFanParameters; /* Fan Control Parameters. */ - UCHAR ucFanMinRPM; /* Fan Minimum RPM (hundreds) -- for display purposes only. */ - UCHAR ucFanMaxRPM; /* Fan Maximum RPM (hundreds) -- for display purposes only. */ - UCHAR ucReserved; - UCHAR ucFlags; /* to be defined */ -} ATOM_Tonga_Thermal_Controller; - -typedef struct _ATOM_Tonga_VCE_State_Record { - UCHAR ucVCEClockIndex; /*index into usVCEDependencyTableOffset of 'ATOM_Tonga_MM_Dependency_Table' type */ - UCHAR ucFlag; /* 2 bits indicates memory p-states */ - UCHAR ucSCLKIndex; /*index into ATOM_Tonga_SCLK_Dependency_Table */ - UCHAR ucMCLKIndex; /*index into ATOM_Tonga_MCLK_Dependency_Table */ -} ATOM_Tonga_VCE_State_Record; - -typedef struct _ATOM_Tonga_VCE_State_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; - ATOM_Tonga_VCE_State_Record entries[1]; -} ATOM_Tonga_VCE_State_Table; - -typedef struct _ATOM_Tonga_PowerTune_Table { - UCHAR ucRevId; - USHORT usTDP; - USHORT usConfigurableTDP; - USHORT usTDC; - USHORT usBatteryPowerLimit; - USHORT usSmallPowerLimit; - USHORT usLowCACLeakage; - USHORT usHighCACLeakage; - USHORT usMaximumPowerDeliveryLimit; - USHORT usTjMax; - USHORT usPowerTuneDataSetID; - USHORT usEDCLimit; - USHORT usSoftwareShutdownTemp; - USHORT usClockStretchAmount; - USHORT usReserve[2]; -} ATOM_Tonga_PowerTune_Table; - -typedef struct _ATOM_Fiji_PowerTune_Table { - UCHAR ucRevId; - USHORT usTDP; - USHORT usConfigurableTDP; - USHORT usTDC; - USHORT usBatteryPowerLimit; - USHORT usSmallPowerLimit; - USHORT usLowCACLeakage; - USHORT usHighCACLeakage; - USHORT usMaximumPowerDeliveryLimit; - USHORT usTjMax; /* For Fiji, this is also usTemperatureLimitEdge; */ - USHORT usPowerTuneDataSetID; - USHORT usEDCLimit; - USHORT usSoftwareShutdownTemp; - USHORT usClockStretchAmount; - USHORT usTemperatureLimitHotspot; /*The following are added for Fiji */ - USHORT usTemperatureLimitLiquid1; - USHORT usTemperatureLimitLiquid2; - USHORT usTemperatureLimitVrVddc; - USHORT usTemperatureLimitVrMvdd; - USHORT usTemperatureLimitPlx; - UCHAR ucLiquid1_I2C_address; /*Liquid */ - UCHAR ucLiquid2_I2C_address; - UCHAR ucLiquid_I2C_Line; - UCHAR ucVr_I2C_address; /*VR */ - UCHAR ucVr_I2C_Line; - UCHAR ucPlx_I2C_address; /*PLX */ - UCHAR ucPlx_I2C_Line; - USHORT usReserved; -} ATOM_Fiji_PowerTune_Table; - -#define ATOM_PPM_A_A 1 -#define ATOM_PPM_A_I 2 -typedef struct _ATOM_Tonga_PPM_Table { - UCHAR ucRevId; - UCHAR ucPpmDesign; /*A+I or A+A */ - USHORT usCpuCoreNumber; - ULONG ulPlatformTDP; - ULONG ulSmallACPlatformTDP; - ULONG ulPlatformTDC; - ULONG ulSmallACPlatformTDC; - ULONG ulApuTDP; - ULONG ulDGpuTDP; - ULONG ulDGpuUlvPower; - ULONG ulTjmax; -} ATOM_Tonga_PPM_Table; - -typedef struct _ATOM_Tonga_Hard_Limit_Record { - ULONG ulSCLKLimit; - ULONG ulMCLKLimit; - USHORT usVddcLimit; - USHORT usVddciLimit; - USHORT usVddgfxLimit; -} ATOM_Tonga_Hard_Limit_Record; - -typedef struct _ATOM_Tonga_Hard_Limit_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; - ATOM_Tonga_Hard_Limit_Record entries[1]; -} ATOM_Tonga_Hard_Limit_Table; - -typedef struct _ATOM_Tonga_GPIO_Table { - UCHAR ucRevId; - UCHAR ucVRHotTriggeredSclkDpmIndex; /* If VRHot signal is triggered SCLK will be limited to this DPM level */ - UCHAR ucReserve[5]; -} ATOM_Tonga_GPIO_Table; - -typedef struct _PPTable_Generic_SubTable_Header { - UCHAR ucRevId; -} PPTable_Generic_SubTable_Header; - - -#pragma pack(pop) - - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c deleted file mode 100644 index b760f95e7fa7..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +++ /dev/null @@ -1,1337 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include <linux/module.h> -#include <linux/slab.h> - -#include "process_pptables_v1_0.h" -#include "ppatomctrl.h" -#include "atombios.h" -#include "hwmgr.h" -#include "cgs_common.h" -#include "pptable_v1_0.h" - -/** - * Private Function used during initialization. - * @param hwmgr Pointer to the hardware manager. - * @param setIt A flag indication if the capability should be set (TRUE) or reset (FALSE). - * @param cap Which capability to set/reset. - */ -static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap) -{ - if (setIt) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); - else - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); -} - - -/** - * Private Function used during initialization. - * @param hwmgr Pointer to the hardware manager. - * @param powerplay_caps the bit array (from BIOS) of capability bits. - * @exception the current implementation always returns 1. - */ -static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) -{ - PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____), - "ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!", continue); - PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____), - "ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!", continue); - PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____), - "ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!", continue); - PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____), - "ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!", continue); - PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____), - "ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!", continue); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY), - PHM_PlatformCaps_PowerPlaySupport - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), - PHM_PlatformCaps_BiosPowerSourceControl - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC), - PHM_PlatformCaps_AutomaticDCTransition - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL), - PHM_PlatformCaps_EnableMVDDControl - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL), - PHM_PlatformCaps_ControlVDDCI - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL), - PHM_PlatformCaps_ControlVDDGFX - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_BACO), - PHM_PlatformCaps_BACO - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND), - PHM_PlatformCaps_DisableVoltageIsland - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL), - PHM_PlatformCaps_CombinePCCWithThermalSignal - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE), - PHM_PlatformCaps_LoadPostProductionFirmware - ); - - return 0; -} - -/** - * Private Function to get the PowerPlay Table Address. - */ -static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) -{ - int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - - u16 size; - u8 frev, crev; - void *table_address = (void *)hwmgr->soft_pp_table; - - if (!table_address) { - table_address = (ATOM_Tonga_POWERPLAYTABLE *) - smu_atom_get_data_table(hwmgr->adev, - index, &size, &frev, &crev); - hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ - hwmgr->soft_pp_table_size = size; - } - - return table_address; -} - -static int get_vddc_lookup_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table **lookup_table, - const ATOM_Tonga_Voltage_Lookup_Table *vddc_lookup_pp_tables, - uint32_t max_levels - ) -{ - uint32_t table_size, i; - phm_ppt_v1_voltage_lookup_table *table; - phm_ppt_v1_voltage_lookup_record *record; - ATOM_Tonga_Voltage_Lookup_Record *atom_record; - - PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries), - "Invalid CAC Leakage PowerPlay Table!", return 1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels; - - table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == table) - return -ENOMEM; - - table->count = vddc_lookup_pp_tables->ucNumEntries; - - for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) { - record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_voltage_lookup_record, - entries, table, i); - atom_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_Voltage_Lookup_Record, - entries, vddc_lookup_pp_tables, i); - record->us_calculated = 0; - record->us_vdd = le16_to_cpu(atom_record->usVdd); - record->us_cac_low = le16_to_cpu(atom_record->usCACLow); - record->us_cac_mid = le16_to_cpu(atom_record->usCACMid); - record->us_cac_high = le16_to_cpu(atom_record->usCACHigh); - } - - *lookup_table = table; - - return 0; -} - -/** - * Private Function used during initialization. - * Initialize Platform Power Management Parameter table - * @param hwmgr Pointer to the hardware manager. - * @param atom_ppm_table Pointer to PPM table in VBIOS - */ -static int get_platform_power_management_table( - struct pp_hwmgr *hwmgr, - ATOM_Tonga_PPM_Table *atom_ppm_table) -{ - struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_Tonga_PPM_Table), GFP_KERNEL); - struct phm_ppt_v1_information *pp_table_information = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - if (NULL == ptr) - return -ENOMEM; - - ptr->ppm_design - = atom_ppm_table->ucPpmDesign; - ptr->cpu_core_number - = le16_to_cpu(atom_ppm_table->usCpuCoreNumber); - ptr->platform_tdp - = le32_to_cpu(atom_ppm_table->ulPlatformTDP); - ptr->small_ac_platform_tdp - = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDP); - ptr->platform_tdc - = le32_to_cpu(atom_ppm_table->ulPlatformTDC); - ptr->small_ac_platform_tdc - = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDC); - ptr->apu_tdp - = le32_to_cpu(atom_ppm_table->ulApuTDP); - ptr->dgpu_tdp - = le32_to_cpu(atom_ppm_table->ulDGpuTDP); - ptr->dgpu_ulv_power - = le32_to_cpu(atom_ppm_table->ulDGpuUlvPower); - ptr->tj_max - = le32_to_cpu(atom_ppm_table->ulTjmax); - - pp_table_information->ppm_parameter_table = ptr; - - return 0; -} - -/** - * Private Function used during initialization. - * Initialize TDP limits for DPM2 - * @param hwmgr Pointer to the hardware manager. - * @param powerplay_table Pointer to the PowerPlay Table. - */ -static int init_dpm_2_parameters( - struct pp_hwmgr *hwmgr, - const ATOM_Tonga_POWERPLAYTABLE *powerplay_table - ) -{ - int result = 0; - struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); - ATOM_Tonga_PPM_Table *atom_ppm_table; - uint32_t disable_ppm = 0; - uint32_t disable_power_control = 0; - - pp_table_information->us_ulv_voltage_offset = - le16_to_cpu(powerplay_table->usUlvVoltageOffset); - - pp_table_information->ppm_parameter_table = NULL; - pp_table_information->vddc_lookup_table = NULL; - pp_table_information->vddgfx_lookup_table = NULL; - /* TDP limits */ - hwmgr->platform_descriptor.TDPODLimit = - le16_to_cpu(powerplay_table->usPowerControlLimit); - hwmgr->platform_descriptor.TDPAdjustment = 0; - hwmgr->platform_descriptor.VidAdjustment = 0; - hwmgr->platform_descriptor.VidAdjustmentPolarity = 0; - hwmgr->platform_descriptor.VidMinLimit = 0; - hwmgr->platform_descriptor.VidMaxLimit = 1500000; - hwmgr->platform_descriptor.VidStep = 6250; - - disable_power_control = 0; - if (0 == disable_power_control) { - /* enable TDP overdrive (PowerControl) feature as well if supported */ - if (hwmgr->platform_descriptor.TDPODLimit != 0) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerControl); - } - - if (0 != powerplay_table->usVddcLookupTableOffset) { - const ATOM_Tonga_Voltage_Lookup_Table *pVddcCACTable = - (ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usVddcLookupTableOffset)); - - result = get_vddc_lookup_table(hwmgr, - &pp_table_information->vddc_lookup_table, pVddcCACTable, 16); - } - - if (0 != powerplay_table->usVddgfxLookupTableOffset) { - const ATOM_Tonga_Voltage_Lookup_Table *pVddgfxCACTable = - (ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usVddgfxLookupTableOffset)); - - result = get_vddc_lookup_table(hwmgr, - &pp_table_information->vddgfx_lookup_table, pVddgfxCACTable, 16); - } - - disable_ppm = 0; - if (0 == disable_ppm) { - atom_ppm_table = (ATOM_Tonga_PPM_Table *) - (((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset)); - - if (0 != powerplay_table->usPPMTableOffset) { - if (get_platform_power_management_table(hwmgr, atom_ppm_table) == 0) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnablePlatformPowerManagement); - } - } - } - - return result; -} - -static int get_valid_clk( - struct pp_hwmgr *hwmgr, - struct phm_clock_array **clk_table, - phm_ppt_v1_clock_voltage_dependency_table const *clk_volt_pp_table - ) -{ - uint32_t table_size, i; - struct phm_clock_array *table; - phm_ppt_v1_clock_voltage_dependency_record *dep_record; - - PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(uint32_t) * clk_volt_pp_table->count; - - table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == table) - return -ENOMEM; - - table->count = (uint32_t)clk_volt_pp_table->count; - - for (i = 0; i < table->count; i++) { - dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_clock_voltage_dependency_record, - entries, clk_volt_pp_table, i); - table->values[i] = (uint32_t)dep_record->clk; - } - *clk_table = table; - - return 0; -} - -static int get_hard_limits( - struct pp_hwmgr *hwmgr, - struct phm_clock_and_voltage_limits *limits, - ATOM_Tonga_Hard_Limit_Table const *limitable - ) -{ - PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1); - - /* currently we always take entries[0] parameters */ - limits->sclk = le32_to_cpu(limitable->entries[0].ulSCLKLimit); - limits->mclk = le32_to_cpu(limitable->entries[0].ulMCLKLimit); - limits->vddc = le16_to_cpu(limitable->entries[0].usVddcLimit); - limits->vddci = le16_to_cpu(limitable->entries[0].usVddciLimit); - limits->vddgfx = le16_to_cpu(limitable->entries[0].usVddgfxLimit); - - return 0; -} - -static int get_mclk_voltage_dependency_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_mclk_dep_table, - ATOM_Tonga_MCLK_Dependency_Table const *mclk_dep_table - ) -{ - uint32_t table_size, i; - phm_ppt_v1_clock_voltage_dependency_table *mclk_table; - phm_ppt_v1_clock_voltage_dependency_record *mclk_table_record; - ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record; - - PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record) - * mclk_dep_table->ucNumEntries; - - mclk_table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == mclk_table) - return -ENOMEM; - - mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; - - for (i = 0; i < mclk_dep_table->ucNumEntries; i++) { - mclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_clock_voltage_dependency_record, - entries, mclk_table, i); - mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_MCLK_Dependency_Record, - entries, mclk_dep_table, i); - mclk_table_record->vddInd = mclk_dep_record->ucVddcInd; - mclk_table_record->vdd_offset = le16_to_cpu(mclk_dep_record->usVddgfxOffset); - mclk_table_record->vddci = le16_to_cpu(mclk_dep_record->usVddci); - mclk_table_record->mvdd = le16_to_cpu(mclk_dep_record->usMvdd); - mclk_table_record->clk = le32_to_cpu(mclk_dep_record->ulMclk); - } - - *pp_tonga_mclk_dep_table = mclk_table; - - return 0; -} - -static int get_sclk_voltage_dependency_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table, - PPTable_Generic_SubTable_Header const *sclk_dep_table - ) -{ - uint32_t table_size, i; - phm_ppt_v1_clock_voltage_dependency_table *sclk_table; - phm_ppt_v1_clock_voltage_dependency_record *sclk_table_record; - - if (sclk_dep_table->ucRevId < 1) { - const ATOM_Tonga_SCLK_Dependency_Table *tonga_table = - (ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table; - ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record; - - PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record) - * tonga_table->ucNumEntries; - - sclk_table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == sclk_table) - return -ENOMEM; - - sclk_table->count = (uint32_t)tonga_table->ucNumEntries; - - for (i = 0; i < tonga_table->ucNumEntries; i++) { - sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_SCLK_Dependency_Record, - entries, tonga_table, i); - sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_clock_voltage_dependency_record, - entries, sclk_table, i); - sclk_table_record->vddInd = sclk_dep_record->ucVddInd; - sclk_table_record->vdd_offset = le16_to_cpu(sclk_dep_record->usVddcOffset); - sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk); - sclk_table_record->cks_enable = - (((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0; - sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F); - } - } else { - const ATOM_Polaris_SCLK_Dependency_Table *polaris_table = - (ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table; - ATOM_Polaris_SCLK_Dependency_Record *sclk_dep_record; - - PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record) - * polaris_table->ucNumEntries; - - sclk_table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == sclk_table) - return -ENOMEM; - - sclk_table->count = (uint32_t)polaris_table->ucNumEntries; - - for (i = 0; i < polaris_table->ucNumEntries; i++) { - sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Polaris_SCLK_Dependency_Record, - entries, polaris_table, i); - sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_clock_voltage_dependency_record, - entries, sclk_table, i); - sclk_table_record->vddInd = sclk_dep_record->ucVddInd; - sclk_table_record->vdd_offset = le16_to_cpu(sclk_dep_record->usVddcOffset); - sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk); - sclk_table_record->cks_enable = - (((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0; - sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F); - sclk_table_record->sclk_offset = le32_to_cpu(sclk_dep_record->ulSclkOffset); - } - } - *pp_tonga_sclk_dep_table = sclk_table; - - return 0; -} - -static int get_pcie_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_pcie_table **pp_tonga_pcie_table, - PPTable_Generic_SubTable_Header const *ptable - ) -{ - uint32_t table_size, i, pcie_count; - phm_ppt_v1_pcie_table *pcie_table; - struct phm_ppt_v1_information *pp_table_information = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - phm_ppt_v1_pcie_record *pcie_record; - - if (ptable->ucRevId < 1) { - const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)ptable; - ATOM_Tonga_PCIE_Record *atom_pcie_record; - - PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries; - - pcie_table = kzalloc(table_size, GFP_KERNEL); - - if (pcie_table == NULL) - return -ENOMEM; - - /* - * Make sure the number of pcie entries are less than or equal to sclk dpm levels. - * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1. - */ - pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1; - if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) - pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; - else - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); - - pcie_table->count = pcie_count; - for (i = 0; i < pcie_count; i++) { - pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_pcie_record, - entries, pcie_table, i); - atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_PCIE_Record, - entries, atom_pcie_table, i); - pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; - pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); - } - - *pp_tonga_pcie_table = pcie_table; - } else { - /* Polaris10/Polaris11 and newer. */ - const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)ptable; - ATOM_Polaris10_PCIE_Record *atom_pcie_record; - - PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries; - - pcie_table = kzalloc(table_size, GFP_KERNEL); - - if (pcie_table == NULL) - return -ENOMEM; - - /* - * Make sure the number of pcie entries are less than or equal to sclk dpm levels. - * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1. - */ - pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1; - if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) - pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; - else - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); - - pcie_table->count = pcie_count; - - for (i = 0; i < pcie_count; i++) { - pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_pcie_record, - entries, pcie_table, i); - atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Polaris10_PCIE_Record, - entries, atom_pcie_table, i); - pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; - pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); - pcie_record->pcie_sclk = le32_to_cpu(atom_pcie_record->ulPCIE_Sclk); - } - - *pp_tonga_pcie_table = pcie_table; - } - - return 0; -} - -static int get_cac_tdp_table( - struct pp_hwmgr *hwmgr, - struct phm_cac_tdp_table **cac_tdp_table, - const PPTable_Generic_SubTable_Header * table - ) -{ - uint32_t table_size; - struct phm_cac_tdp_table *tdp_table; - - table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table); - tdp_table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == tdp_table) - return -ENOMEM; - - hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == hwmgr->dyn_state.cac_dtp_table) { - kfree(tdp_table); - return -ENOMEM; - } - - if (table->ucRevId < 3) { - const ATOM_Tonga_PowerTune_Table *tonga_table = - (ATOM_Tonga_PowerTune_Table *)table; - tdp_table->usTDP = le16_to_cpu(tonga_table->usTDP); - tdp_table->usConfigurableTDP = - le16_to_cpu(tonga_table->usConfigurableTDP); - tdp_table->usTDC = le16_to_cpu(tonga_table->usTDC); - tdp_table->usBatteryPowerLimit = - le16_to_cpu(tonga_table->usBatteryPowerLimit); - tdp_table->usSmallPowerLimit = - le16_to_cpu(tonga_table->usSmallPowerLimit); - tdp_table->usLowCACLeakage = - le16_to_cpu(tonga_table->usLowCACLeakage); - tdp_table->usHighCACLeakage = - le16_to_cpu(tonga_table->usHighCACLeakage); - tdp_table->usMaximumPowerDeliveryLimit = - le16_to_cpu(tonga_table->usMaximumPowerDeliveryLimit); - tdp_table->usDefaultTargetOperatingTemp = - le16_to_cpu(tonga_table->usTjMax); - tdp_table->usTargetOperatingTemp = - le16_to_cpu(tonga_table->usTjMax); /*Set the initial temp to the same as default */ - tdp_table->usPowerTuneDataSetID = - le16_to_cpu(tonga_table->usPowerTuneDataSetID); - tdp_table->usSoftwareShutdownTemp = - le16_to_cpu(tonga_table->usSoftwareShutdownTemp); - tdp_table->usClockStretchAmount = - le16_to_cpu(tonga_table->usClockStretchAmount); - } else { /* Fiji and newer */ - const ATOM_Fiji_PowerTune_Table *fijitable = - (ATOM_Fiji_PowerTune_Table *)table; - tdp_table->usTDP = le16_to_cpu(fijitable->usTDP); - tdp_table->usConfigurableTDP = le16_to_cpu(fijitable->usConfigurableTDP); - tdp_table->usTDC = le16_to_cpu(fijitable->usTDC); - tdp_table->usBatteryPowerLimit = le16_to_cpu(fijitable->usBatteryPowerLimit); - tdp_table->usSmallPowerLimit = le16_to_cpu(fijitable->usSmallPowerLimit); - tdp_table->usLowCACLeakage = le16_to_cpu(fijitable->usLowCACLeakage); - tdp_table->usHighCACLeakage = le16_to_cpu(fijitable->usHighCACLeakage); - tdp_table->usMaximumPowerDeliveryLimit = - le16_to_cpu(fijitable->usMaximumPowerDeliveryLimit); - tdp_table->usDefaultTargetOperatingTemp = - le16_to_cpu(fijitable->usTjMax); - tdp_table->usTargetOperatingTemp = - le16_to_cpu(fijitable->usTjMax); /*Set the initial temp to the same as default */ - tdp_table->usPowerTuneDataSetID = - le16_to_cpu(fijitable->usPowerTuneDataSetID); - tdp_table->usSoftwareShutdownTemp = - le16_to_cpu(fijitable->usSoftwareShutdownTemp); - tdp_table->usClockStretchAmount = - le16_to_cpu(fijitable->usClockStretchAmount); - tdp_table->usTemperatureLimitHotspot = - le16_to_cpu(fijitable->usTemperatureLimitHotspot); - tdp_table->usTemperatureLimitLiquid1 = - le16_to_cpu(fijitable->usTemperatureLimitLiquid1); - tdp_table->usTemperatureLimitLiquid2 = - le16_to_cpu(fijitable->usTemperatureLimitLiquid2); - tdp_table->usTemperatureLimitVrVddc = - le16_to_cpu(fijitable->usTemperatureLimitVrVddc); - tdp_table->usTemperatureLimitVrMvdd = - le16_to_cpu(fijitable->usTemperatureLimitVrMvdd); - tdp_table->usTemperatureLimitPlx = - le16_to_cpu(fijitable->usTemperatureLimitPlx); - tdp_table->ucLiquid1_I2C_address = - fijitable->ucLiquid1_I2C_address; - tdp_table->ucLiquid2_I2C_address = - fijitable->ucLiquid2_I2C_address; - tdp_table->ucLiquid_I2C_Line = - fijitable->ucLiquid_I2C_Line; - tdp_table->ucVr_I2C_address = fijitable->ucVr_I2C_address; - tdp_table->ucVr_I2C_Line = fijitable->ucVr_I2C_Line; - tdp_table->ucPlx_I2C_address = fijitable->ucPlx_I2C_address; - tdp_table->ucPlx_I2C_Line = fijitable->ucPlx_I2C_Line; - } - - *cac_tdp_table = tdp_table; - - return 0; -} - -static int get_mm_clock_voltage_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_mm_clock_voltage_dependency_table **tonga_mm_table, - const ATOM_Tonga_MM_Dependency_Table * mm_dependency_table - ) -{ - uint32_t table_size, i; - const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record; - phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table; - phm_ppt_v1_mm_clock_voltage_dependency_record *mm_table_record; - - PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries), - "Invalid PowerPlay Table!", return -1); - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) - * mm_dependency_table->ucNumEntries; - mm_table = kzalloc(table_size, GFP_KERNEL); - - if (NULL == mm_table) - return -ENOMEM; - - mm_table->count = mm_dependency_table->ucNumEntries; - - for (i = 0; i < mm_dependency_table->ucNumEntries; i++) { - mm_dependency_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_MM_Dependency_Record, - entries, mm_dependency_table, i); - mm_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - phm_ppt_v1_mm_clock_voltage_dependency_record, - entries, mm_table, i); - mm_table_record->vddcInd = mm_dependency_record->ucVddcInd; - mm_table_record->vddgfx_offset = le16_to_cpu(mm_dependency_record->usVddgfxOffset); - mm_table_record->aclk = le32_to_cpu(mm_dependency_record->ulAClk); - mm_table_record->samclock = le32_to_cpu(mm_dependency_record->ulSAMUClk); - mm_table_record->eclk = le32_to_cpu(mm_dependency_record->ulEClk); - mm_table_record->vclk = le32_to_cpu(mm_dependency_record->ulVClk); - mm_table_record->dclk = le32_to_cpu(mm_dependency_record->ulDClk); - } - - *tonga_mm_table = mm_table; - - return 0; -} - -static int get_gpio_table(struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_gpio_table **pp_tonga_gpio_table, - const ATOM_Tonga_GPIO_Table *atom_gpio_table) -{ - uint32_t table_size; - struct phm_ppt_v1_gpio_table *pp_gpio_table; - struct phm_ppt_v1_information *pp_table_information = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - table_size = sizeof(struct phm_ppt_v1_gpio_table); - pp_gpio_table = kzalloc(table_size, GFP_KERNEL); - if (!pp_gpio_table) - return -ENOMEM; - - if (pp_table_information->vdd_dep_on_sclk->count < - atom_gpio_table->ucVRHotTriggeredSclkDpmIndex) - PP_ASSERT_WITH_CODE(false, - "SCLK DPM index for VRHot cannot exceed the total sclk level count!",); - else - pp_gpio_table->vrhot_triggered_sclk_dpm_index = - atom_gpio_table->ucVRHotTriggeredSclkDpmIndex; - - *pp_tonga_gpio_table = pp_gpio_table; - - return 0; -} -/** - * Private Function used during initialization. - * Initialize clock voltage dependency - * @param hwmgr Pointer to the hardware manager. - * @param powerplay_table Pointer to the PowerPlay Table. - */ -static int init_clock_voltage_dependency( - struct pp_hwmgr *hwmgr, - const ATOM_Tonga_POWERPLAYTABLE *powerplay_table - ) -{ - int result = 0; - struct phm_ppt_v1_information *pp_table_information = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - const ATOM_Tonga_MM_Dependency_Table *mm_dependency_table = - (const ATOM_Tonga_MM_Dependency_Table *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usMMDependencyTableOffset)); - const PPTable_Generic_SubTable_Header *pPowerTuneTable = - (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usPowerTuneTableOffset)); - const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = - (const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); - const PPTable_Generic_SubTable_Header *sclk_dep_table = - (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); - const ATOM_Tonga_Hard_Limit_Table *pHardLimits = - (const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usHardLimitTableOffset)); - const PPTable_Generic_SubTable_Header *pcie_table = - (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usPCIETableOffset)); - const ATOM_Tonga_GPIO_Table *gpio_table = - (const ATOM_Tonga_GPIO_Table *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usGPIOTableOffset)); - - pp_table_information->vdd_dep_on_sclk = NULL; - pp_table_information->vdd_dep_on_mclk = NULL; - pp_table_information->mm_dep_table = NULL; - pp_table_information->pcie_table = NULL; - pp_table_information->gpio_table = NULL; - - if (powerplay_table->usMMDependencyTableOffset != 0) - result = get_mm_clock_voltage_table(hwmgr, - &pp_table_information->mm_dep_table, mm_dependency_table); - - if (result == 0 && powerplay_table->usPowerTuneTableOffset != 0) - result = get_cac_tdp_table(hwmgr, - &pp_table_information->cac_dtp_table, pPowerTuneTable); - - if (result == 0 && powerplay_table->usSclkDependencyTableOffset != 0) - result = get_sclk_voltage_dependency_table(hwmgr, - &pp_table_information->vdd_dep_on_sclk, sclk_dep_table); - - if (result == 0 && powerplay_table->usMclkDependencyTableOffset != 0) - result = get_mclk_voltage_dependency_table(hwmgr, - &pp_table_information->vdd_dep_on_mclk, mclk_dep_table); - - if (result == 0 && powerplay_table->usPCIETableOffset != 0) - result = get_pcie_table(hwmgr, - &pp_table_information->pcie_table, pcie_table); - - if (result == 0 && powerplay_table->usHardLimitTableOffset != 0) - result = get_hard_limits(hwmgr, - &pp_table_information->max_clock_voltage_on_dc, pHardLimits); - - hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = - pp_table_information->max_clock_voltage_on_dc.sclk; - hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = - pp_table_information->max_clock_voltage_on_dc.mclk; - hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = - pp_table_information->max_clock_voltage_on_dc.vddc; - hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = - pp_table_information->max_clock_voltage_on_dc.vddci; - - if (result == 0 && (NULL != pp_table_information->vdd_dep_on_mclk) - && (0 != pp_table_information->vdd_dep_on_mclk->count)) - result = get_valid_clk(hwmgr, &pp_table_information->valid_mclk_values, - pp_table_information->vdd_dep_on_mclk); - - if (result == 0 && (NULL != pp_table_information->vdd_dep_on_sclk) - && (0 != pp_table_information->vdd_dep_on_sclk->count)) - result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values, - pp_table_information->vdd_dep_on_sclk); - - if (!result && gpio_table) - result = get_gpio_table(hwmgr, &pp_table_information->gpio_table, - gpio_table); - - return result; -} - -/** Retrieves the (signed) Overdrive limits from VBIOS. - * The max engine clock, memory clock and max temperature come from the firmware info table. - * - * The information is placed into the platform descriptor. - * - * @param hwmgr source of the VBIOS table and owner of the platform descriptor to be updated. - * @param powerplay_table the address of the PowerPlay table. - * - * @return 1 as long as the firmware info table was present and of a supported version. - */ -static int init_over_drive_limits( - struct pp_hwmgr *hwmgr, - const ATOM_Tonga_POWERPLAYTABLE *powerplay_table) -{ - hwmgr->platform_descriptor.overdriveLimit.engineClock = - le32_to_cpu(powerplay_table->ulMaxODEngineClock); - hwmgr->platform_descriptor.overdriveLimit.memoryClock = - le32_to_cpu(powerplay_table->ulMaxODMemoryClock); - - hwmgr->platform_descriptor.minOverdriveVDDC = 0; - hwmgr->platform_descriptor.maxOverdriveVDDC = 0; - hwmgr->platform_descriptor.overdriveVDDCStep = 0; - - return 0; -} - -/** - * Private Function used during initialization. - * Inspect the PowerPlay table for obvious signs of corruption. - * @param hwmgr Pointer to the hardware manager. - * @param powerplay_table Pointer to the PowerPlay Table. - * @exception This implementation always returns 1. - */ -static int init_thermal_controller( - struct pp_hwmgr *hwmgr, - const ATOM_Tonga_POWERPLAYTABLE *powerplay_table - ) -{ - const PPTable_Generic_SubTable_Header *fan_table; - ATOM_Tonga_Thermal_Controller *thermal_controller; - - thermal_controller = (ATOM_Tonga_Thermal_Controller *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usThermalControllerOffset)); - PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset), - "Thermal controller table not set!", return -1); - - hwmgr->thermal_controller.ucType = thermal_controller->ucType; - hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine; - hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress; - - hwmgr->thermal_controller.fanInfo.bNoFan = - (0 != (thermal_controller->ucFanParameters & ATOM_TONGA_PP_FANPARAMETERS_NOFAN)); - - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = - thermal_controller->ucFanParameters & - ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; - - hwmgr->thermal_controller.fanInfo.ulMinRPM - = thermal_controller->ucFanMinRPM * 100UL; - hwmgr->thermal_controller.fanInfo.ulMaxRPM - = thermal_controller->ucFanMaxRPM * 100UL; - - set_hw_cap( - hwmgr, - ATOM_TONGA_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, - PHM_PlatformCaps_ThermalController - ); - - if (0 == powerplay_table->usFanTableOffset) { - hwmgr->thermal_controller.use_hw_fan_control = 1; - return 0; - } - - fan_table = (const PPTable_Generic_SubTable_Header *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usFanTableOffset)); - - PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset), - "Fan table not set!", return -1); - PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId), - "Unsupported fan table format!", return -1); - - hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay - = 100000; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl); - - if (fan_table->ucRevId < 8) { - const ATOM_Tonga_Fan_Table *tonga_fan_table = - (ATOM_Tonga_Fan_Table *)fan_table; - hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst - = tonga_fan_table->ucTHyst; - hwmgr->thermal_controller.advanceFanControlParameters.usTMin - = le16_to_cpu(tonga_fan_table->usTMin); - hwmgr->thermal_controller.advanceFanControlParameters.usTMed - = le16_to_cpu(tonga_fan_table->usTMed); - hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - = le16_to_cpu(tonga_fan_table->usTHigh); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin - = le16_to_cpu(tonga_fan_table->usPWMMin); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - = le16_to_cpu(tonga_fan_table->usPWMMed); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - = le16_to_cpu(tonga_fan_table->usPWMHigh); - hwmgr->thermal_controller.advanceFanControlParameters.usTMax - = 10900; /* hard coded */ - hwmgr->thermal_controller.advanceFanControlParameters.usTMax - = le16_to_cpu(tonga_fan_table->usTMax); - hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode - = tonga_fan_table->ucFanControlMode; - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM - = le16_to_cpu(tonga_fan_table->usFanPWMMax); - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity - = 4836; - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity - = le16_to_cpu(tonga_fan_table->usFanOutputSensitivity); - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM - = le16_to_cpu(tonga_fan_table->usFanRPMMax); - hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit - = (le32_to_cpu(tonga_fan_table->ulMinFanSCLKAcousticLimit) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places. SMC wants MHz. */ - hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature - = tonga_fan_table->ucTargetTemperature; - hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit - = tonga_fan_table->ucMinimumPWMLimit; - } else { - const ATOM_Fiji_Fan_Table *fiji_fan_table = - (ATOM_Fiji_Fan_Table *)fan_table; - hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst - = fiji_fan_table->ucTHyst; - hwmgr->thermal_controller.advanceFanControlParameters.usTMin - = le16_to_cpu(fiji_fan_table->usTMin); - hwmgr->thermal_controller.advanceFanControlParameters.usTMed - = le16_to_cpu(fiji_fan_table->usTMed); - hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - = le16_to_cpu(fiji_fan_table->usTHigh); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin - = le16_to_cpu(fiji_fan_table->usPWMMin); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - = le16_to_cpu(fiji_fan_table->usPWMMed); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - = le16_to_cpu(fiji_fan_table->usPWMHigh); - hwmgr->thermal_controller.advanceFanControlParameters.usTMax - = le16_to_cpu(fiji_fan_table->usTMax); - hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode - = fiji_fan_table->ucFanControlMode; - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM - = le16_to_cpu(fiji_fan_table->usFanPWMMax); - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity - = 4836; - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity - = le16_to_cpu(fiji_fan_table->usFanOutputSensitivity); - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM - = le16_to_cpu(fiji_fan_table->usFanRPMMax); - hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit - = (le32_to_cpu(fiji_fan_table->ulMinFanSCLKAcousticLimit) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places. SMC wants MHz. */ - hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature - = fiji_fan_table->ucTargetTemperature; - hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit - = fiji_fan_table->ucMinimumPWMLimit; - - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge - = le16_to_cpu(fiji_fan_table->usFanGainEdge); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot - = le16_to_cpu(fiji_fan_table->usFanGainHotspot); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid - = le16_to_cpu(fiji_fan_table->usFanGainLiquid); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc - = le16_to_cpu(fiji_fan_table->usFanGainVrVddc); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd - = le16_to_cpu(fiji_fan_table->usFanGainVrMvdd); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx - = le16_to_cpu(fiji_fan_table->usFanGainPlx); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm - = le16_to_cpu(fiji_fan_table->usFanGainHbm); - } - - return 0; -} - -/** - * Private Function used during initialization. - * Inspect the PowerPlay table for obvious signs of corruption. - * @param hwmgr Pointer to the hardware manager. - * @param powerplay_table Pointer to the PowerPlay Table. - * @exception 2 if the powerplay table is incorrect. - */ -static int check_powerplay_tables( - struct pp_hwmgr *hwmgr, - const ATOM_Tonga_POWERPLAYTABLE *powerplay_table - ) -{ - const ATOM_Tonga_State_Array *state_arrays; - - state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usStateArrayOffset)); - - PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <= - powerplay_table->sHeader.ucTableFormatRevision), - "Unsupported PPTable format!", return -1); - PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset), - "State table is not set!", return -1); - PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize), - "Invalid PowerPlay Table!", return -1); - PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries), - "Invalid PowerPlay Table!", return -1); - - return 0; -} - -static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr) -{ - int result = 0; - const ATOM_Tonga_POWERPLAYTABLE *powerplay_table; - - hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL); - - PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), - "Failed to allocate hwmgr->pptable!", return -ENOMEM); - - powerplay_table = get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE((NULL != powerplay_table), - "Missing PowerPlay Table!", return -1); - - result = check_powerplay_tables(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "check_powerplay_tables failed", return result); - - result = set_platform_caps(hwmgr, - le32_to_cpu(powerplay_table->ulPlatformCaps)); - - PP_ASSERT_WITH_CODE((result == 0), - "set_platform_caps failed", return result); - - result = init_thermal_controller(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_thermal_controller failed", return result); - - result = init_over_drive_limits(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_over_drive_limits failed", return result); - - result = init_clock_voltage_dependency(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_clock_voltage_dependency failed", return result); - - result = init_dpm_2_parameters(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_dpm_2_parameters failed", return result); - - return result; -} - -static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *pp_table_information = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - kfree(pp_table_information->vdd_dep_on_sclk); - pp_table_information->vdd_dep_on_sclk = NULL; - - kfree(pp_table_information->vdd_dep_on_mclk); - pp_table_information->vdd_dep_on_mclk = NULL; - - kfree(pp_table_information->valid_mclk_values); - pp_table_information->valid_mclk_values = NULL; - - kfree(pp_table_information->valid_sclk_values); - pp_table_information->valid_sclk_values = NULL; - - kfree(pp_table_information->vddc_lookup_table); - pp_table_information->vddc_lookup_table = NULL; - - kfree(pp_table_information->vddgfx_lookup_table); - pp_table_information->vddgfx_lookup_table = NULL; - - kfree(pp_table_information->mm_dep_table); - pp_table_information->mm_dep_table = NULL; - - kfree(pp_table_information->cac_dtp_table); - pp_table_information->cac_dtp_table = NULL; - - kfree(hwmgr->dyn_state.cac_dtp_table); - hwmgr->dyn_state.cac_dtp_table = NULL; - - kfree(pp_table_information->ppm_parameter_table); - pp_table_information->ppm_parameter_table = NULL; - - kfree(pp_table_information->pcie_table); - pp_table_information->pcie_table = NULL; - - kfree(pp_table_information->gpio_table); - pp_table_information->gpio_table = NULL; - - kfree(hwmgr->pptable); - hwmgr->pptable = NULL; - - return 0; -} - -const struct pp_table_func pptable_v1_0_funcs = { - .pptable_init = pp_tables_v1_0_initialize, - .pptable_fini = pp_tables_v1_0_uninitialize, -}; - -int get_number_of_powerplay_table_entries_v1_0(struct pp_hwmgr *hwmgr) -{ - ATOM_Tonga_State_Array const *state_arrays; - const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE((NULL != pp_table), - "Missing PowerPlay Table!", return -1); - PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >= - ATOM_Tonga_TABLE_REVISION_TONGA), - "Incorrect PowerPlay table revision!", return -1); - - state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) + - le16_to_cpu(pp_table->usStateArrayOffset)); - - return (uint32_t)(state_arrays->ucNumEntries); -} - -/** -* Private function to convert flags stored in the BIOS to software flags in PowerPlay. -*/ -static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, - uint16_t classification, uint16_t classification2) -{ - uint32_t result = 0; - - if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT) - result |= PP_StateClassificationFlag_Boot; - - if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL) - result |= PP_StateClassificationFlag_Thermal; - - if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) - result |= PP_StateClassificationFlag_LimitedPowerSource; - - if (classification & ATOM_PPLIB_CLASSIFICATION_REST) - result |= PP_StateClassificationFlag_Rest; - - if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED) - result |= PP_StateClassificationFlag_Forced; - - if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI) - result |= PP_StateClassificationFlag_ACPI; - - if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) - result |= PP_StateClassificationFlag_LimitedPowerSource_2; - - return result; -} - -static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr) -{ - const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); - const ATOM_Tonga_VCE_State_Table *vce_state_table; - - - if (pp_table == NULL) - return 0; - - vce_state_table = (void *)pp_table + - le16_to_cpu(pp_table->usVCEStateTableOffset); - - return vce_state_table->ucNumEntries; -} - -static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i, - struct amd_vce_state *vce_state, void **clock_info, uint32_t *flag) -{ - const ATOM_Tonga_VCE_State_Record *vce_state_record; - ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record; - ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record; - ATOM_Tonga_MM_Dependency_Record *mm_dep_record; - const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr); - const ATOM_Tonga_VCE_State_Table *vce_state_table = (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pptable) - + le16_to_cpu(pptable->usVCEStateTableOffset)); - const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = (ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long)pptable) - + le16_to_cpu(pptable->usSclkDependencyTableOffset)); - const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = (ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long)pptable) - + le16_to_cpu(pptable->usMclkDependencyTableOffset)); - const ATOM_Tonga_MM_Dependency_Table *mm_dep_table = (ATOM_Tonga_MM_Dependency_Table *)(((unsigned long)pptable) - + le16_to_cpu(pptable->usMMDependencyTableOffset)); - - PP_ASSERT_WITH_CODE((i < vce_state_table->ucNumEntries), - "Requested state entry ID is out of range!", - return -EINVAL); - - vce_state_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_VCE_State_Record, - entries, vce_state_table, i); - sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_SCLK_Dependency_Record, - entries, sclk_dep_table, - vce_state_record->ucSCLKIndex); - mm_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_MM_Dependency_Record, - entries, mm_dep_table, - vce_state_record->ucVCEClockIndex); - *flag = vce_state_record->ucFlag; - - vce_state->evclk = le32_to_cpu(mm_dep_record->ulEClk); - vce_state->ecclk = le32_to_cpu(mm_dep_record->ulEClk); - vce_state->sclk = le32_to_cpu(sclk_dep_record->ulSclk); - - if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries) - mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_MCLK_Dependency_Record, - entries, mclk_dep_table, - mclk_dep_table->ucNumEntries - 1); - else - mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_MCLK_Dependency_Record, - entries, mclk_dep_table, - vce_state_record->ucMCLKIndex); - - vce_state->mclk = le32_to_cpu(mclk_dep_record->ulMclk); - return 0; -} - -/** -* Create a Power State out of an entry in the PowerPlay table. -* This function is called by the hardware back-end. -* @param hwmgr Pointer to the hardware manager. -* @param entry_index The index of the entry to be extracted from the table. -* @param power_state The address of the PowerState instance being created. -* @return -1 if the entry cannot be retrieved. -*/ -int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr, - uint32_t entry_index, struct pp_power_state *power_state, - int (*call_back_func)(struct pp_hwmgr *, void *, - struct pp_power_state *, void *, uint32_t)) -{ - int result = 0; - const ATOM_Tonga_State_Array *state_arrays; - const ATOM_Tonga_State *state_entry; - const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); - int i, j; - uint32_t flags = 0; - - PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;); - power_state->classification.bios_index = entry_index; - - if (pp_table->sHeader.ucTableFormatRevision >= - ATOM_Tonga_TABLE_REVISION_TONGA) { - state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) + - le16_to_cpu(pp_table->usStateArrayOffset)); - - PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset), - "Invalid PowerPlay Table State Array Offset.", return -1); - PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries), - "Invalid PowerPlay Table State Array.", return -1); - PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), - "Invalid PowerPlay Table State Array Entry.", return -1); - - state_entry = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( - ATOM_Tonga_State, entries, - state_arrays, entry_index); - - result = call_back_func(hwmgr, (void *)state_entry, power_state, - (void *)pp_table, - make_classification_flags(hwmgr, - le16_to_cpu(state_entry->usClassification), - le16_to_cpu(state_entry->usClassification2))); - } - - if (!result && (power_state->classification.flags & - PP_StateClassificationFlag_Boot)) - result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); - - hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr); - - if ((i != 0) && (i <= AMD_MAX_VCE_LEVELS)) { - for (j = 0; j < i; j++) - ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags); - } - - return result; -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h deleted file mode 100644 index b9710abdff01..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _PROCESSPPTABLES_V1_0_H -#define _PROCESSPPTABLES_V1_0_H - -#include "hwmgr.h" - -extern const struct pp_table_func pptable_v1_0_funcs; -extern int get_number_of_powerplay_table_entries_v1_0(struct pp_hwmgr *hwmgr); -extern int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t entry_index, - struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *, - struct pp_power_state *, void *, uint32_t)); - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c deleted file mode 100644 index 719597c5d27d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ /dev/null @@ -1,1732 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <drm/amdgpu_drm.h> -#include "processpptables.h" -#include <atom-types.h> -#include <atombios.h> -#include "pptable.h" -#include "power_state.h" -#include "hwmgr.h" -#include "hardwaremanager.h" - - -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8 24 -#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V9 26 - -#define NUM_BITS_CLOCK_INFO_ARRAY_INDEX 6 - -static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t vce_table_offset = 0; - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) { - const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 = - (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; - - if (powerplay_table3->usExtendendedHeaderOffset > 0) { - const ATOM_PPLIB_EXTENDEDHEADER *extended_header = - (const ATOM_PPLIB_EXTENDEDHEADER *) - (((unsigned long)powerplay_table3) + - le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset)); - if (le16_to_cpu(extended_header->usSize) >= - SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) - vce_table_offset = le16_to_cpu(extended_header->usVCETableOffset); - } - } - - return vce_table_offset; -} - -static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_vce_table_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) - return table_offset + 1; - - return 0; -} - -static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, - powerplay_table); - uint16_t table_size = 0; - - if (table_offset > 0) { - const VCEClockInfoArray *p = (const VCEClockInfoArray *) - (((unsigned long) powerplay_table) + table_offset); - table_size = sizeof(uint8_t) + p->ucNumEntries * sizeof(VCEClockInfo); - } - - return table_size; -} - -static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) - return table_offset + get_vce_clock_info_array_size(hwmgr, - powerplay_table); - - return 0; -} - -static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); - uint16_t table_size = 0; - - if (table_offset > 0) { - const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *ptable = - (const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)(((unsigned long) powerplay_table) + table_offset); - - table_size = sizeof(uint8_t) + ptable->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record); - } - return table_size; -} - -static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); - - if (table_offset > 0) - return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table); - - return 0; -} - -static const ATOM_PPLIB_VCE_State_Table *get_vce_state_table( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table); - - if (table_offset > 0) - return (const ATOM_PPLIB_VCE_State_Table *)(((unsigned long) powerplay_table) + table_offset); - - return NULL; -} - -static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t uvd_table_offset = 0; - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) { - const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 = - (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; - if (powerplay_table3->usExtendendedHeaderOffset > 0) { - const ATOM_PPLIB_EXTENDEDHEADER *extended_header = - (const ATOM_PPLIB_EXTENDEDHEADER *) - (((unsigned long)powerplay_table3) + - le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset)); - if (le16_to_cpu(extended_header->usSize) >= - SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) - uvd_table_offset = le16_to_cpu(extended_header->usUVDTableOffset); - } - } - return uvd_table_offset; -} - -static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_uvd_table_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) - return table_offset + 1; - return 0; -} - -static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, - powerplay_table); - uint16_t table_size = 0; - - if (table_offset > 0) { - const UVDClockInfoArray *p = (const UVDClockInfoArray *) - (((unsigned long) powerplay_table) - + table_offset); - table_size = sizeof(UCHAR) + - p->ucNumEntries * sizeof(UVDClockInfo); - } - - return table_size; -} - -static uint16_t get_uvd_clock_voltage_limit_table_offset( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) - return table_offset + - get_uvd_clock_info_array_size(hwmgr, powerplay_table); - - return 0; -} - -static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t samu_table_offset = 0; - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) { - const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 = - (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; - if (powerplay_table3->usExtendendedHeaderOffset > 0) { - const ATOM_PPLIB_EXTENDEDHEADER *extended_header = - (const ATOM_PPLIB_EXTENDEDHEADER *) - (((unsigned long)powerplay_table3) + - le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset)); - if (le16_to_cpu(extended_header->usSize) >= - SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) - samu_table_offset = le16_to_cpu(extended_header->usSAMUTableOffset); - } - } - - return samu_table_offset; -} - -static uint16_t get_samu_clock_voltage_limit_table_offset( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t table_offset = get_samu_table_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) - return table_offset + 1; - - return 0; -} - -static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t acp_table_offset = 0; - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) { - const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 = - (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; - if (powerplay_table3->usExtendendedHeaderOffset > 0) { - const ATOM_PPLIB_EXTENDEDHEADER *pExtendedHeader = - (const ATOM_PPLIB_EXTENDEDHEADER *) - (((unsigned long)powerplay_table3) + - le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset)); - if (le16_to_cpu(pExtendedHeader->usSize) >= - SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) - acp_table_offset = le16_to_cpu(pExtendedHeader->usACPTableOffset); - } - } - - return acp_table_offset; -} - -static uint16_t get_acp_clock_voltage_limit_table_offset( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table); - - if (tableOffset > 0) - return tableOffset + 1; - - return 0; -} - -static uint16_t get_cacp_tdp_table_offset( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t cacTdpTableOffset = 0; - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) { - const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 = - (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; - if (powerplay_table3->usExtendendedHeaderOffset > 0) { - const ATOM_PPLIB_EXTENDEDHEADER *pExtendedHeader = - (const ATOM_PPLIB_EXTENDEDHEADER *) - (((unsigned long)powerplay_table3) + - le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset)); - if (le16_to_cpu(pExtendedHeader->usSize) >= - SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) - cacTdpTableOffset = le16_to_cpu(pExtendedHeader->usPowerTuneTableOffset); - } - } - - return cacTdpTableOffset; -} - -static int get_cac_tdp_table(struct pp_hwmgr *hwmgr, - struct phm_cac_tdp_table **ptable, - const ATOM_PowerTune_Table *table, - uint16_t us_maximum_power_delivery_limit) -{ - unsigned long table_size; - struct phm_cac_tdp_table *tdp_table; - - table_size = sizeof(unsigned long) + sizeof(struct phm_cac_tdp_table); - - tdp_table = kzalloc(table_size, GFP_KERNEL); - if (NULL == tdp_table) - return -ENOMEM; - - tdp_table->usTDP = le16_to_cpu(table->usTDP); - tdp_table->usConfigurableTDP = le16_to_cpu(table->usConfigurableTDP); - tdp_table->usTDC = le16_to_cpu(table->usTDC); - tdp_table->usBatteryPowerLimit = le16_to_cpu(table->usBatteryPowerLimit); - tdp_table->usSmallPowerLimit = le16_to_cpu(table->usSmallPowerLimit); - tdp_table->usLowCACLeakage = le16_to_cpu(table->usLowCACLeakage); - tdp_table->usHighCACLeakage = le16_to_cpu(table->usHighCACLeakage); - tdp_table->usMaximumPowerDeliveryLimit = us_maximum_power_delivery_limit; - - *ptable = tdp_table; - - return 0; -} - -static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t sclk_vdd_gfx_table_offset = 0; - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) { - const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 = - (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; - if (powerplay_table3->usExtendendedHeaderOffset > 0) { - const ATOM_PPLIB_EXTENDEDHEADER *pExtendedHeader = - (const ATOM_PPLIB_EXTENDEDHEADER *) - (((unsigned long)powerplay_table3) + - le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset)); - if (le16_to_cpu(pExtendedHeader->usSize) >= - SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8) - sclk_vdd_gfx_table_offset = - le16_to_cpu(pExtendedHeader->usSclkVddgfxTableOffset); - } - } - - return sclk_vdd_gfx_table_offset; -} - -static uint16_t get_sclk_vdd_gfx_clock_voltage_dependency_table_offset( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table); - - if (tableOffset > 0) - return tableOffset; - - return 0; -} - - -static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, - struct phm_clock_voltage_dependency_table **ptable, - const ATOM_PPLIB_Clock_Voltage_Dependency_Table *table) -{ - - unsigned long table_size, i; - struct phm_clock_voltage_dependency_table *dep_table; - - table_size = sizeof(unsigned long) + - sizeof(struct phm_clock_voltage_dependency_table) - * table->ucNumEntries; - - dep_table = kzalloc(table_size, GFP_KERNEL); - if (NULL == dep_table) - return -ENOMEM; - - dep_table->count = (unsigned long)table->ucNumEntries; - - for (i = 0; i < dep_table->count; i++) { - dep_table->entries[i].clk = - ((unsigned long)table->entries[i].ucClockHigh << 16) | - le16_to_cpu(table->entries[i].usClockLow); - dep_table->entries[i].v = - (unsigned long)le16_to_cpu(table->entries[i].usVoltage); - } - - *ptable = dep_table; - - return 0; -} - -static int get_valid_clk(struct pp_hwmgr *hwmgr, - struct phm_clock_array **ptable, - const struct phm_clock_voltage_dependency_table *table) -{ - unsigned long table_size, i; - struct phm_clock_array *clock_table; - - table_size = sizeof(unsigned long) + sizeof(unsigned long) * table->count; - clock_table = kzalloc(table_size, GFP_KERNEL); - if (NULL == clock_table) - return -ENOMEM; - - clock_table->count = (unsigned long)table->count; - - for (i = 0; i < clock_table->count; i++) - clock_table->values[i] = (unsigned long)table->entries[i].clk; - - *ptable = clock_table; - - return 0; -} - -static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr, - struct phm_clock_and_voltage_limits *limits, - const ATOM_PPLIB_Clock_Voltage_Limit_Table *table) -{ - limits->sclk = ((unsigned long)table->entries[0].ucSclkHigh << 16) | - le16_to_cpu(table->entries[0].usSclkLow); - limits->mclk = ((unsigned long)table->entries[0].ucMclkHigh << 16) | - le16_to_cpu(table->entries[0].usMclkLow); - limits->vddc = (unsigned long)le16_to_cpu(table->entries[0].usVddc); - limits->vddci = (unsigned long)le16_to_cpu(table->entries[0].usVddci); - - return 0; -} - - -static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, - enum phm_platform_caps cap) -{ - if (enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); - else - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); -} - -static int set_platform_caps(struct pp_hwmgr *hwmgr, - unsigned long powerplay_caps) -{ - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_POWERPLAY), - PHM_PlatformCaps_PowerPlaySupport - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), - PHM_PlatformCaps_BiosPowerSourceControl - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s), - PHM_PlatformCaps_EnableASPML0s - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1), - PHM_PlatformCaps_EnableASPML1 - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS), - PHM_PlatformCaps_EnableBackbias - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC), - PHM_PlatformCaps_AutomaticDCTransition - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY), - PHM_PlatformCaps_GeminiPrimary - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC), - PHM_PlatformCaps_StepVddc - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL), - PHM_PlatformCaps_EnableVoltageControl - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL), - PHM_PlatformCaps_EnableSideportControl - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1), - PHM_PlatformCaps_TurnOffPll_ASPML1 - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_HTLINKCONTROL), - PHM_PlatformCaps_EnableHTLinkControl - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL), - PHM_PlatformCaps_EnableMVDDControl - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL), - PHM_PlatformCaps_ControlVDDCI - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT), - PHM_PlatformCaps_RegulatorHot - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT), - PHM_PlatformCaps_BootStateOnAlert - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT), - PHM_PlatformCaps_DontWaitForVBlankOnAlert - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_BACO), - PHM_PlatformCaps_BACO - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE), - PHM_PlatformCaps_NewCACVoltage - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY), - PHM_PlatformCaps_RevertGPIO5Polarity - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17), - PHM_PlatformCaps_Thermal2GPIO17 - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE), - PHM_PlatformCaps_VRHotGPIOConfigurable - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_TEMP_INVERSION), - PHM_PlatformCaps_TempInversion - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_EVV), - PHM_PlatformCaps_EVV - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL), - PHM_PlatformCaps_CombinePCCWithThermalSignal - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE), - PHM_PlatformCaps_LoadPostProductionFirmware - ); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC), - PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc - ); - - return 0; -} - -static PP_StateClassificationFlags make_classification_flags( - struct pp_hwmgr *hwmgr, - USHORT classification, - USHORT classification2) -{ - PP_StateClassificationFlags result = 0; - - if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT) - result |= PP_StateClassificationFlag_Boot; - - if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL) - result |= PP_StateClassificationFlag_Thermal; - - if (classification & - ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) - result |= PP_StateClassificationFlag_LimitedPowerSource; - - if (classification & ATOM_PPLIB_CLASSIFICATION_REST) - result |= PP_StateClassificationFlag_Rest; - - if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED) - result |= PP_StateClassificationFlag_Forced; - - if (classification & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) - result |= PP_StateClassificationFlag_3DPerformance; - - - if (classification & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) - result |= PP_StateClassificationFlag_ACOverdriveTemplate; - - if (classification & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) - result |= PP_StateClassificationFlag_Uvd; - - if (classification & ATOM_PPLIB_CLASSIFICATION_HDSTATE) - result |= PP_StateClassificationFlag_UvdHD; - - if (classification & ATOM_PPLIB_CLASSIFICATION_SDSTATE) - result |= PP_StateClassificationFlag_UvdSD; - - if (classification & ATOM_PPLIB_CLASSIFICATION_HD2STATE) - result |= PP_StateClassificationFlag_HD2; - - if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI) - result |= PP_StateClassificationFlag_ACPI; - - if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) - result |= PP_StateClassificationFlag_LimitedPowerSource_2; - - - if (classification2 & ATOM_PPLIB_CLASSIFICATION2_ULV) - result |= PP_StateClassificationFlag_ULV; - - if (classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC) - result |= PP_StateClassificationFlag_UvdMVC; - - return result; -} - -static int init_non_clock_fields(struct pp_hwmgr *hwmgr, - struct pp_power_state *ps, - uint8_t version, - const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info) { - unsigned long rrr_index; - unsigned long tmp; - - ps->classification.ui_label = (le16_to_cpu(pnon_clock_info->usClassification) & - ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; - ps->classification.flags = make_classification_flags(hwmgr, - le16_to_cpu(pnon_clock_info->usClassification), - le16_to_cpu(pnon_clock_info->usClassification2)); - - ps->classification.temporary_state = false; - ps->classification.to_be_deleted = false; - tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_SINGLE_DISPLAY_ONLY; - - ps->validation.singleDisplayOnly = (0 != tmp); - - tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_DISALLOW_ON_DC; - - ps->validation.disallowOnDC = (0 != tmp); - - ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> - ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; - - ps->pcie.lanes = 0; - - ps->display.disableFrameModulation = false; - - rrr_index = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK) >> - ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT; - - if (rrr_index != ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED) { - static const uint8_t look_up[(ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK >> ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT) + 1] = \ - { 0, 50, 0 }; - - ps->display.refreshrateSource = PP_RefreshrateSource_Explicit; - ps->display.explicitRefreshrate = look_up[rrr_index]; - ps->display.limitRefreshrate = true; - - if (ps->display.explicitRefreshrate == 0) - ps->display.limitRefreshrate = false; - } else - ps->display.limitRefreshrate = false; - - tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_ENABLE_VARIBRIGHT; - - ps->display.enableVariBright = (0 != tmp); - - tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF; - - ps->memory.dllOff = (0 != tmp); - - ps->memory.m3arb = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_M3ARB_MASK) >> ATOM_PPLIB_M3ARB_SHIFT; - - ps->temperatures.min = PP_TEMPERATURE_UNITS_PER_CENTIGRADES * - pnon_clock_info->ucMinTemperature; - - ps->temperatures.max = PP_TEMPERATURE_UNITS_PER_CENTIGRADES * - pnon_clock_info->ucMaxTemperature; - - tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING; - - ps->software.disableLoadBalancing = tmp; - - tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & - ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS; - - ps->software.enableSleepForTimestamps = (0 != tmp); - - ps->validation.supportedPowerLevels = pnon_clock_info->ucRequiredPower; - - if (ATOM_PPLIB_NONCLOCKINFO_VER1 < version) { - ps->uvd_clocks.VCLK = le32_to_cpu(pnon_clock_info->ulVCLK); - ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK); - } else { - ps->uvd_clocks.VCLK = 0; - ps->uvd_clocks.DCLK = 0; - } - - return 0; -} - -static ULONG size_of_entry_v2(ULONG num_dpm_levels) -{ - return (sizeof(UCHAR) + sizeof(UCHAR) + - (num_dpm_levels * sizeof(UCHAR))); -} - -static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2( - const StateArray * pstate_arrays, - ULONG entry_index) -{ - ULONG i; - const ATOM_PPLIB_STATE_V2 *pstate; - - pstate = pstate_arrays->states; - if (entry_index <= pstate_arrays->ucNumEntries) { - for (i = 0; i < entry_index; i++) - pstate = (ATOM_PPLIB_STATE_V2 *)( - (unsigned long)pstate + - size_of_entry_v2(pstate->ucNumDPMLevels)); - } - return pstate; -} - -static const unsigned char soft_dummy_pp_table[] = { - 0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 0x00, 0x6c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x18, 0x05, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1, 0x00, 0x43, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x8e, 0x01, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c, - 0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x70, 0x00, 0x91, 0xf4, 0x00, - 0x64, 0x00, 0x40, 0x19, 0x01, 0x5a, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a, - 0x00, 0x00, 0x09, 0x30, 0x75, 0x00, 0x30, 0x75, 0x00, 0x40, 0x9c, 0x00, 0x40, 0x9c, 0x00, 0x59, - 0xd8, 0x00, 0x59, 0xd8, 0x00, 0x91, 0xf4, 0x00, 0x91, 0xf4, 0x00, 0x0e, 0x28, 0x01, 0x0e, 0x28, - 0x01, 0x90, 0x5f, 0x01, 0x90, 0x5f, 0x01, 0x00, 0x77, 0x01, 0x00, 0x77, 0x01, 0xca, 0x91, 0x01, - 0xca, 0x91, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01, - 0x7c, 0x00, 0x02, 0x70, 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a, - 0x00, 0x07, 0x08, 0x08, 0x00, 0x08, 0x00, 0x01, 0x02, 0x02, 0x02, 0x01, 0x02, 0x02, 0x02, 0x03, - 0x02, 0x04, 0x02, 0x00, 0x08, 0x40, 0x9c, 0x00, 0x30, 0x75, 0x00, 0x74, 0xb5, 0x00, 0xa0, 0x8c, - 0x00, 0x60, 0xea, 0x00, 0x74, 0xb5, 0x00, 0x0e, 0x28, 0x01, 0x60, 0xea, 0x00, 0x90, 0x5f, 0x01, - 0x40, 0x19, 0x01, 0xb2, 0xb0, 0x01, 0x90, 0x5f, 0x01, 0xc0, 0xd4, 0x01, 0x00, 0x77, 0x01, 0x5e, - 0xff, 0x01, 0xca, 0x91, 0x01, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01, 0x7c, 0x00, 0x02, 0x70, - 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a, 0x00, 0x07, 0x00, 0x08, - 0x80, 0x00, 0x30, 0x75, 0x00, 0x7e, 0x00, 0x40, 0x9c, 0x00, 0x7c, 0x00, 0x59, 0xd8, 0x00, 0x70, - 0x00, 0xdc, 0x0b, 0x01, 0x64, 0x00, 0x80, 0x38, 0x01, 0x5a, 0x00, 0x80, 0x38, 0x01, 0x52, 0x00, - 0x80, 0x38, 0x01, 0x4a, 0x00, 0x80, 0x38, 0x01, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c, - 0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x74, 0x00, 0x91, 0xf4, 0x00, - 0x66, 0x00, 0x40, 0x19, 0x01, 0x58, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a, - 0x00 -}; - -static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( - struct pp_hwmgr *hwmgr) -{ - const void *table_addr = hwmgr->soft_pp_table; - uint8_t frev, crev; - uint16_t size; - - if (!table_addr) { - if (hwmgr->chip_id == CHIP_RAVEN) { - table_addr = &soft_dummy_pp_table[0]; - hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; - hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); - } else { - table_addr = smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, PowerPlayInfo), - &size, &frev, &crev); - hwmgr->soft_pp_table = table_addr; - hwmgr->soft_pp_table_size = size; - } - } - - return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr; -} - -int pp_tables_get_response_times(struct pp_hwmgr *hwmgr, - uint32_t *vol_rep_time, uint32_t *bb_rep_time) -{ - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_tab = get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE(NULL != powerplay_tab, - "Missing PowerPlay Table!", return -EINVAL); - - *vol_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usVoltageTime); - *bb_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usBackbiasTime); - - return 0; -} - -int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr, - unsigned long *num_of_entries) -{ - const StateArray *pstate_arrays; - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); - - if (powerplay_table == NULL) - return -1; - - if (powerplay_table->sHeader.ucTableFormatRevision >= 6) { - pstate_arrays = (StateArray *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usStateArrayOffset)); - - *num_of_entries = (unsigned long)(pstate_arrays->ucNumEntries); - } else - *num_of_entries = (unsigned long)(powerplay_table->ucNumStates); - - return 0; -} - -int pp_tables_get_entry(struct pp_hwmgr *hwmgr, - unsigned long entry_index, - struct pp_power_state *ps, - pp_tables_hw_clock_info_callback func) -{ - int i; - const StateArray *pstate_arrays; - const ATOM_PPLIB_STATE_V2 *pstate_entry_v2; - const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info; - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); - int result = 0; - int res = 0; - - const ClockInfoArray *pclock_arrays; - - const NonClockInfoArray *pnon_clock_arrays; - - const ATOM_PPLIB_STATE *pstate_entry; - - if (powerplay_table == NULL) - return -1; - - ps->classification.bios_index = entry_index; - - if (powerplay_table->sHeader.ucTableFormatRevision >= 6) { - pstate_arrays = (StateArray *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usStateArrayOffset)); - - if (entry_index > pstate_arrays->ucNumEntries) - return -1; - - pstate_entry_v2 = get_state_entry_v2(pstate_arrays, entry_index); - pclock_arrays = (ClockInfoArray *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usClockInfoArrayOffset)); - - pnon_clock_arrays = (NonClockInfoArray *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usNonClockInfoArrayOffset)); - - pnon_clock_info = (ATOM_PPLIB_NONCLOCK_INFO *)((unsigned long)(pnon_clock_arrays->nonClockInfo) + - (pstate_entry_v2->nonClockInfoIndex * pnon_clock_arrays->ucEntrySize)); - - result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info); - - for (i = 0; i < pstate_entry_v2->ucNumDPMLevels; i++) { - const void *pclock_info = (const void *)( - (unsigned long)(pclock_arrays->clockInfo) + - (pstate_entry_v2->clockInfoIndex[i] * pclock_arrays->ucEntrySize)); - res = func(hwmgr, &ps->hardware, i, pclock_info); - if ((0 == result) && (0 != res)) - result = res; - } - } else { - if (entry_index > powerplay_table->ucNumStates) - return -1; - - pstate_entry = (ATOM_PPLIB_STATE *)((unsigned long)powerplay_table + - le16_to_cpu(powerplay_table->usStateArrayOffset) + - entry_index * powerplay_table->ucStateEntrySize); - - pnon_clock_info = (ATOM_PPLIB_NONCLOCK_INFO *)((unsigned long)powerplay_table + - le16_to_cpu(powerplay_table->usNonClockInfoArrayOffset) + - pstate_entry->ucNonClockStateIndex * - powerplay_table->ucNonClockSize); - - result = init_non_clock_fields(hwmgr, ps, - powerplay_table->ucNonClockSize, - pnon_clock_info); - - for (i = 0; i < powerplay_table->ucStateEntrySize-1; i++) { - const void *pclock_info = (const void *)((unsigned long)powerplay_table + - le16_to_cpu(powerplay_table->usClockInfoArrayOffset) + - pstate_entry->ucClockStateIndices[i] * - powerplay_table->ucClockInfoSize); - - int res = func(hwmgr, &ps->hardware, i, pclock_info); - - if ((0 == result) && (0 != res)) - result = res; - } - } - - if ((0 == result) && (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot))) { - if (hwmgr->chip_family < AMDGPU_FAMILY_RV) - result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware)); - } - - return result; -} - -static int init_powerplay_tables( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table -) -{ - return 0; -} - - -static int init_thermal_controller( - struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - hwmgr->thermal_controller.ucType = - powerplay_table->sThermalController.ucType; - hwmgr->thermal_controller.ucI2cLine = - powerplay_table->sThermalController.ucI2cLine; - hwmgr->thermal_controller.ucI2cAddress = - powerplay_table->sThermalController.ucI2cAddress; - - hwmgr->thermal_controller.fanInfo.bNoFan = - (0 != (powerplay_table->sThermalController.ucFanParameters & - ATOM_PP_FANPARAMETERS_NOFAN)); - - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = - powerplay_table->sThermalController.ucFanParameters & - ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; - - hwmgr->thermal_controller.fanInfo.ulMinRPM - = powerplay_table->sThermalController.ucFanMinRPM * 100UL; - hwmgr->thermal_controller.fanInfo.ulMaxRPM - = powerplay_table->sThermalController.ucFanMaxRPM * 100UL; - - set_hw_cap(hwmgr, - ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, - PHM_PlatformCaps_ThermalController); - - hwmgr->thermal_controller.use_hw_fan_control = 1; - - return 0; -} - -static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table, - const ATOM_FIRMWARE_INFO_V1_4 *fw_info) -{ - hwmgr->platform_descriptor.overdriveLimit.engineClock = - le32_to_cpu(fw_info->ulASICMaxEngineClock); - - hwmgr->platform_descriptor.overdriveLimit.memoryClock = - le32_to_cpu(fw_info->ulASICMaxMemoryClock); - - hwmgr->platform_descriptor.maxOverdriveVDDC = - le32_to_cpu(fw_info->ul3DAccelerationEngineClock) & 0x7FF; - - hwmgr->platform_descriptor.minOverdriveVDDC = - le16_to_cpu(fw_info->usBootUpVDDCVoltage); - - hwmgr->platform_descriptor.maxOverdriveVDDC = - le16_to_cpu(fw_info->usBootUpVDDCVoltage); - - hwmgr->platform_descriptor.overdriveVDDCStep = 0; - return 0; -} - -static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table, - const ATOM_FIRMWARE_INFO_V2_1 *fw_info) -{ - const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3; - const ATOM_PPLIB_EXTENDEDHEADER *header; - - if (le16_to_cpu(powerplay_table->usTableSize) < - sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) - return 0; - - powerplay_table3 = (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table; - - if (0 == powerplay_table3->usExtendendedHeaderOffset) - return 0; - - header = (ATOM_PPLIB_EXTENDEDHEADER *)(((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset)); - - hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); - hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock); - - - hwmgr->platform_descriptor.minOverdriveVDDC = 0; - hwmgr->platform_descriptor.maxOverdriveVDDC = 0; - hwmgr->platform_descriptor.overdriveVDDCStep = 0; - - return 0; -} - -static int init_overdrive_limits(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - int result = 0; - uint8_t frev, crev; - uint16_t size; - - const ATOM_COMMON_TABLE_HEADER *fw_info = NULL; - - hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; - hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0; - hwmgr->platform_descriptor.minOverdriveVDDC = 0; - hwmgr->platform_descriptor.maxOverdriveVDDC = 0; - hwmgr->platform_descriptor.overdriveVDDCStep = 0; - - if (hwmgr->chip_id == CHIP_RAVEN) - return 0; - - /* We assume here that fw_info is unchanged if this call fails.*/ - fw_info = smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, FirmwareInfo), - &size, &frev, &crev); - - if ((fw_info->ucTableFormatRevision == 1) - && (le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V1_4))) - result = init_overdrive_limits_V1_4(hwmgr, - powerplay_table, - (const ATOM_FIRMWARE_INFO_V1_4 *)fw_info); - - else if ((fw_info->ucTableFormatRevision == 2) - && (le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V2_1))) - result = init_overdrive_limits_V2_1(hwmgr, - powerplay_table, - (const ATOM_FIRMWARE_INFO_V2_1 *)fw_info); - - return result; -} - -static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, - struct phm_uvd_clock_voltage_dependency_table **ptable, - const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *table, - const UVDClockInfoArray *array) -{ - unsigned long table_size, i; - struct phm_uvd_clock_voltage_dependency_table *uvd_table; - - table_size = sizeof(unsigned long) + - sizeof(struct phm_uvd_clock_voltage_dependency_table) * - table->numEntries; - - uvd_table = kzalloc(table_size, GFP_KERNEL); - if (NULL == uvd_table) - return -ENOMEM; - - uvd_table->count = table->numEntries; - - for (i = 0; i < table->numEntries; i++) { - const UVDClockInfo *entry = - &array->entries[table->entries[i].ucUVDClockInfoIndex]; - uvd_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage); - uvd_table->entries[i].vclk = ((unsigned long)entry->ucVClkHigh << 16) - | le16_to_cpu(entry->usVClkLow); - uvd_table->entries[i].dclk = ((unsigned long)entry->ucDClkHigh << 16) - | le16_to_cpu(entry->usDClkLow); - } - - *ptable = uvd_table; - - return 0; -} - -static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, - struct phm_vce_clock_voltage_dependency_table **ptable, - const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table, - const VCEClockInfoArray *array) -{ - unsigned long table_size, i; - struct phm_vce_clock_voltage_dependency_table *vce_table = NULL; - - table_size = sizeof(unsigned long) + - sizeof(struct phm_vce_clock_voltage_dependency_table) - * table->numEntries; - - vce_table = kzalloc(table_size, GFP_KERNEL); - if (NULL == vce_table) - return -ENOMEM; - - vce_table->count = table->numEntries; - for (i = 0; i < table->numEntries; i++) { - const VCEClockInfo *entry = &array->entries[table->entries[i].ucVCEClockInfoIndex]; - - vce_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage); - vce_table->entries[i].evclk = ((unsigned long)entry->ucEVClkHigh << 16) - | le16_to_cpu(entry->usEVClkLow); - vce_table->entries[i].ecclk = ((unsigned long)entry->ucECClkHigh << 16) - | le16_to_cpu(entry->usECClkLow); - } - - *ptable = vce_table; - - return 0; -} - -static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, - struct phm_samu_clock_voltage_dependency_table **ptable, - const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *table) -{ - unsigned long table_size, i; - struct phm_samu_clock_voltage_dependency_table *samu_table; - - table_size = sizeof(unsigned long) + - sizeof(struct phm_samu_clock_voltage_dependency_table) * - table->numEntries; - - samu_table = kzalloc(table_size, GFP_KERNEL); - if (NULL == samu_table) - return -ENOMEM; - - samu_table->count = table->numEntries; - - for (i = 0; i < table->numEntries; i++) { - samu_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage); - samu_table->entries[i].samclk = ((unsigned long)table->entries[i].ucSAMClockHigh << 16) - | le16_to_cpu(table->entries[i].usSAMClockLow); - } - - *ptable = samu_table; - - return 0; -} - -static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, - struct phm_acp_clock_voltage_dependency_table **ptable, - const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *table) -{ - unsigned table_size, i; - struct phm_acp_clock_voltage_dependency_table *acp_table; - - table_size = sizeof(unsigned long) + - sizeof(struct phm_acp_clock_voltage_dependency_table) * - table->numEntries; - - acp_table = kzalloc(table_size, GFP_KERNEL); - if (NULL == acp_table) - return -ENOMEM; - - acp_table->count = (unsigned long)table->numEntries; - - for (i = 0; i < table->numEntries; i++) { - acp_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage); - acp_table->entries[i].acpclk = ((unsigned long)table->entries[i].ucACPClockHigh << 16) - | le16_to_cpu(table->entries[i].usACPClockLow); - } - - *ptable = acp_table; - - return 0; -} - -static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - ATOM_PPLIB_Clock_Voltage_Dependency_Table *table; - ATOM_PPLIB_Clock_Voltage_Limit_Table *limit_table; - int result = 0; - - uint16_t vce_clock_info_array_offset; - uint16_t uvd_clock_info_array_offset; - uint16_t table_offset; - - hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; - hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; - hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; - hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; - hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; - hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; - hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; - hwmgr->dyn_state.ppm_parameter_table = NULL; - hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; - - vce_clock_info_array_offset = get_vce_clock_info_array_offset( - hwmgr, powerplay_table); - table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, - powerplay_table); - if (vce_clock_info_array_offset > 0 && table_offset > 0) { - const VCEClockInfoArray *array = (const VCEClockInfoArray *) - (((unsigned long) powerplay_table) + - vce_clock_info_array_offset); - const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table = - (const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *) - (((unsigned long) powerplay_table) + table_offset); - result = get_vce_clock_voltage_limit_table(hwmgr, - &hwmgr->dyn_state.vce_clock_voltage_dependency_table, - table, array); - } - - uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table); - table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table); - - if (uvd_clock_info_array_offset > 0 && table_offset > 0) { - const UVDClockInfoArray *array = (const UVDClockInfoArray *) - (((unsigned long) powerplay_table) + - uvd_clock_info_array_offset); - const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *ptable = - (const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *) - (((unsigned long) powerplay_table) + table_offset); - result = get_uvd_clock_voltage_limit_table(hwmgr, - &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array); - } - - table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) { - const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *ptable = - (const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *) - (((unsigned long) powerplay_table) + table_offset); - result = get_samu_clock_voltage_limit_table(hwmgr, - &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable); - } - - table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) { - const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *ptable = - (const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *) - (((unsigned long) powerplay_table) + table_offset); - result = get_acp_clock_voltage_limit_table(hwmgr, - &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable); - } - - table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table); - if (table_offset > 0) { - UCHAR rev_id = *(UCHAR *)(((unsigned long)powerplay_table) + table_offset); - - if (rev_id > 0) { - const ATOM_PPLIB_POWERTUNE_Table_V1 *tune_table = - (const ATOM_PPLIB_POWERTUNE_Table_V1 *) - (((unsigned long) powerplay_table) + table_offset); - result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table, - &tune_table->power_tune_table, - le16_to_cpu(tune_table->usMaximumPowerDeliveryLimit)); - hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = - le16_to_cpu(tune_table->usTjMax); - } else { - const ATOM_PPLIB_POWERTUNE_Table *tune_table = - (const ATOM_PPLIB_POWERTUNE_Table *) - (((unsigned long) powerplay_table) + table_offset); - result = get_cac_tdp_table(hwmgr, - &hwmgr->dyn_state.cac_dtp_table, - &tune_table->power_tune_table, 255); - } - } - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE4)) { - const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 = - (const ATOM_PPLIB_POWERPLAYTABLE4 *)powerplay_table; - if (0 != powerplay_table4->usVddcDependencyOnSCLKOffset) { - table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) - (((unsigned long) powerplay_table4) + - le16_to_cpu(powerplay_table4->usVddcDependencyOnSCLKOffset)); - result = get_clock_voltage_dependency_table(hwmgr, - &hwmgr->dyn_state.vddc_dependency_on_sclk, table); - } - - if (result == 0 && (0 != powerplay_table4->usVddciDependencyOnMCLKOffset)) { - table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) - (((unsigned long) powerplay_table4) + - le16_to_cpu(powerplay_table4->usVddciDependencyOnMCLKOffset)); - result = get_clock_voltage_dependency_table(hwmgr, - &hwmgr->dyn_state.vddci_dependency_on_mclk, table); - } - - if (result == 0 && (0 != powerplay_table4->usVddcDependencyOnMCLKOffset)) { - table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) - (((unsigned long) powerplay_table4) + - le16_to_cpu(powerplay_table4->usVddcDependencyOnMCLKOffset)); - result = get_clock_voltage_dependency_table(hwmgr, - &hwmgr->dyn_state.vddc_dependency_on_mclk, table); - } - - if (result == 0 && (0 != powerplay_table4->usMaxClockVoltageOnDCOffset)) { - limit_table = (ATOM_PPLIB_Clock_Voltage_Limit_Table *) - (((unsigned long) powerplay_table4) + - le16_to_cpu(powerplay_table4->usMaxClockVoltageOnDCOffset)); - result = get_clock_voltage_limit(hwmgr, - &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table); - } - - if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) && - (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count)) - result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values, - hwmgr->dyn_state.vddc_dependency_on_mclk); - - if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && - (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) - result = get_valid_clk(hwmgr, - &hwmgr->dyn_state.valid_sclk_values, - hwmgr->dyn_state.vddc_dependency_on_sclk); - - if (result == 0 && (0 != powerplay_table4->usMvddDependencyOnMCLKOffset)) { - table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) - (((unsigned long) powerplay_table4) + - le16_to_cpu(powerplay_table4->usMvddDependencyOnMCLKOffset)); - result = get_clock_voltage_dependency_table(hwmgr, - &hwmgr->dyn_state.mvdd_dependency_on_mclk, table); - } - } - - table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr, - powerplay_table); - - if (table_offset > 0) { - table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) - (((unsigned long) powerplay_table) + table_offset); - result = get_clock_voltage_dependency_table(hwmgr, - &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table); - } - - return result; -} - -static int get_cac_leakage_table(struct pp_hwmgr *hwmgr, - struct phm_cac_leakage_table **ptable, - const ATOM_PPLIB_CAC_Leakage_Table *table) -{ - struct phm_cac_leakage_table *cac_leakage_table; - unsigned long table_size, i; - - if (hwmgr == NULL || table == NULL || ptable == NULL) - return -EINVAL; - - table_size = sizeof(ULONG) + - (sizeof(struct phm_cac_leakage_table) * table->ucNumEntries); - - cac_leakage_table = kzalloc(table_size, GFP_KERNEL); - - if (cac_leakage_table == NULL) - return -ENOMEM; - - cac_leakage_table->count = (ULONG)table->ucNumEntries; - - for (i = 0; i < cac_leakage_table->count; i++) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EVV)) { - cac_leakage_table->entries[i].Vddc1 = le16_to_cpu(table->entries[i].usVddc1); - cac_leakage_table->entries[i].Vddc2 = le16_to_cpu(table->entries[i].usVddc2); - cac_leakage_table->entries[i].Vddc3 = le16_to_cpu(table->entries[i].usVddc3); - } else { - cac_leakage_table->entries[i].Vddc = le16_to_cpu(table->entries[i].usVddc); - cac_leakage_table->entries[i].Leakage = le32_to_cpu(table->entries[i].ulLeakageValue); - } - } - - *ptable = cac_leakage_table; - - return 0; -} - -static int get_platform_power_management_table(struct pp_hwmgr *hwmgr, - ATOM_PPLIB_PPM_Table *atom_ppm_table) -{ - struct phm_ppm_table *ptr = kzalloc(sizeof(struct phm_ppm_table), GFP_KERNEL); - - if (NULL == ptr) - return -ENOMEM; - - ptr->ppm_design = atom_ppm_table->ucPpmDesign; - ptr->cpu_core_number = le16_to_cpu(atom_ppm_table->usCpuCoreNumber); - ptr->platform_tdp = le32_to_cpu(atom_ppm_table->ulPlatformTDP); - ptr->small_ac_platform_tdp = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDP); - ptr->platform_tdc = le32_to_cpu(atom_ppm_table->ulPlatformTDC); - ptr->small_ac_platform_tdc = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDC); - ptr->apu_tdp = le32_to_cpu(atom_ppm_table->ulApuTDP); - ptr->dgpu_tdp = le32_to_cpu(atom_ppm_table->ulDGpuTDP); - ptr->dgpu_ulv_power = le32_to_cpu(atom_ppm_table->ulDGpuUlvPower); - ptr->tj_max = le32_to_cpu(atom_ppm_table->ulTjmax); - hwmgr->dyn_state.ppm_parameter_table = ptr; - - return 0; -} - -static int init_dpm2_parameters(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - int result = 0; - - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE5)) { - const ATOM_PPLIB_POWERPLAYTABLE5 *ptable5 = - (const ATOM_PPLIB_POWERPLAYTABLE5 *)powerplay_table; - const ATOM_PPLIB_POWERPLAYTABLE4 *ptable4 = - (const ATOM_PPLIB_POWERPLAYTABLE4 *) - (&ptable5->basicTable4); - const ATOM_PPLIB_POWERPLAYTABLE3 *ptable3 = - (const ATOM_PPLIB_POWERPLAYTABLE3 *) - (&ptable4->basicTable3); - const ATOM_PPLIB_EXTENDEDHEADER *extended_header; - uint16_t table_offset; - ATOM_PPLIB_PPM_Table *atom_ppm_table; - - hwmgr->platform_descriptor.TDPLimit = le32_to_cpu(ptable5->ulTDPLimit); - hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit); - - hwmgr->platform_descriptor.TDPODLimit = le16_to_cpu(ptable5->usTDPODLimit); - hwmgr->platform_descriptor.TDPAdjustment = 0; - - hwmgr->platform_descriptor.VidAdjustment = 0; - hwmgr->platform_descriptor.VidAdjustmentPolarity = 0; - hwmgr->platform_descriptor.VidMinLimit = 0; - hwmgr->platform_descriptor.VidMaxLimit = 1500000; - hwmgr->platform_descriptor.VidStep = 6250; - - hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit); - - if (hwmgr->platform_descriptor.TDPODLimit != 0) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerControl); - - hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold); - - hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage); - - hwmgr->dyn_state.cac_leakage_table = NULL; - - if (0 != ptable5->usCACLeakageTableOffset) { - const ATOM_PPLIB_CAC_Leakage_Table *pCAC_leakage_table = - (ATOM_PPLIB_CAC_Leakage_Table *)(((unsigned long)ptable5) + - le16_to_cpu(ptable5->usCACLeakageTableOffset)); - result = get_cac_leakage_table(hwmgr, - &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table); - } - - hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope); - - hwmgr->dyn_state.ppm_parameter_table = NULL; - - if (0 != ptable3->usExtendendedHeaderOffset) { - extended_header = (const ATOM_PPLIB_EXTENDEDHEADER *) - (((unsigned long)powerplay_table) + - le16_to_cpu(ptable3->usExtendendedHeaderOffset)); - if ((extended_header->usPPMTableOffset > 0) && - le16_to_cpu(extended_header->usSize) >= - SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) { - table_offset = le16_to_cpu(extended_header->usPPMTableOffset); - atom_ppm_table = (ATOM_PPLIB_PPM_Table *) - (((unsigned long)powerplay_table) + table_offset); - if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table)) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnablePlatformPowerManagement); - } - } - } - return result; -} - -static int init_phase_shedding_table(struct pp_hwmgr *hwmgr, - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) -{ - if (le16_to_cpu(powerplay_table->usTableSize) >= - sizeof(ATOM_PPLIB_POWERPLAYTABLE4)) { - const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 = - (const ATOM_PPLIB_POWERPLAYTABLE4 *)powerplay_table; - - if (0 != powerplay_table4->usVddcPhaseShedLimitsTableOffset) { - const ATOM_PPLIB_PhaseSheddingLimits_Table *ptable = - (ATOM_PPLIB_PhaseSheddingLimits_Table *) - (((unsigned long)powerplay_table4) + - le16_to_cpu(powerplay_table4->usVddcPhaseShedLimitsTableOffset)); - struct phm_phase_shedding_limits_table *table; - unsigned long size, i; - - - size = sizeof(unsigned long) + - (sizeof(struct phm_phase_shedding_limits_table) * - ptable->ucNumEntries); - - table = kzalloc(size, GFP_KERNEL); - - if (table == NULL) - return -ENOMEM; - - table->count = (unsigned long)ptable->ucNumEntries; - - for (i = 0; i < table->count; i++) { - table->entries[i].Voltage = (unsigned long)le16_to_cpu(ptable->entries[i].usVoltage); - table->entries[i].Sclk = ((unsigned long)ptable->entries[i].ucSclkHigh << 16) - | le16_to_cpu(ptable->entries[i].usSclkLow); - table->entries[i].Mclk = ((unsigned long)ptable->entries[i].ucMclkHigh << 16) - | le16_to_cpu(ptable->entries[i].usMclkLow); - } - hwmgr->dyn_state.vddc_phase_shed_limits_table = table; - } - } - - return 0; -} - -static int get_number_of_vce_state_table_entries( - struct pp_hwmgr *hwmgr) -{ - const ATOM_PPLIB_POWERPLAYTABLE *table = - get_powerplay_table(hwmgr); - const ATOM_PPLIB_VCE_State_Table *vce_table = - get_vce_state_table(hwmgr, table); - - if (vce_table) - return vce_table->numEntries; - - return 0; -} - -static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr, - unsigned long i, - struct amd_vce_state *vce_state, - void **clock_info, - unsigned long *flag) -{ - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); - - const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table); - - unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_table); - - const VCEClockInfoArray *vce_clock_info_array = (const VCEClockInfoArray *)(((unsigned long) powerplay_table) + vce_clock_info_array_offset); - - const ClockInfoArray *clock_arrays = (ClockInfoArray *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usClockInfoArrayOffset)); - - const ATOM_PPLIB_VCE_State_Record *record = &vce_state_table->entries[i]; - - const VCEClockInfo *vce_clock_info = &vce_clock_info_array->entries[record->ucVCEClockInfoIndex]; - - unsigned long clockInfoIndex = record->ucClockInfoIndex & 0x3F; - - *flag = (record->ucClockInfoIndex >> NUM_BITS_CLOCK_INFO_ARRAY_INDEX); - - vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | le16_to_cpu(vce_clock_info->usEVClkLow); - vce_state->ecclk = ((uint32_t)vce_clock_info->ucECClkHigh << 16) | le16_to_cpu(vce_clock_info->usECClkLow); - - *clock_info = (void *)((unsigned long)(clock_arrays->clockInfo) + (clockInfoIndex * clock_arrays->ucEntrySize)); - - return 0; -} - - -static int pp_tables_initialize(struct pp_hwmgr *hwmgr) -{ - int result; - const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; - - if (hwmgr->chip_id == CHIP_RAVEN) - return 0; - - hwmgr->need_pp_table_upload = true; - - powerplay_table = get_powerplay_table(hwmgr); - - result = init_powerplay_tables(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_powerplay_tables failed", return result); - - result = set_platform_caps(hwmgr, - le32_to_cpu(powerplay_table->ulPlatformCaps)); - - PP_ASSERT_WITH_CODE((result == 0), - "set_platform_caps failed", return result); - - result = init_thermal_controller(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_thermal_controller failed", return result); - - result = init_overdrive_limits(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_overdrive_limits failed", return result); - - result = init_clock_voltage_dependency(hwmgr, - powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_clock_voltage_dependency failed", return result); - - result = init_dpm2_parameters(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_dpm2_parameters failed", return result); - - result = init_phase_shedding_table(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_phase_shedding_table failed", return result); - - return result; -} - -static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->chip_id == CHIP_RAVEN) - return 0; - - kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); - hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; - - kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); - hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; - - kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); - hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; - - kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); - hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; - - kfree(hwmgr->dyn_state.valid_mclk_values); - hwmgr->dyn_state.valid_mclk_values = NULL; - - kfree(hwmgr->dyn_state.valid_sclk_values); - hwmgr->dyn_state.valid_sclk_values = NULL; - - kfree(hwmgr->dyn_state.cac_leakage_table); - hwmgr->dyn_state.cac_leakage_table = NULL; - - kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); - hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; - - kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); - hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; - - kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); - hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; - - kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); - hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; - - kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); - hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; - - kfree(hwmgr->dyn_state.cac_dtp_table); - hwmgr->dyn_state.cac_dtp_table = NULL; - - kfree(hwmgr->dyn_state.ppm_parameter_table); - hwmgr->dyn_state.ppm_parameter_table = NULL; - - kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); - hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; - - return 0; -} - -const struct pp_table_func pptable_funcs = { - .pptable_init = pp_tables_initialize, - .pptable_fini = pp_tables_uninitialize, - .pptable_get_number_of_vce_state_table_entries = - get_number_of_vce_state_table_entries, - .pptable_get_vce_state_table_entry = - get_vce_state_table_entry, -}; - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h deleted file mode 100644 index baddaa75693b..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * Interface Functions related to the BIOS PowerPlay Tables. - * - */ - -#ifndef PROCESSPPTABLES_H -#define PROCESSPPTABLES_H - -struct pp_hwmgr; -struct pp_power_state; -struct pp_hw_power_state; - -extern const struct pp_table_func pptable_funcs; - -typedef int (*pp_tables_hw_clock_info_callback)(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps, - unsigned int index, - const void *clock_info); - -int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr, - unsigned long *num_of_entries); - -int pp_tables_get_entry(struct pp_hwmgr *hwmgr, - unsigned long entry_index, - struct pp_power_state *ps, - pp_tables_hw_clock_info_callback func); - -int pp_tables_get_response_times(struct pp_hwmgr *hwmgr, - uint32_t *vol_rep_time, uint32_t *bb_rep_time); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c deleted file mode 100644 index c9cfe90a2947..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +++ /dev/null @@ -1,1404 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include "atom-types.h" -#include "atombios.h" -#include "processpptables.h" -#include "cgs_common.h" -#include "smumgr.h" -#include "hwmgr.h" -#include "hardwaremanager.h" -#include "rv_ppsmc.h" -#include "smu10_hwmgr.h" -#include "power_state.h" -#include "soc15_common.h" -#include "smu10.h" -#include "asic_reg/pwr/pwr_10_0_offset.h" -#include "asic_reg/pwr/pwr_10_0_sh_mask.h" - -#define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5 -#define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */ -#define SCLK_MIN_DIV_INTV_SHIFT 12 -#define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */ -#define SMC_RAM_END 0x40000 - -static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic; - - -static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, - struct pp_display_clock_request *clock_req) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - enum amd_pp_clock_type clk_type = clock_req->clock_type; - uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; - PPSMC_Msg msg; - - switch (clk_type) { - case amd_pp_dcf_clock: - if (clk_freq == smu10_data->dcf_actual_hard_min_freq) - return 0; - msg = PPSMC_MSG_SetHardMinDcefclkByFreq; - smu10_data->dcf_actual_hard_min_freq = clk_freq; - break; - case amd_pp_soc_clock: - msg = PPSMC_MSG_SetHardMinSocclkByFreq; - break; - case amd_pp_f_clock: - if (clk_freq == smu10_data->f_actual_hard_min_freq) - return 0; - smu10_data->f_actual_hard_min_freq = clk_freq; - msg = PPSMC_MSG_SetHardMinFclkByFreq; - break; - default: - pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); - return -EINVAL; - } - smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL); - - return 0; -} - -static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps) -{ - if (SMU10_Magic != hw_ps->magic) - return NULL; - - return (struct smu10_power_state *)hw_ps; -} - -static const struct smu10_power_state *cast_const_smu10_ps( - const struct pp_hw_power_state *hw_ps) -{ - if (SMU10_Magic != hw_ps->magic) - return NULL; - - return (struct smu10_power_state *)hw_ps; -} - -static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - - smu10_data->dce_slow_sclk_threshold = 30000; - smu10_data->thermal_auto_throttling_treshold = 0; - smu10_data->is_nb_dpm_enabled = 1; - smu10_data->dpm_flags = 1; - smu10_data->need_min_deep_sleep_dcefclk = true; - smu10_data->num_active_display = 0; - smu10_data->deep_sleep_dcefclk = 0; - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerPlaySupport); - return 0; -} - -static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, - struct phm_clock_and_voltage_limits *table) -{ - return 0; -} - -static int smu10_init_dynamic_state_adjustment_rule_settings( - struct pp_hwmgr *hwmgr) -{ - struct phm_clock_voltage_dependency_table *table_clk_vlt; - - table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 7), - GFP_KERNEL); - - if (NULL == table_clk_vlt) { - pr_err("Can not allocate memory!\n"); - return -ENOMEM; - } - - table_clk_vlt->count = 8; - table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; - table_clk_vlt->entries[0].v = 0; - table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; - table_clk_vlt->entries[1].v = 1; - table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; - table_clk_vlt->entries[2].v = 2; - table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; - table_clk_vlt->entries[3].v = 3; - table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; - table_clk_vlt->entries[4].v = 4; - table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; - table_clk_vlt->entries[5].v = 5; - table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; - table_clk_vlt->entries[6].v = 6; - table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; - table_clk_vlt->entries[7].v = 7; - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; - - return 0; -} - -static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend; - - smu10_data->sys_info.htc_hyst_lmt = 5; - smu10_data->sys_info.htc_tmp_lmt = 203; - - if (smu10_data->thermal_auto_throttling_treshold == 0) - smu10_data->thermal_auto_throttling_treshold = 203; - - smu10_construct_max_power_limits_table (hwmgr, - &hwmgr->dyn_state.max_clock_voltage_on_ac); - - smu10_init_dynamic_state_adjustment_rule_settings(hwmgr); - - return 0; -} - -static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr) -{ - return 0; -} - -static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) -{ - struct PP_Clocks clocks = {0}; - struct pp_display_clock_request clock_req; - - clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; - clock_req.clock_type = amd_pp_dcf_clock; - clock_req.clock_freq_in_khz = clocks.dcefClock * 10; - - PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), - "Attempt to set DCF Clock Failed!", return -EINVAL); - - return 0; -} - -static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (smu10_data->need_min_deep_sleep_dcefclk && - smu10_data->deep_sleep_dcefclk != clock) { - smu10_data->deep_sleep_dcefclk = clock; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetMinDeepSleepDcefclk, - smu10_data->deep_sleep_dcefclk, - NULL); - } - return 0; -} - -static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (smu10_data->dcf_actual_hard_min_freq && - smu10_data->dcf_actual_hard_min_freq != clock) { - smu10_data->dcf_actual_hard_min_freq = clock; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinDcefclkByFreq, - smu10_data->dcf_actual_hard_min_freq, - NULL); - } - return 0; -} - -static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (smu10_data->f_actual_hard_min_freq && - smu10_data->f_actual_hard_min_freq != clock) { - smu10_data->f_actual_hard_min_freq = clock; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinFclkByFreq, - smu10_data->f_actual_hard_min_freq, - NULL); - } - return 0; -} - -static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (smu10_data->num_active_display != count) { - smu10_data->num_active_display = count; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetDisplayCount, - smu10_data->num_active_display, - NULL); - } - - return 0; -} - -static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) -{ - return smu10_set_clock_limit(hwmgr, input); -} - -static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - struct amdgpu_device *adev = hwmgr->adev; - - smu10_data->vcn_power_gated = true; - smu10_data->isp_tileA_power_gated = true; - smu10_data->isp_tileB_power_gated = true; - - if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetGfxCGPG, - true, - NULL); - else - return 0; -} - - -static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr) -{ - return smu10_init_power_gate_state(hwmgr); -} - -static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - - smu10_data->separation_time = 0; - smu10_data->cc6_disable = false; - smu10_data->pstate_disable = false; - smu10_data->cc6_setting_changed = false; - - return 0; -} - -static int smu10_power_off_asic(struct pp_hwmgr *hwmgr) -{ - return smu10_reset_cc6_data(hwmgr); -} - -static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr) -{ - uint32_t reg; - struct amdgpu_device *adev = hwmgr->adev; - - reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); - if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) == - (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT)) - return true; - - return false; -} - -static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - if (adev->pm.pp_feature & PP_GFXOFF_MASK) { - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL); - - /* confirm gfx is back to "on" state */ - while (!smu10_is_gfx_on(hwmgr)) - msleep(1); - } - - return 0; -} - -static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - return 0; -} - -static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - if (adev->pm.pp_feature & PP_GFXOFF_MASK) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL); - - return 0; -} - -static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - return 0; -} - -static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) -{ - if (enable) - return smu10_enable_gfx_off(hwmgr); - else - return smu10_disable_gfx_off(hwmgr); -} - -static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, - struct pp_power_state *prequest_ps, - const struct pp_power_state *pcurrent_ps) -{ - return 0; -} - -/* temporary hardcoded clock voltage breakdown tables */ -static const DpmClock_t VddDcfClk[]= { - { 300, 2600}, - { 600, 3200}, - { 600, 3600}, -}; - -static const DpmClock_t VddSocClk[]= { - { 478, 2600}, - { 722, 3200}, - { 722, 3600}, -}; - -static const DpmClock_t VddFClk[]= { - { 400, 2600}, - {1200, 3200}, - {1200, 3600}, -}; - -static const DpmClock_t VddDispClk[]= { - { 435, 2600}, - { 661, 3200}, - {1086, 3600}, -}; - -static const DpmClock_t VddDppClk[]= { - { 435, 2600}, - { 661, 3200}, - { 661, 3600}, -}; - -static const DpmClock_t VddPhyClk[]= { - { 540, 2600}, - { 810, 3200}, - { 810, 3600}, -}; - -static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, - struct smu10_voltage_dependency_table **pptable, - uint32_t num_entry, const DpmClock_t *pclk_dependency_table) -{ - uint32_t i; - struct smu10_voltage_dependency_table *ptable; - - ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL); - if (NULL == ptable) - return -ENOMEM; - - ptable->count = num_entry; - - for (i = 0; i < ptable->count; i++) { - ptable->entries[i].clk = pclk_dependency_table->Freq * 100; - ptable->entries[i].vol = pclk_dependency_table->Vol; - pclk_dependency_table++; - } - - *pptable = ptable; - - return 0; -} - - -static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr) -{ - uint32_t result; - - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - DpmClocks_t *table = &(smu10_data->clock_table); - struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); - - result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true); - - PP_ASSERT_WITH_CODE((0 == result), - "Attempt to copy clock table from smc failed", - return result); - - if (0 == result && table->DcefClocks[0].Freq != 0) { - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, - NUM_DCEFCLK_DPM_LEVELS, - &smu10_data->clock_table.DcefClocks[0]); - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, - NUM_SOCCLK_DPM_LEVELS, - &smu10_data->clock_table.SocClocks[0]); - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, - NUM_FCLK_DPM_LEVELS, - &smu10_data->clock_table.FClocks[0]); - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk, - NUM_MEMCLK_DPM_LEVELS, - &smu10_data->clock_table.MemClocks[0]); - } else { - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, - ARRAY_SIZE(VddDcfClk), - &VddDcfClk[0]); - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, - ARRAY_SIZE(VddSocClk), - &VddSocClk[0]); - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, - ARRAY_SIZE(VddFClk), - &VddFClk[0]); - } - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk, - ARRAY_SIZE(VddDispClk), - &VddDispClk[0]); - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk, - ARRAY_SIZE(VddDppClk), &VddDppClk[0]); - smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk, - ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]); - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result); - smu10_data->gfx_min_freq_limit = result / 10 * 1000; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result); - smu10_data->gfx_max_freq_limit = result / 10 * 1000; - - return 0; -} - -static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) -{ - int result = 0; - struct smu10_hwmgr *data; - - data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - - hwmgr->backend = data; - - result = smu10_initialize_dpm_defaults(hwmgr); - if (result != 0) { - pr_err("smu10_initialize_dpm_defaults failed\n"); - return result; - } - - smu10_populate_clock_table(hwmgr); - - result = smu10_get_system_info_data(hwmgr); - if (result != 0) { - pr_err("smu10_get_system_info_data failed\n"); - return result; - } - - smu10_construct_boot_state(hwmgr); - - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = - SMU10_MAX_HARDWARE_POWERLEVELS; - - hwmgr->platform_descriptor.hardwarePerformanceLevels = - SMU10_MAX_HARDWARE_POWERLEVELS; - - hwmgr->platform_descriptor.vbiosInterruptId = 0; - - hwmgr->platform_descriptor.clockStep.engineClock = 500; - - hwmgr->platform_descriptor.clockStep.memoryClock = 500; - - hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - - hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100; - hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100; - - return result; -} - -static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); - - kfree(pinfo->vdd_dep_on_dcefclk); - pinfo->vdd_dep_on_dcefclk = NULL; - kfree(pinfo->vdd_dep_on_socclk); - pinfo->vdd_dep_on_socclk = NULL; - kfree(pinfo->vdd_dep_on_fclk); - pinfo->vdd_dep_on_fclk = NULL; - kfree(pinfo->vdd_dep_on_dispclk); - pinfo->vdd_dep_on_dispclk = NULL; - kfree(pinfo->vdd_dep_on_dppclk); - pinfo->vdd_dep_on_dppclk = NULL; - kfree(pinfo->vdd_dep_on_phyclk); - pinfo->vdd_dep_on_phyclk = NULL; - - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - - kfree(hwmgr->backend); - hwmgr->backend = NULL; - - return 0; -} - -static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, - enum amd_dpm_forced_level level) -{ - struct smu10_hwmgr *data = hwmgr->backend; - uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; - uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; - - if (hwmgr->smu_version < 0x1E3700) { - pr_info("smu firmware version too old, can not set dpm level\n"); - return 0; - } - - if (min_sclk < data->gfx_min_freq_limit) - min_sclk = data->gfx_min_freq_limit; - - min_sclk /= 100; /* transfer 10KHz to MHz */ - if (min_mclk < data->clock_table.FClocks[0].Freq) - min_mclk = data->clock_table.FClocks[0].Freq; - - switch (level) { - case AMD_DPM_FORCED_LEVEL_HIGH: - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - data->gfx_max_freq_limit/100, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinFclkByFreq, - SMU10_UMD_PSTATE_PEAK_FCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinSocclkByFreq, - SMU10_UMD_PSTATE_PEAK_SOCCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinVcn, - SMU10_UMD_PSTATE_VCE, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - data->gfx_max_freq_limit/100, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxFclkByFreq, - SMU10_UMD_PSTATE_PEAK_FCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxSocclkByFreq, - SMU10_UMD_PSTATE_PEAK_SOCCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxVcn, - SMU10_UMD_PSTATE_VCE, - NULL); - break; - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - min_sclk, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - min_sclk, - NULL); - break; - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinFclkByFreq, - min_mclk, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxFclkByFreq, - min_mclk, - NULL); - break; - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - SMU10_UMD_PSTATE_GFXCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinFclkByFreq, - SMU10_UMD_PSTATE_FCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinSocclkByFreq, - SMU10_UMD_PSTATE_SOCCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinVcn, - SMU10_UMD_PSTATE_VCE, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - SMU10_UMD_PSTATE_GFXCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxFclkByFreq, - SMU10_UMD_PSTATE_FCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxSocclkByFreq, - SMU10_UMD_PSTATE_SOCCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxVcn, - SMU10_UMD_PSTATE_VCE, - NULL); - break; - case AMD_DPM_FORCED_LEVEL_AUTO: - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - min_sclk, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinFclkByFreq, - hwmgr->display_config->num_display > 3 ? - SMU10_UMD_PSTATE_PEAK_FCLK : - min_mclk, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinSocclkByFreq, - SMU10_UMD_PSTATE_MIN_SOCCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinVcn, - SMU10_UMD_PSTATE_MIN_VCE, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - data->gfx_max_freq_limit/100, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxFclkByFreq, - SMU10_UMD_PSTATE_PEAK_FCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxSocclkByFreq, - SMU10_UMD_PSTATE_PEAK_SOCCLK, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxVcn, - SMU10_UMD_PSTATE_VCE, - NULL); - break; - case AMD_DPM_FORCED_LEVEL_LOW: - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - data->gfx_min_freq_limit/100, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - data->gfx_min_freq_limit/100, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinFclkByFreq, - min_mclk, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxFclkByFreq, - min_mclk, - NULL); - break; - case AMD_DPM_FORCED_LEVEL_MANUAL: - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: - default: - break; - } - return 0; -} - -static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct smu10_hwmgr *data; - - if (hwmgr == NULL) - return -EINVAL; - - data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (low) - return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; - else - return data->clock_vol_info.vdd_dep_on_fclk->entries[ - data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; -} - -static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct smu10_hwmgr *data; - - if (hwmgr == NULL) - return -EINVAL; - - data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (low) - return data->gfx_min_freq_limit; - else - return data->gfx_max_freq_limit; -} - -static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps) -{ - return 0; -} - -static int smu10_dpm_get_pp_table_entry_callback( - struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps, - unsigned int index, - const void *clock_info) -{ - struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps); - - smu10_ps->levels[index].engine_clock = 0; - - smu10_ps->levels[index].vddc_index = 0; - smu10_ps->level = index + 1; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - smu10_ps->levels[index].ds_divider_index = 5; - smu10_ps->levels[index].ss_divider_index = 5; - } - - return 0; -} - -static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) -{ - int result; - unsigned long ret = 0; - - result = pp_tables_get_num_of_entries(hwmgr, &ret); - - return result ? 0 : ret; -} - -static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, - unsigned long entry, struct pp_power_state *ps) -{ - int result; - struct smu10_power_state *smu10_ps; - - ps->hardware.magic = SMU10_Magic; - - smu10_ps = cast_smu10_ps(&(ps->hardware)); - - result = pp_tables_get_entry(hwmgr, entry, ps, - smu10_dpm_get_pp_table_entry_callback); - - smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; - smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; - - return result; -} - -static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr) -{ - return sizeof(struct smu10_power_state); -} - -static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr) -{ - return 0; -} - - -static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, - bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) -{ - struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (separation_time != data->separation_time || - cc6_disable != data->cc6_disable || - pstate_disable != data->pstate_disable) { - data->separation_time = separation_time; - data->cc6_disable = cc6_disable; - data->pstate_disable = pstate_disable; - data->cc6_setting_changed = true; - } - return 0; -} - -static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr, - struct amd_pp_simple_clock_info *info) -{ - return -EINVAL; -} - -static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask) -{ - struct smu10_hwmgr *data = hwmgr->backend; - struct smu10_voltage_dependency_table *mclk_table = - data->clock_vol_info.vdd_dep_on_fclk; - uint32_t low, high; - - low = mask ? (ffs(mask) - 1) : 0; - high = mask ? (fls(mask) - 1) : 0; - - switch (type) { - case PP_SCLK: - if (low > 2 || high > 2) { - pr_info("Currently sclk only support 3 levels on RV\n"); - return -EINVAL; - } - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - low == 2 ? data->gfx_max_freq_limit/100 : - low == 1 ? SMU10_UMD_PSTATE_GFXCLK : - data->gfx_min_freq_limit/100, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - high == 0 ? data->gfx_min_freq_limit/100 : - high == 1 ? SMU10_UMD_PSTATE_GFXCLK : - data->gfx_max_freq_limit/100, - NULL); - break; - - case PP_MCLK: - if (low > mclk_table->count - 1 || high > mclk_table->count - 1) - return -EINVAL; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinFclkByFreq, - mclk_table->entries[low].clk/100, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxFclkByFreq, - mclk_table->entries[high].clk/100, - NULL); - break; - - case PP_PCIE: - default: - break; - } - return 0; -} - -static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) -{ - struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); - struct smu10_voltage_dependency_table *mclk_table = - data->clock_vol_info.vdd_dep_on_fclk; - uint32_t i, now, size = 0; - - switch (type) { - case PP_SCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now); - - /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ - if (now == data->gfx_max_freq_limit/100) - i = 2; - else if (now == data->gfx_min_freq_limit/100) - i = 0; - else - i = 1; - - size += sprintf(buf + size, "0: %uMhz %s\n", - data->gfx_min_freq_limit/100, - i == 0 ? "*" : ""); - size += sprintf(buf + size, "1: %uMhz %s\n", - i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK, - i == 1 ? "*" : ""); - size += sprintf(buf + size, "2: %uMhz %s\n", - data->gfx_max_freq_limit/100, - i == 2 ? "*" : ""); - break; - case PP_MCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now); - - for (i = 0; i < mclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, - mclk_table->entries[i].clk / 100, - ((mclk_table->entries[i].clk / 100) - == now) ? "*" : ""); - break; - default: - break; - } - - return size; -} - -static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, - PHM_PerformanceLevelDesignation designation, uint32_t index, - PHM_PerformanceLevel *level) -{ - struct smu10_hwmgr *data; - - if (level == NULL || hwmgr == NULL || state == NULL) - return -EINVAL; - - data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (index == 0) { - level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; - level->coreClock = data->gfx_min_freq_limit; - } else { - level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ - data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; - level->coreClock = data->gfx_max_freq_limit; - } - - level->nonLocalMemoryFreq = 0; - level->nonLocalMemoryWidth = 0; - - return 0; -} - -static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, - const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) -{ - const struct smu10_power_state *ps = cast_const_smu10_ps(state); - - clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); - clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index)); - - return 0; -} - -#define MEM_FREQ_LOW_LATENCY 25000 -#define MEM_FREQ_HIGH_LATENCY 80000 -#define MEM_LATENCY_HIGH 245 -#define MEM_LATENCY_LOW 35 -#define MEM_LATENCY_ERR 0xFFFF - - -static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr, - uint32_t clock) -{ - if (clock >= MEM_FREQ_LOW_LATENCY && - clock < MEM_FREQ_HIGH_LATENCY) - return MEM_LATENCY_HIGH; - else if (clock >= MEM_FREQ_HIGH_LATENCY) - return MEM_LATENCY_LOW; - else - return MEM_LATENCY_ERR; -} - -static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks) -{ - uint32_t i; - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); - struct smu10_voltage_dependency_table *pclk_vol_table; - bool latency_required = false; - - if (pinfo == NULL) - return -EINVAL; - - switch (type) { - case amd_pp_mem_clock: - pclk_vol_table = pinfo->vdd_dep_on_mclk; - latency_required = true; - break; - case amd_pp_f_clock: - pclk_vol_table = pinfo->vdd_dep_on_fclk; - latency_required = true; - break; - case amd_pp_dcf_clock: - pclk_vol_table = pinfo->vdd_dep_on_dcefclk; - break; - case amd_pp_disp_clock: - pclk_vol_table = pinfo->vdd_dep_on_dispclk; - break; - case amd_pp_phy_clock: - pclk_vol_table = pinfo->vdd_dep_on_phyclk; - break; - case amd_pp_dpp_clock: - pclk_vol_table = pinfo->vdd_dep_on_dppclk; - break; - default: - return -EINVAL; - } - - if (pclk_vol_table == NULL || pclk_vol_table->count == 0) - return -EINVAL; - - clocks->num_levels = 0; - for (i = 0; i < pclk_vol_table->count; i++) { - if (pclk_vol_table->entries[i].clk) { - clocks->data[clocks->num_levels].clocks_in_khz = - pclk_vol_table->entries[i].clk * 10; - clocks->data[clocks->num_levels].latency_in_us = latency_required ? - smu10_get_mem_latency(hwmgr, - pclk_vol_table->entries[i].clk) : - 0; - clocks->num_levels++; - } - } - - return 0; -} - -static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks) -{ - uint32_t i; - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); - struct smu10_voltage_dependency_table *pclk_vol_table = NULL; - - if (pinfo == NULL) - return -EINVAL; - - switch (type) { - case amd_pp_mem_clock: - pclk_vol_table = pinfo->vdd_dep_on_mclk; - break; - case amd_pp_f_clock: - pclk_vol_table = pinfo->vdd_dep_on_fclk; - break; - case amd_pp_dcf_clock: - pclk_vol_table = pinfo->vdd_dep_on_dcefclk; - break; - case amd_pp_soc_clock: - pclk_vol_table = pinfo->vdd_dep_on_socclk; - break; - case amd_pp_disp_clock: - pclk_vol_table = pinfo->vdd_dep_on_dispclk; - break; - case amd_pp_phy_clock: - pclk_vol_table = pinfo->vdd_dep_on_phyclk; - break; - default: - return -EINVAL; - } - - if (pclk_vol_table == NULL || pclk_vol_table->count == 0) - return -EINVAL; - - clocks->num_levels = 0; - for (i = 0; i < pclk_vol_table->count; i++) { - if (pclk_vol_table->entries[i].clk) { - clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; - clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; - clocks->num_levels++; - } - } - - return 0; -} - - - -static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) -{ - clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */ - return 0; -} - -static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); - int cur_temp = - (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT; - - if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK) - cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - else - cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return cur_temp; -} - -static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, - void *value, int *size) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - uint32_t sclk, mclk; - int ret = 0; - - switch (idx) { - case AMDGPU_PP_SENSOR_GFX_SCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk); - /* in units of 10KHZ */ - *((uint32_t *)value) = sclk * 100; - *size = 4; - break; - case AMDGPU_PP_SENSOR_GFX_MCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk); - /* in units of 10KHZ */ - *((uint32_t *)value) = mclk * 100; - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_TEMP: - *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr); - break; - case AMDGPU_PP_SENSOR_VCN_POWER_STATE: - *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; - *size = 4; - break; - default: - ret = -EINVAL; - break; - } - - return ret; -} - -static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, - void *clock_ranges) -{ - struct smu10_hwmgr *data = hwmgr->backend; - struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; - Watermarks_t *table = &(data->water_marks_table); - - smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges); - smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false); - data->water_marks_exist = true; - return 0; -} - -static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr) -{ - - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL); -} - -static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr) -{ - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL); -} - -static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate) -{ - if (gate) - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL); - else - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL); -} - -static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - - if (bgate) { - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCN, - AMD_PG_STATE_GATE); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_PowerDownVcn, 0, NULL); - smu10_data->vcn_power_gated = true; - } else { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_PowerUpVcn, 0, NULL); - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCN, - AMD_PG_STATE_UNGATE); - smu10_data->vcn_power_gated = false; - } -} - -static int conv_power_profile_to_pplib_workload(int power_profile) -{ - int pplib_workload = 0; - - switch (power_profile) { - case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT: - pplib_workload = WORKLOAD_DEFAULT_BIT; - break; - case PP_SMC_POWER_PROFILE_FULLSCREEN3D: - pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; - break; - case PP_SMC_POWER_PROFILE_POWERSAVING: - pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; - break; - case PP_SMC_POWER_PROFILE_VIDEO: - pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; - break; - case PP_SMC_POWER_PROFILE_VR: - pplib_workload = WORKLOAD_PPLIB_VR_BIT; - break; - case PP_SMC_POWER_PROFILE_COMPUTE: - pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; - break; - } - - return pplib_workload; -} - -static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) -{ - uint32_t i, size = 0; - static const uint8_t - profile_mode_setting[6][4] = {{70, 60, 0, 0,}, - {70, 60, 1, 3,}, - {90, 60, 0, 0,}, - {70, 60, 0, 0,}, - {70, 90, 0, 0,}, - {30, 60, 0, 6,}, - }; - static const char *profile_name[6] = { - "BOOTUP_DEFAULT", - "3D_FULL_SCREEN", - "POWER_SAVING", - "VIDEO", - "VR", - "COMPUTE"}; - static const char *title[6] = {"NUM", - "MODE_NAME", - "BUSY_SET_POINT", - "FPS", - "USE_RLC_BUSY", - "MIN_ACTIVE_LEVEL"}; - - if (!buf) - return -EINVAL; - - size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0], - title[1], title[2], title[3], title[4], title[5]); - - for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++) - size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", - i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", - profile_mode_setting[i][0], profile_mode_setting[i][1], - profile_mode_setting[i][2], profile_mode_setting[i][3]); - - return size; -} - -static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - if ((adev->apu_flags & AMD_APU_IS_RAVEN) && - (hwmgr->smu_version >= 0x41e2b)) - return true; - else - return false; -} - -static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) -{ - int workload_type = 0; - int result = 0; - - if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) { - pr_err("Invalid power profile mode %ld\n", input[size]); - return -EINVAL; - } - if (hwmgr->power_profile_mode == input[size]) - return 0; - - /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ - workload_type = - conv_power_profile_to_pplib_workload(input[size]); - if (workload_type && - smu10_is_raven1_refresh(hwmgr) && - !hwmgr->gfxoff_state_changed_by_workload) { - smu10_gfx_off_control(hwmgr, false); - hwmgr->gfxoff_state_changed_by_workload = true; - } - result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify, - 1 << workload_type, - NULL); - if (!result) - hwmgr->power_profile_mode = input[size]; - if (workload_type && hwmgr->gfxoff_state_changed_by_workload) { - smu10_gfx_off_control(hwmgr, true); - hwmgr->gfxoff_state_changed_by_workload = false; - } - - return 0; -} - -static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode) -{ - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DeviceDriverReset, - mode, - NULL); -} - -static const struct pp_hwmgr_func smu10_hwmgr_funcs = { - .backend_init = smu10_hwmgr_backend_init, - .backend_fini = smu10_hwmgr_backend_fini, - .apply_state_adjust_rules = smu10_apply_state_adjust_rules, - .force_dpm_level = smu10_dpm_force_dpm_level, - .get_power_state_size = smu10_get_power_state_size, - .powerdown_uvd = NULL, - .powergate_uvd = smu10_powergate_vcn, - .powergate_vce = NULL, - .get_mclk = smu10_dpm_get_mclk, - .get_sclk = smu10_dpm_get_sclk, - .patch_boot_state = smu10_dpm_patch_boot_state, - .get_pp_table_entry = smu10_dpm_get_pp_table_entry, - .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries, - .set_cpu_power_state = smu10_set_cpu_power_state, - .store_cc6_data = smu10_store_cc6_data, - .force_clock_level = smu10_force_clock_level, - .print_clock_levels = smu10_print_clock_levels, - .get_dal_power_level = smu10_get_dal_power_level, - .get_performance_level = smu10_get_performance_level, - .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks, - .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency, - .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage, - .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges, - .get_max_high_clocks = smu10_get_max_high_clocks, - .read_sensor = smu10_read_sensor, - .set_active_display_count = smu10_set_active_display_count, - .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk, - .dynamic_state_management_enable = smu10_enable_dpm_tasks, - .power_off_asic = smu10_power_off_asic, - .asic_setup = smu10_setup_asic_task, - .power_state_set = smu10_set_power_state_tasks, - .dynamic_state_management_disable = smu10_disable_dpm_tasks, - .powergate_mmhub = smu10_powergate_mmhub, - .smus_notify_pwe = smu10_smus_notify_pwe, - .display_clock_voltage_request = smu10_display_clock_voltage_request, - .powergate_gfx = smu10_gfx_off_control, - .powergate_sdma = smu10_powergate_sdma, - .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq, - .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq, - .get_power_profile_mode = smu10_get_power_profile_mode, - .set_power_profile_mode = smu10_set_power_profile_mode, - .asic_reset = smu10_asic_reset, -}; - -int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) -{ - hwmgr->hwmgr_func = &smu10_hwmgr_funcs; - hwmgr->pptable_func = &pptable_funcs; - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h deleted file mode 100644 index 0f969de10fab..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef SMU10_HWMGR_H -#define SMU10_HWMGR_H - -#include "hwmgr.h" -#include "smu10_inc.h" -#include "smu10_driver_if.h" -#include "rv_ppsmc.h" - - -#define SMU10_MAX_HARDWARE_POWERLEVELS 8 -#define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15 - -#define DPMFlags_SCLK_Enabled 0x00000001 -#define DPMFlags_UVD_Enabled 0x00000002 -#define DPMFlags_VCE_Enabled 0x00000004 -#define DPMFlags_ACP_Enabled 0x00000008 -#define DPMFlags_ForceHighestValid 0x40000000 - -/* Do not change the following, it is also defined in SMU8.h */ -#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 -#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000 -#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x01000000 -#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x02000000 - -#define SMU_PHYID_SHIFT 8 - -#define SMU10_PCIE_POWERGATING_TARGET_GFX 0 -#define SMU10_PCIE_POWERGATING_TARGET_DDI 1 -#define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE 2 -#define SMU10_PCIE_POWERGATING_TARGET_PHY 3 - -enum VQ_TYPE { - CLOCK_TYPE_DCLK = 0L, - CLOCK_TYPE_ECLK, - CLOCK_TYPE_SCLK, - CLOCK_TYPE_CCLK, - VQ_GFX_CU -}; - -#define SUSTAINABLE_SCLK_MASK 0x00ffffff -#define SUSTAINABLE_SCLK_SHIFT 0 -#define SUSTAINABLE_CU_MASK 0xff000000 -#define SUSTAINABLE_CU_SHIFT 24 - -struct smu10_dpm_entry { - uint32_t soft_min_clk; - uint32_t hard_min_clk; - uint32_t soft_max_clk; - uint32_t hard_max_clk; -}; - -struct smu10_power_level { - uint32_t engine_clock; - uint8_t vddc_index; - uint8_t ds_divider_index; - uint8_t ss_divider_index; - uint8_t allow_gnb_slow; - uint8_t force_nbp_state; - uint8_t display_wm; - uint8_t vce_wm; - uint8_t num_simd_to_powerdown; - uint8_t hysteresis_up; - uint8_t rsv[3]; -}; - -/*used for the nbpsFlags field in smu10_power state*/ -#define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0) -#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1) -#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2) - -#define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0) - -struct smu10_uvd_clocks { - uint32_t vclk; - uint32_t dclk; - uint32_t vclk_low_divider; - uint32_t vclk_high_divider; - uint32_t dclk_low_divider; - uint32_t dclk_high_divider; -}; - -struct pp_disable_nbpslo_flags { - union { - struct { - uint32_t entry : 1; - uint32_t display : 1; - uint32_t driver: 1; - uint32_t vce : 1; - uint32_t uvd : 1; - uint32_t acp : 1; - uint32_t reserved: 26; - } bits; - uint32_t u32All; - }; -}; - - -enum smu10_pstate_previous_action { - DO_NOTHING = 1, - FORCE_HIGH, - CANCEL_FORCE_HIGH -}; - -struct smu10_power_state { - unsigned int magic; - uint32_t level; - struct smu10_uvd_clocks uvd_clocks; - uint32_t evclk; - uint32_t ecclk; - uint32_t samclk; - uint32_t acpclk; - bool need_dfs_bypass; - - uint32_t nbps_flags; - uint32_t bapm_flags; - uint8_t dpm0_pg_nbps_low; - uint8_t dpm0_pg_nbps_high; - uint8_t dpm_x_nbps_low; - uint8_t dpm_x_nbps_high; - - enum smu10_pstate_previous_action action; - - struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS]; - struct pp_disable_nbpslo_flags nbpslo_flags; -}; - -#define SMU10_NUM_NBPSTATES 4 -#define SMU10_NUM_NBPMEMORYCLOCK 2 - - -struct smu10_display_phy_info_entry { - uint8_t phy_present; - uint8_t active_lane_mapping; - uint8_t display_config_type; - uint8_t active_num_of_lanes; -}; - -#define SMU10_MAX_DISPLAYPHY_IDS 10 - -struct smu10_display_phy_info { - bool display_phy_access_initialized; - struct smu10_display_phy_info_entry entries[SMU10_MAX_DISPLAYPHY_IDS]; -}; - -#define MAX_DISPLAY_CLOCK_LEVEL 8 - -struct smu10_system_info{ - uint8_t htc_tmp_lmt; - uint8_t htc_hyst_lmt; -}; - -#define MAX_REGULAR_DPM_NUMBER 8 - -struct smu10_mclk_latency_entries { - uint32_t frequency; - uint32_t latency; -}; - -struct smu10_mclk_latency_table { - uint32_t count; - struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct smu10_clock_voltage_dependency_record { - uint32_t clk; - uint32_t vol; -}; - - -struct smu10_voltage_dependency_table { - uint32_t count; - struct smu10_clock_voltage_dependency_record entries[]; -}; - -struct smu10_clock_voltage_information { - struct smu10_voltage_dependency_table *vdd_dep_on_dcefclk; - struct smu10_voltage_dependency_table *vdd_dep_on_socclk; - struct smu10_voltage_dependency_table *vdd_dep_on_fclk; - struct smu10_voltage_dependency_table *vdd_dep_on_mclk; - struct smu10_voltage_dependency_table *vdd_dep_on_dispclk; - struct smu10_voltage_dependency_table *vdd_dep_on_dppclk; - struct smu10_voltage_dependency_table *vdd_dep_on_phyclk; -}; - -struct smu10_hwmgr { - uint32_t disable_driver_thermal_policy; - uint32_t thermal_auto_throttling_treshold; - struct smu10_system_info sys_info; - struct smu10_mclk_latency_table mclk_latency_table; - - uint32_t ddi_power_gating_disabled; - - struct smu10_display_phy_info_entry display_phy_info; - uint32_t dce_slow_sclk_threshold; - - bool disp_clk_bypass; - bool disp_clk_bypass_pending; - uint32_t bapm_enabled; - - bool video_start; - bool battery_state; - - uint32_t is_nb_dpm_enabled; - uint32_t is_voltage_island_enabled; - uint32_t disable_smu_acp_s3_handshake; - uint32_t disable_notify_smu_vpu_recovery; - bool in_vpu_recovery; - bool pg_acp_init; - uint8_t disp_config; - - /* PowerTune */ - uint32_t power_containment_features; - bool cac_enabled; - bool disable_uvd_power_tune_feature; - bool enable_bapm_feature; - bool enable_tdc_limit_feature; - - - /* SMC SRAM Address of firmware header tables */ - uint32_t sram_end; - uint32_t dpm_table_start; - uint32_t soft_regs_start; - - /* start of SMU7_Fusion_DpmTable */ - - uint8_t uvd_level_count; - uint8_t vce_level_count; - uint8_t acp_level_count; - uint8_t samu_level_count; - - uint32_t fps_high_threshold; - uint32_t fps_low_threshold; - - uint32_t dpm_flags; - struct smu10_dpm_entry sclk_dpm; - struct smu10_dpm_entry uvd_dpm; - struct smu10_dpm_entry vce_dpm; - struct smu10_dpm_entry acp_dpm; - bool acp_power_up_no_dsp; - - uint32_t max_sclk_level; - uint32_t num_of_clk_entries; - - /* CPU Power State */ - uint32_t separation_time; - bool cc6_disable; - bool pstate_disable; - bool cc6_setting_changed; - - uint32_t ulTotalActiveCUs; - - bool isp_tileA_power_gated; - bool isp_tileB_power_gated; - uint32_t isp_actual_hard_min_freq; - uint32_t soc_actual_hard_min_freq; - uint32_t dcf_actual_hard_min_freq; - - uint32_t f_actual_hard_min_freq; - uint32_t fabric_actual_soft_min_freq; - uint32_t vclk_soft_min; - uint32_t dclk_soft_min; - uint32_t gfx_actual_soft_min_freq; - uint32_t gfx_min_freq_limit; - uint32_t gfx_max_freq_limit; - - bool vcn_power_gated; - bool vcn_dpg_mode; - - bool gfx_off_controled_by_driver; - bool water_marks_exist; - Watermarks_t water_marks_table; - struct smu10_clock_voltage_information clock_vol_info; - DpmClocks_t clock_table; - - uint32_t active_process_mask; - bool need_min_deep_sleep_dcefclk; - uint32_t deep_sleep_dcefclk; - uint32_t num_active_display; -}; - -struct pp_hwmgr; - -int smu10_init_function_pointers(struct pp_hwmgr *hwmgr); - -/* UMD PState SMU10 Msg Parameters in MHz */ -#define SMU10_UMD_PSTATE_GFXCLK 700 -#define SMU10_UMD_PSTATE_SOCCLK 626 -#define SMU10_UMD_PSTATE_FCLK 933 -#define SMU10_UMD_PSTATE_VCE 0x03C00320 - -#define SMU10_UMD_PSTATE_PEAK_SOCCLK 757 -#define SMU10_UMD_PSTATE_PEAK_FCLK 1200 - -#define SMU10_UMD_PSTATE_MIN_FCLK 400 -#define SMU10_UMD_PSTATE_MIN_SOCCLK 200 -#define SMU10_UMD_PSTATE_MIN_VCE 0x0190012C - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_inc.h deleted file mode 100644 index edb68e302f6f..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_inc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef SMU10_INC_H -#define SMU10_INC_H - - -#include "asic_reg/mp/mp_10_0_default.h" -#include "asic_reg/mp/mp_10_0_offset.h" -#include "asic_reg/mp/mp_10_0_sh_mask.h" - -#include "asic_reg/nbio/nbio_7_0_default.h" -#include "asic_reg/nbio/nbio_7_0_offset.h" -#include "asic_reg/nbio/nbio_7_0_sh_mask.h" - -#include "asic_reg/thm/thm_10_0_default.h" -#include "asic_reg/thm/thm_10_0_offset.h" -#include "asic_reg/thm/thm_10_0_sh_mask.h" - - -#define ixDDI_PHY_GEN_STATUS 0x3FCE8 - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c deleted file mode 100644 index 044cda005aed..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "smu7_baco.h" -#include "tonga_baco.h" -#include "fiji_baco.h" -#include "polaris_baco.h" -#include "ci_baco.h" - -#include "bif/bif_5_0_d.h" -#include "bif/bif_5_0_sh_mask.h" - -#include "smu/smu_7_1_2_d.h" -#include "smu/smu_7_1_2_sh_mask.h" - -int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - uint32_t reg; - - *cap = false; - if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) - return 0; - - reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); - - if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) - *cap = true; - - return 0; -} - -int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - uint32_t reg; - - reg = RREG32(mmBACO_CNTL); - - if (reg & BACO_CNTL__BACO_MODE_MASK) - /* gfx has already entered BACO state */ - *state = BACO_STATE_IN; - else - *state = BACO_STATE_OUT; - return 0; -} - -int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - - switch (adev->asic_type) { - case CHIP_TOPAZ: - case CHIP_TONGA: - return tonga_baco_set_state(hwmgr, state); - case CHIP_FIJI: - return fiji_baco_set_state(hwmgr, state); - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_POLARIS12: - case CHIP_VEGAM: - return polaris_baco_set_state(hwmgr, state); -#ifdef CONFIG_DRM_AMDGPU_CIK - case CHIP_BONAIRE: - case CHIP_HAWAII: - return ci_baco_set_state(hwmgr, state); -#endif - default: - return -EINVAL; - } -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h deleted file mode 100644 index be0d98abb536..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __SMU7_BACO_H__ -#define __SMU7_BACO_H__ -#include "hwmgr.h" -#include "common_baco.h" - -extern int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); -extern int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); -extern int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c deleted file mode 100644 index f2bda3bcbbde..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "smu7_hwmgr.h" -#include "smu7_clockpowergating.h" -#include "smu7_common.h" - -static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - return smum_send_msg_to_smc(hwmgr, enable ? - PPSMC_MSG_UVDDPM_Enable : - PPSMC_MSG_UVDDPM_Disable, - NULL); -} - -static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - return smum_send_msg_to_smc(hwmgr, enable ? - PPSMC_MSG_VCEDPM_Enable : - PPSMC_MSG_VCEDPM_Disable, - NULL); -} - -static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) -{ - if (!bgate) - smum_update_smc_table(hwmgr, SMU_UVD_TABLE); - return smu7_enable_disable_uvd_dpm(hwmgr, !bgate); -} - -static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate) -{ - if (!bgate) - smum_update_smc_table(hwmgr, SMU_VCE_TABLE); - return smu7_enable_disable_vce_dpm(hwmgr, !bgate); -} - -int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_uvd_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_UVDPowerOFF, - NULL); - return 0; -} - -static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_uvd_power_gating(hwmgr)) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDynamicPowerGating)) { - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_UVDPowerON, 1, NULL); - } else { - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_UVDPowerON, 0, NULL); - } - } - - return 0; -} - -static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_vce_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_VCEPowerOFF, - NULL); - return 0; -} - -static int smu7_powerup_vce(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_vce_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_VCEPowerON, - NULL); - return 0; -} - -int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - data->uvd_power_gated = false; - data->vce_power_gated = false; - - smu7_powerup_uvd(hwmgr); - smu7_powerup_vce(hwmgr); - - return 0; -} - -void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - data->uvd_power_gated = bgate; - - if (bgate) { - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_GATE); - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); - smu7_update_uvd_dpm(hwmgr, true); - smu7_powerdown_uvd(hwmgr); - } else { - smu7_powerup_uvd(hwmgr); - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_UNGATE); - smu7_update_uvd_dpm(hwmgr, false); - } - -} - -void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - data->vce_power_gated = bgate; - - if (bgate) { - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_GATE); - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_GATE); - smu7_update_vce_dpm(hwmgr, true); - smu7_powerdown_vce(hwmgr); - } else { - smu7_powerup_vce(hwmgr); - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_UNGATE); - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_UNGATE); - smu7_update_vce_dpm(hwmgr, false); - } -} - -int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, - const uint32_t *msg_id) -{ - PPSMC_Msg msg; - uint32_t value; - - if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU)) - return 0; - - switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) { - case PP_GROUP_GFX: - switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { - case PP_BLOCK_GFX_CG: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_CGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS - ? PPSMC_MSG_EnableClockGatingFeature - : PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_CGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_GFX_3D: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_3DCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_3DLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_GFX_RLC: - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_RLC_LS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_GFX_CP: - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_CP_LS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_GFX_MG: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK | - CG_GFX_OTHERS_MGCG_MASK); - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - default: - return -EINVAL; - } - break; - - case PP_GROUP_SYS: - switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { - case PP_BLOCK_SYS_BIF: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_BIF_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_BIF_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_SYS_MC: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_MC_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_MC_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_SYS_DRM: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_DRM_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_DRM_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_SYS_HDP: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_HDP_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_HDP_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_SYS_SDMA: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_SDMA_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_SDMA_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - case PP_BLOCK_SYS_ROM: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_ROM_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr, msg, value, NULL)) - return -EINVAL; - } - break; - - default: - return -EINVAL; - - } - break; - - default: - return -EINVAL; - - } - - return 0; -} - -/* This function is for Polaris11 only for now, - * Powerplay will only control the static per CU Power Gating. - * Dynamic per CU Power Gating will be done in gfx. - */ -int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable) -{ - struct amdgpu_device *adev = hwmgr->adev; - - if (enable) - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GFX_CU_PG_ENABLE, - adev->gfx.cu_info.number, - NULL); - else - return smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_GFX_CU_PG_DISABLE, - NULL); -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h deleted file mode 100644 index fc8f8a6acc72..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _SMU7_CLOCK_POWER_GATING_H_ -#define _SMU7_CLOCK_POWER_GATING_H_ - -#include "smu7_hwmgr.h" - -void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); -void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); -int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr); -int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate); -int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr); -int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, - const uint32_t *msg_id); -int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h deleted file mode 100644 index 3477d4dfff70..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _SMU7_DYN_DEFAULTS_H -#define _SMU7_DYN_DEFAULTS_H - - -/* We need to fill in the default values */ - - -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 -#define SMU7_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 - - -#define SMU7_THERMALPROTECTCOUNTER_DFLT 0x200 -#define SMU7_STATICSCREENTHRESHOLDUNIT_DFLT 0 -#define SMU7_STATICSCREENTHRESHOLD_DFLT 0x00C8 -#define SMU7_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 -#define SMU7_REFERENCEDIVIDER_DFLT 4 - -#define SMU7_ULVVOLTAGECHANGEDELAY_DFLT 1687 - -#define SMU7_CGULVPARAMETER_DFLT 0x00040035 -#define SMU7_CGULVCONTROL_DFLT 0x00007450 -#define SMU7_TARGETACTIVITY_DFLT 50 -#define SMU7_MCLK_TARGETACTIVITY_DFLT 10 -#define SMU7_SCLK_TARGETACTIVITY_DFLT 30 -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c deleted file mode 100644 index ffe05b7cc1f0..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ /dev/null @@ -1,5215 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/module.h> -#include <linux/pci.h> -#include <linux/slab.h> -#include <asm/div64.h> -#include <drm/amdgpu_drm.h> -#include "ppatomctrl.h" -#include "atombios.h" -#include "pptable_v1_0.h" -#include "pppcielanes.h" -#include "amd_pcie_helpers.h" -#include "hardwaremanager.h" -#include "process_pptables_v1_0.h" -#include "cgs_common.h" - -#include "smu7_common.h" - -#include "hwmgr.h" -#include "smu7_hwmgr.h" -#include "smu_ucode_xfer_vi.h" -#include "smu7_powertune.h" -#include "smu7_dyn_defaults.h" -#include "smu7_thermal.h" -#include "smu7_clockpowergating.h" -#include "processpptables.h" -#include "pp_thermal.h" -#include "smu7_baco.h" - -#include "ivsrcid/ivsrcid_vislands30.h" - -#define MC_CG_ARB_FREQ_F0 0x0a -#define MC_CG_ARB_FREQ_F1 0x0b -#define MC_CG_ARB_FREQ_F2 0x0c -#define MC_CG_ARB_FREQ_F3 0x0d - -#define MC_CG_SEQ_DRAMCONF_S0 0x05 -#define MC_CG_SEQ_DRAMCONF_S1 0x06 -#define MC_CG_SEQ_YCLK_SUSPEND 0x04 -#define MC_CG_SEQ_YCLK_RESUME 0x0a - -#define SMC_CG_IND_START 0xc0030000 -#define SMC_CG_IND_END 0xc0040000 - -#define MEM_FREQ_LOW_LATENCY 25000 -#define MEM_FREQ_HIGH_LATENCY 80000 - -#define MEM_LATENCY_HIGH 45 -#define MEM_LATENCY_LOW 35 -#define MEM_LATENCY_ERR 0xFFFF - -#define MC_SEQ_MISC0_GDDR5_SHIFT 28 -#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 -#define MC_SEQ_MISC0_GDDR5_VALUE 5 - -#define PCIE_BUS_CLK 10000 -#define TCLK (PCIE_BUS_CLK / 10) - -static struct profile_mode_setting smu7_profiling[7] = - {{0, 0, 0, 0, 0, 0, 0, 0}, - {1, 0, 100, 30, 1, 0, 100, 10}, - {1, 10, 0, 30, 0, 0, 0, 0}, - {0, 0, 0, 0, 1, 10, 16, 31}, - {1, 0, 11, 50, 1, 0, 100, 10}, - {1, 0, 5, 30, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - }; - -#define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310) - -#define ixPWR_SVI2_PLANE1_LOAD 0xC0200280 -#define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L -#define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L -#define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005 -#define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006 - -/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ -enum DPM_EVENT_SRC { - DPM_EVENT_SRC_ANALOG = 0, - DPM_EVENT_SRC_EXTERNAL = 1, - DPM_EVENT_SRC_DIGITAL = 2, - DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, - DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 -}; - -static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic); -static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask); - -static struct smu7_power_state *cast_phw_smu7_power_state( - struct pp_hw_power_state *hw_ps) -{ - PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), - "Invalid Powerstate Type!", - return NULL); - - return (struct smu7_power_state *)hw_ps; -} - -static const struct smu7_power_state *cast_const_phw_smu7_power_state( - const struct pp_hw_power_state *hw_ps) -{ - PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), - "Invalid Powerstate Type!", - return NULL); - - return (const struct smu7_power_state *)hw_ps; -} - -/** - * Find the MC microcode version and store it in the HwMgr struct - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) -{ - cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); - - hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); - - return 0; -} - -static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) -{ - uint32_t speedCntl = 0; - - /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ - speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, - ixPCIE_LC_SPEED_CNTL); - return((uint16_t)PHM_GET_FIELD(speedCntl, - PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); -} - -static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) -{ - uint32_t link_width; - - /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ - link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, - PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); - - PP_ASSERT_WITH_CODE((7 >= link_width), - "Invalid PCIe lane width!", return 0); - - return decode_pcie_lane_width(link_width); -} - -/** -* Enable voltage control -* -* @param pHwMgr the address of the powerplay hardware manager. -* @return always PP_Result_OK -*/ -static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->chip_id == CHIP_VEGAM) { - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0); - } - - if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL); - - return 0; -} - -/** -* Checks if we want to support voltage control -* -* @param hwmgr the address of the powerplay hardware manager. -*/ -static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr) -{ - const struct smu7_hwmgr *data = - (const struct smu7_hwmgr *)(hwmgr->backend); - - return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control); -} - -/** -* Enable voltage control -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr) -{ - /* enable voltage control */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); - - return 0; -} - -static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table, - struct phm_clock_voltage_dependency_table *voltage_dependency_table - ) -{ - uint32_t i; - - PP_ASSERT_WITH_CODE((NULL != voltage_table), - "Voltage Dependency Table empty.", return -EINVAL;); - - voltage_table->mask_low = 0; - voltage_table->phase_delay = 0; - voltage_table->count = voltage_dependency_table->count; - - for (i = 0; i < voltage_dependency_table->count; i++) { - voltage_table->entries[i].value = - voltage_dependency_table->entries[i].v; - voltage_table->entries[i].smio_low = 0; - } - - return 0; -} - - -/** -* Create Voltage Tables. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - int result = 0; - uint32_t tmp; - - if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { - result = atomctrl_get_voltage_table_v3(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, - &(data->mvdd_voltage_table)); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve MVDD table.", - return result); - } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { - if (hwmgr->pp_table_version == PP_TABLE_V1) - result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), - table_info->vdd_dep_on_mclk); - else if (hwmgr->pp_table_version == PP_TABLE_V0) - result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table), - hwmgr->dyn_state.mvdd_dependency_on_mclk); - - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve SVI2 MVDD table from dependency table.", - return result;); - } - - if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { - result = atomctrl_get_voltage_table_v3(hwmgr, - VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, - &(data->vddci_voltage_table)); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve VDDCI table.", - return result); - } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { - if (hwmgr->pp_table_version == PP_TABLE_V1) - result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), - table_info->vdd_dep_on_mclk); - else if (hwmgr->pp_table_version == PP_TABLE_V0) - result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table), - hwmgr->dyn_state.vddci_dependency_on_mclk); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve SVI2 VDDCI table from dependency table.", - return result); - } - - if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { - /* VDDGFX has only SVI2 voltage control */ - result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table), - table_info->vddgfx_lookup_table); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); - } - - - if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) { - result = atomctrl_get_voltage_table_v3(hwmgr, - VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT, - &data->vddc_voltage_table); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve VDDC table.", return result;); - } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { - - if (hwmgr->pp_table_version == PP_TABLE_V0) - result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table, - hwmgr->dyn_state.vddc_dependency_on_mclk); - else if (hwmgr->pp_table_version == PP_TABLE_V1) - result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), - table_info->vddc_lookup_table); - - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve SVI2 VDDC table from dependency table.", return result;); - } - - tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC); - PP_ASSERT_WITH_CODE( - (data->vddc_voltage_table.count <= tmp), - "Too many voltage values for VDDC. Trimming to fit state table.", - phm_trim_voltage_table_to_fit_state_table(tmp, - &(data->vddc_voltage_table))); - - tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); - PP_ASSERT_WITH_CODE( - (data->vddgfx_voltage_table.count <= tmp), - "Too many voltage values for VDDC. Trimming to fit state table.", - phm_trim_voltage_table_to_fit_state_table(tmp, - &(data->vddgfx_voltage_table))); - - tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI); - PP_ASSERT_WITH_CODE( - (data->vddci_voltage_table.count <= tmp), - "Too many voltage values for VDDCI. Trimming to fit state table.", - phm_trim_voltage_table_to_fit_state_table(tmp, - &(data->vddci_voltage_table))); - - tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD); - PP_ASSERT_WITH_CODE( - (data->mvdd_voltage_table.count <= tmp), - "Too many voltage values for MVDD. Trimming to fit state table.", - phm_trim_voltage_table_to_fit_state_table(tmp, - &(data->mvdd_voltage_table))); - - return 0; -} - -/** -* Programs static screed detection parameters -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int smu7_program_static_screen_threshold_parameters( - struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /* Set static screen threshold unit */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, - data->static_screen_threshold_unit); - /* Set static screen threshold */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, - data->static_screen_threshold); - - return 0; -} - -/** -* Setup display gap for glitch free memory clock switching. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) -{ - uint32_t display_gap = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_DISPLAY_GAP_CNTL); - - display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, - DISP_GAP, DISPLAY_GAP_IGNORE); - - display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, - DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_DISPLAY_GAP_CNTL, display_gap); - - return 0; -} - -/** -* Programs activity state transition voting clients -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - int i; - - /* Clear reset for voting clients before enabling DPM */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); - - for (i = 0; i < 8; i++) - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0 + i * 4, - data->voting_rights_clients[i]); - return 0; -} - -static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) -{ - int i; - - /* Reset voting clients before disabling DPM */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); - - for (i = 0; i < 8; i++) - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0); - - return 0; -} - -/* Copy one arb setting to another and then switch the active set. - * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. - */ -static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, - uint32_t arb_src, uint32_t arb_dest) -{ - uint32_t mc_arb_dram_timing; - uint32_t mc_arb_dram_timing2; - uint32_t burst_time; - uint32_t mc_cg_config; - - switch (arb_src) { - case MC_CG_ARB_FREQ_F0: - mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); - mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); - burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); - break; - case MC_CG_ARB_FREQ_F1: - mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); - mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); - burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); - break; - default: - return -EINVAL; - } - - switch (arb_dest) { - case MC_CG_ARB_FREQ_F0: - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); - PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); - break; - case MC_CG_ARB_FREQ_F1: - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); - PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); - break; - default: - return -EINVAL; - } - - mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); - mc_cg_config |= 0x0000000F; - cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); - PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); - - return 0; -} - -static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) -{ - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL); -} - -/** -* Initial switch from ARB F0->F1 -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -* This function is to be called from the SetPowerState table. -*/ -static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) -{ - return smu7_copy_and_switch_arb_sets(hwmgr, - MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); -} - -static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) -{ - uint32_t tmp; - - tmp = (cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, ixSMC_SCRATCH9) & - 0x0000ff00) >> 8; - - if (tmp == MC_CG_ARB_FREQ_F0) - return 0; - - return smu7_copy_and_switch_arb_sets(hwmgr, - tmp, MC_CG_ARB_FREQ_F0); -} - -static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_pcie_table *pcie_table = NULL; - - uint32_t i, max_entry; - uint32_t tmp; - - PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || - data->use_pcie_power_saving_levels), "No pcie performance levels!", - return -EINVAL); - - if (table_info != NULL) - pcie_table = table_info->pcie_table; - - if (data->use_pcie_performance_levels && - !data->use_pcie_power_saving_levels) { - data->pcie_gen_power_saving = data->pcie_gen_performance; - data->pcie_lane_power_saving = data->pcie_lane_performance; - } else if (!data->use_pcie_performance_levels && - data->use_pcie_power_saving_levels) { - data->pcie_gen_performance = data->pcie_gen_power_saving; - data->pcie_lane_performance = data->pcie_lane_power_saving; - } - tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK); - phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, - tmp, - MAX_REGULAR_DPM_NUMBER); - - if (pcie_table != NULL) { - /* max_entry is used to make sure we reserve one PCIE level - * for boot level (fix for A+A PSPP issue). - * If PCIE table from PPTable have ULV entry + 8 entries, - * then ignore the last entry.*/ - max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count; - for (i = 1; i < max_entry; i++) { - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, - get_pcie_gen_support(data->pcie_gen_cap, - pcie_table->entries[i].gen_speed), - get_pcie_lane_support(data->pcie_lane_cap, - pcie_table->entries[i].lane_width)); - } - data->dpm_table.pcie_speed_table.count = max_entry - 1; - smum_update_smc_table(hwmgr, SMU_BIF_TABLE); - } else { - /* Hardcode Pcie Table */ - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Min_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Min_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - - data->dpm_table.pcie_speed_table.count = 6; - } - /* Populate last level for boot PCIE level, but do not increment count. */ - if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { - for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - data->vbios_boot_state.pcie_lane_bootup_value); - } else { - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, - data->dpm_table.pcie_speed_table.count, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Min_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - } - return 0; -} - -static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); - - phm_reset_single_dpm_table( - &data->dpm_table.sclk_table, - smum_get_mac_definition(hwmgr, - SMU_MAX_LEVELS_GRAPHICS), - MAX_REGULAR_DPM_NUMBER); - phm_reset_single_dpm_table( - &data->dpm_table.mclk_table, - smum_get_mac_definition(hwmgr, - SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); - - phm_reset_single_dpm_table( - &data->dpm_table.vddc_table, - smum_get_mac_definition(hwmgr, - SMU_MAX_LEVELS_VDDC), - MAX_REGULAR_DPM_NUMBER); - phm_reset_single_dpm_table( - &data->dpm_table.vddci_table, - smum_get_mac_definition(hwmgr, - SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); - - phm_reset_single_dpm_table( - &data->dpm_table.mvdd_table, - smum_get_mac_definition(hwmgr, - SMU_MAX_LEVELS_MVDD), - MAX_REGULAR_DPM_NUMBER); - return 0; -} -/* - * This function is to initialize all DPM state tables - * for SMU7 based on the dependency table. - * Dynamic state patching function will then trim these - * state tables to the allowed range based - * on the power policy or external client requests, - * such as UVD request, etc. - */ - -static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table = - hwmgr->dyn_state.vddc_dependency_on_mclk; - struct phm_cac_leakage_table *std_voltage_table = - hwmgr->dyn_state.cac_leakage_table; - uint32_t i; - - PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, - "SCLK dependency table is missing. This table is mandatory", return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, - "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); - - PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, - "MCLK dependency table is missing. This table is mandatory", return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, - "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); - - - /* Initialize Sclk DPM table based on allow Sclk values*/ - data->dpm_table.sclk_table.count = 0; - - for (i = 0; i < allowed_vdd_sclk_table->count; i++) { - if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != - allowed_vdd_sclk_table->entries[i].clk) { - data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = - allowed_vdd_sclk_table->entries[i].clk; - data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; - data->dpm_table.sclk_table.count++; - } - } - - PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, - "MCLK dependency table is missing. This table is mandatory", return -EINVAL); - /* Initialize Mclk DPM table based on allow Mclk values */ - data->dpm_table.mclk_table.count = 0; - for (i = 0; i < allowed_vdd_mclk_table->count; i++) { - if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != - allowed_vdd_mclk_table->entries[i].clk) { - data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = - allowed_vdd_mclk_table->entries[i].clk; - data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; - data->dpm_table.mclk_table.count++; - } - } - - /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */ - for (i = 0; i < allowed_vdd_sclk_table->count; i++) { - data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; - data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; - /* param1 is for corresponding std voltage */ - data->dpm_table.vddc_table.dpm_levels[i].enabled = true; - } - - data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count; - allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; - - if (NULL != allowed_vdd_mclk_table) { - /* Initialize Vddci DPM table based on allow Mclk values */ - for (i = 0; i < allowed_vdd_mclk_table->count; i++) { - data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; - data->dpm_table.vddci_table.dpm_levels[i].enabled = true; - } - data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count; - } - - allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; - - if (NULL != allowed_vdd_mclk_table) { - /* - * Initialize MVDD DPM table based on allow Mclk - * values - */ - for (i = 0; i < allowed_vdd_mclk_table->count; i++) { - data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; - data->dpm_table.mvdd_table.dpm_levels[i].enabled = true; - } - data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count; - } - - return 0; -} - -static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint32_t i; - - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; - - if (table_info == NULL) - return -EINVAL; - - dep_sclk_table = table_info->vdd_dep_on_sclk; - dep_mclk_table = table_info->vdd_dep_on_mclk; - - PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, - "SCLK dependency table is missing.", - return -EINVAL); - PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, - "SCLK dependency table count is 0.", - return -EINVAL); - - PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, - "MCLK dependency table is missing.", - return -EINVAL); - PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, - "MCLK dependency table count is 0", - return -EINVAL); - - /* Initialize Sclk DPM table based on allow Sclk values */ - data->dpm_table.sclk_table.count = 0; - for (i = 0; i < dep_sclk_table->count; i++) { - if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != - dep_sclk_table->entries[i].clk) { - - data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = - dep_sclk_table->entries[i].clk; - - data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = - (i == 0) ? true : false; - data->dpm_table.sclk_table.count++; - } - } - if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) - hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; - /* Initialize Mclk DPM table based on allow Mclk values */ - data->dpm_table.mclk_table.count = 0; - for (i = 0; i < dep_mclk_table->count; i++) { - if (i == 0 || data->dpm_table.mclk_table.dpm_levels - [data->dpm_table.mclk_table.count - 1].value != - dep_mclk_table->entries[i].clk) { - data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = - dep_mclk_table->entries[i].clk; - data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = - (i == 0) ? true : false; - data->dpm_table.mclk_table.count++; - } - } - - if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) - hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk; - return 0; -} - -static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint32_t i; - - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; - struct phm_odn_performance_level *entries; - - if (table_info == NULL) - return -EINVAL; - - dep_sclk_table = table_info->vdd_dep_on_sclk; - dep_mclk_table = table_info->vdd_dep_on_mclk; - - odn_table->odn_core_clock_dpm_levels.num_of_pl = - data->golden_dpm_table.sclk_table.count; - entries = odn_table->odn_core_clock_dpm_levels.entries; - for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) { - entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value; - entries[i].enabled = true; - entries[i].vddc = dep_sclk_table->entries[i].vddc; - } - - smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table, - (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk)); - - odn_table->odn_memory_clock_dpm_levels.num_of_pl = - data->golden_dpm_table.mclk_table.count; - entries = odn_table->odn_memory_clock_dpm_levels.entries; - for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) { - entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value; - entries[i].enabled = true; - entries[i].vddc = dep_mclk_table->entries[i].vddc; - } - - smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table, - (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk)); - - return 0; -} - -static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint32_t min_vddc = 0; - uint32_t max_vddc = 0; - - if (!table_info) - return; - - dep_sclk_table = table_info->vdd_dep_on_sclk; - - atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc); - - if (min_vddc == 0 || min_vddc > 2000 - || min_vddc > dep_sclk_table->entries[0].vddc) - min_vddc = dep_sclk_table->entries[0].vddc; - - if (max_vddc == 0 || max_vddc > 2000 - || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc) - max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc; - - data->odn_dpm_table.min_vddc = min_vddc; - data->odn_dpm_table.max_vddc = max_vddc; -} - -static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint32_t i; - - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; - struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; - - if (table_info == NULL) - return; - - for (i = 0; i < data->dpm_table.sclk_table.count; i++) { - if (odn_table->odn_core_clock_dpm_levels.entries[i].clock != - data->dpm_table.sclk_table.dpm_levels[i].value) { - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; - break; - } - } - - for (i = 0; i < data->dpm_table.mclk_table.count; i++) { - if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock != - data->dpm_table.mclk_table.dpm_levels[i].value) { - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; - break; - } - } - - dep_table = table_info->vdd_dep_on_mclk; - odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk); - - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; - return; - } - } - - dep_table = table_info->vdd_dep_on_sclk; - odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; - return; - } - } - if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { - data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; - } -} - -static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - smu7_reset_dpm_tables(hwmgr); - - if (hwmgr->pp_table_version == PP_TABLE_V1) - smu7_setup_dpm_tables_v1(hwmgr); - else if (hwmgr->pp_table_version == PP_TABLE_V0) - smu7_setup_dpm_tables_v0(hwmgr); - - smu7_setup_default_pcie_table(hwmgr); - - /* save a copy of the default DPM table */ - memcpy(&(data->golden_dpm_table), &(data->dpm_table), - sizeof(struct smu7_dpm_table)); - - /* initialize ODN table */ - if (hwmgr->od_enabled) { - if (data->odn_dpm_table.max_vddc) { - smu7_check_dpm_table_updated(hwmgr); - } else { - smu7_setup_voltage_range_from_vbios(hwmgr); - smu7_odn_initial_default_setting(hwmgr); - } - } - return 0; -} - -static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) -{ - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot)) - return smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_EnableVRHotGPIOInterrupt, - NULL); - - return 0; -} - -static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr) -{ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, - SCLK_PWRMGT_OFF, 0); - return 0; -} - -static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (data->ulv_supported) - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL); - - return 0; -} - -static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (data->ulv_supported) - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL); - - return 0; -} - -static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep)) { - if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL)) - PP_ASSERT_WITH_CODE(false, - "Attempt to enable Master Deep Sleep switch failed!", - return -EINVAL); - } else { - if (smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_MASTER_DeepSleep_OFF, - NULL)) { - PP_ASSERT_WITH_CODE(false, - "Attempt to disable Master Deep Sleep switch failed!", - return -EINVAL); - } - } - - return 0; -} - -static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep)) { - if (smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_MASTER_DeepSleep_OFF, - NULL)) { - PP_ASSERT_WITH_CODE(false, - "Attempt to disable Master Deep Sleep switch failed!", - return -EINVAL); - } - } - - return 0; -} - -static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t soft_register_value = 0; - uint32_t handshake_disables_offset = data->soft_regs_start - + smum_get_offsetof(hwmgr, - SMU_SoftRegisters, HandshakeDisables); - - soft_register_value = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, handshake_disables_offset); - soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE; - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - handshake_disables_offset, soft_register_value); - return 0; -} - -static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t soft_register_value = 0; - uint32_t handshake_disables_offset = data->soft_regs_start - + smum_get_offsetof(hwmgr, - SMU_SoftRegisters, HandshakeDisables); - - soft_register_value = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, handshake_disables_offset); - soft_register_value |= smum_get_mac_definition(hwmgr, - SMU_UVD_MCLK_HANDSHAKE_DISABLE); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - handshake_disables_offset, soft_register_value); - return 0; -} - -static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /* enable SCLK dpm */ - if (!data->sclk_dpm_key_disabled) { - if (hwmgr->chip_id == CHIP_VEGAM) - smu7_disable_sclk_vce_handshake(hwmgr); - - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)), - "Failed to enable SCLK DPM during DPM Start Function!", - return -EINVAL); - } - - /* enable MCLK dpm */ - if (0 == data->mclk_dpm_key_disabled) { - if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) - smu7_disable_handshake_uvd(hwmgr); - - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_MCLKDPM_Enable, - NULL)), - "Failed to enable MCLK DPM during DPM Start Function!", - return -EINVAL); - - if (hwmgr->chip_family != CHIP_VEGAM) - PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); - - - if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005); - udelay(10); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005); - } else { - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); - udelay(10); - if (hwmgr->chip_id == CHIP_VEGAM) { - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009); - } else { - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); - } - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); - } - } - - return 0; -} - -static int smu7_start_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /*enable general power management */ - - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - GLOBAL_PWRMGT_EN, 1); - - /* enable sclk deep sleep */ - - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, - DYNAMIC_PM_EN, 1); - - /* prepare for PCIE DPM */ - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + - smum_get_offsetof(hwmgr, SMU_SoftRegisters, - VoltageChangeTimeout), 0x1000); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, - SWRST_COMMAND_1, RESETLC, 0x0); - - if (hwmgr->chip_family == AMDGPU_FAMILY_CI) - cgs_write_register(hwmgr->device, 0x1488, - (cgs_read_register(hwmgr->device, 0x1488) & ~0x1)); - - if (smu7_enable_sclk_mclk_dpm(hwmgr)) { - pr_err("Failed to enable Sclk DPM and Mclk DPM!"); - return -EINVAL; - } - - /* enable PCIE dpm */ - if (0 == data->pcie_dpm_key_disabled) { - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_PCIeDPM_Enable, - NULL)), - "Failed to enable pcie DPM during DPM Start Function!", - return -EINVAL); - } - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_Falcon_QuickTransition)) { - PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_EnableACDCGPIOInterrupt, - NULL)), - "Failed to enable AC DC GPIO Interrupt!", - ); - } - - return 0; -} - -static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /* disable SCLK dpm */ - if (!data->sclk_dpm_key_disabled) { - PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), - "Trying to disable SCLK DPM when DPM is disabled", - return 0); - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL); - } - - /* disable MCLK dpm */ - if (!data->mclk_dpm_key_disabled) { - PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), - "Trying to disable MCLK DPM when DPM is disabled", - return 0); - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL); - } - - return 0; -} - -static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /* disable general power management */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - GLOBAL_PWRMGT_EN, 0); - /* disable sclk deep sleep */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, - DYNAMIC_PM_EN, 0); - - /* disable PCIE dpm */ - if (!data->pcie_dpm_key_disabled) { - PP_ASSERT_WITH_CODE( - (smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_PCIeDPM_Disable, - NULL) == 0), - "Failed to disable pcie DPM during DPM Stop Function!", - return -EINVAL); - } - - smu7_disable_sclk_mclk_dpm(hwmgr); - - PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), - "Trying to disable voltage DPM when DPM is disabled", - return 0); - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL); - - return 0; -} - -static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) -{ - bool protection; - enum DPM_EVENT_SRC src; - - switch (sources) { - default: - pr_err("Unknown throttling event sources."); - fallthrough; - case 0: - protection = false; - /* src is unused */ - break; - case (1 << PHM_AutoThrottleSource_Thermal): - protection = true; - src = DPM_EVENT_SRC_DIGITAL; - break; - case (1 << PHM_AutoThrottleSource_External): - protection = true; - src = DPM_EVENT_SRC_EXTERNAL; - break; - case (1 << PHM_AutoThrottleSource_External) | - (1 << PHM_AutoThrottleSource_Thermal): - protection = true; - src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; - break; - } - /* Order matters - don't enable thermal protection for the wrong source. */ - if (protection) { - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, - DPM_EVENT_SRC, src); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - THERMAL_PROTECTION_DIS, - !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)); - } else - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - THERMAL_PROTECTION_DIS, 1); -} - -static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, - PHM_AutoThrottleSource source) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (!(data->active_auto_throttle_sources & (1 << source))) { - data->active_auto_throttle_sources |= 1 << source; - smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); - } - return 0; -} - -static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) -{ - return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); -} - -static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, - PHM_AutoThrottleSource source) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (data->active_auto_throttle_sources & (1 << source)) { - data->active_auto_throttle_sources &= ~(1 << source); - smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); - } - return 0; -} - -static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) -{ - return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); -} - -static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - data->pcie_performance_request = true; - - return 0; -} - -static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int tmp_result = 0; - int result = 0; - - if (smu7_voltage_control(hwmgr)) { - tmp_result = smu7_enable_voltage_control(hwmgr); - PP_ASSERT_WITH_CODE(tmp_result == 0, - "Failed to enable voltage control!", - result = tmp_result); - - tmp_result = smu7_construct_voltage_tables(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to construct voltage tables!", - result = tmp_result); - } - smum_initialize_mc_reg_table(hwmgr); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EngineSpreadSpectrumSupport)) - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); - - tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to program static screen threshold parameters!", - result = tmp_result); - - tmp_result = smu7_enable_display_gap(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable display gap!", result = tmp_result); - - tmp_result = smu7_program_voting_clients(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to program voting clients!", result = tmp_result); - - tmp_result = smum_process_firmware_header(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to process firmware header!", result = tmp_result); - - if (hwmgr->chip_id != CHIP_VEGAM) { - tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to initialize switch from ArbF0 to F1!", - result = tmp_result); - } - - result = smu7_setup_default_dpm_tables(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to setup default DPM tables!", return result); - - tmp_result = smum_init_smc_table(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to initialize SMC table!", result = tmp_result); - - tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable VR hot GPIO interrupt!", result = tmp_result); - - smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL); - - tmp_result = smu7_enable_sclk_control(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable SCLK control!", result = tmp_result); - - tmp_result = smu7_enable_smc_voltage_controller(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable voltage control!", result = tmp_result); - - tmp_result = smu7_enable_ulv(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable ULV!", result = tmp_result); - - tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable deep sleep master switch!", result = tmp_result); - - tmp_result = smu7_enable_didt_config(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to enable deep sleep master switch!", result = tmp_result); - - tmp_result = smu7_start_dpm(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to start DPM!", result = tmp_result); - - tmp_result = smu7_enable_smc_cac(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable SMC CAC!", result = tmp_result); - - tmp_result = smu7_enable_power_containment(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable power containment!", result = tmp_result); - - tmp_result = smu7_power_control_set_level(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to power control set level!", result = tmp_result); - - tmp_result = smu7_enable_thermal_auto_throttle(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable thermal auto throttle!", result = tmp_result); - - tmp_result = smu7_pcie_performance_request(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "pcie performance request failed!", result = tmp_result); - - return 0; -} - -static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) -{ - if (!hwmgr->avfs_supported) - return 0; - - if (enable) { - if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( - hwmgr, PPSMC_MSG_EnableAvfs, NULL), - "Failed to enable AVFS!", - return -EINVAL); - } - } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( - hwmgr, PPSMC_MSG_DisableAvfs, NULL), - "Failed to disable AVFS!", - return -EINVAL); - } - - return 0; -} - -static int smu7_update_avfs(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (!hwmgr->avfs_supported) - return 0; - - if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { - smu7_avfs_control(hwmgr, false); - } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { - smu7_avfs_control(hwmgr, false); - smu7_avfs_control(hwmgr, true); - } else { - smu7_avfs_control(hwmgr, true); - } - - return 0; -} - -static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1); - - tmp_result = smu7_disable_power_containment(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable power containment!", result = tmp_result); - - tmp_result = smu7_disable_smc_cac(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable SMC CAC!", result = tmp_result); - - tmp_result = smu7_disable_didt_config(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable DIDT!", result = tmp_result); - - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_SPLL_SPREAD_SPECTRUM, SSEN, 0); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0); - - tmp_result = smu7_disable_thermal_auto_throttle(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable thermal auto throttle!", result = tmp_result); - - tmp_result = smu7_avfs_control(hwmgr, false); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable AVFS!", result = tmp_result); - - tmp_result = smu7_stop_dpm(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to stop DPM!", result = tmp_result); - - tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable deep sleep master switch!", result = tmp_result); - - tmp_result = smu7_disable_ulv(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable ULV!", result = tmp_result); - - tmp_result = smu7_clear_voting_clients(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to clear voting clients!", result = tmp_result); - - tmp_result = smu7_reset_to_default(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to reset to default!", result = tmp_result); - - tmp_result = smu7_force_switch_to_arbf0(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to force to switch arbf0!", result = tmp_result); - - return result; -} - -static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct amdgpu_device *adev = hwmgr->adev; - - data->dll_default_on = false; - data->mclk_dpm0_activity_target = 0xa; - data->vddc_vddgfx_delta = 300; - data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; - data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; - data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0; - data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1; - data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2; - data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3; - data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4; - data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5; - data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6; - data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7; - - data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; - data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; - data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; - /* need to set voltage control types before EVV patching */ - data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE; - data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE; - data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE; - data->enable_tdc_limit_feature = true; - data->enable_pkg_pwr_tracking_feature = true; - data->force_pcie_gen = PP_PCIEGenInvalid; - data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; - data->current_profile_setting.bupdate_sclk = 1; - data->current_profile_setting.sclk_up_hyst = 0; - data->current_profile_setting.sclk_down_hyst = 100; - data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT; - data->current_profile_setting.bupdate_mclk = 1; - data->current_profile_setting.mclk_up_hyst = 0; - data->current_profile_setting.mclk_down_hyst = 100; - data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT; - hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; - hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; - hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; - - if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) { - uint8_t tmp1, tmp2; - uint16_t tmp3 = 0; - atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, - &tmp3); - tmp3 = (tmp3 >> 5) & 0x3; - data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3; - } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { - data->vddc_phase_shed_control = 1; - } else { - data->vddc_phase_shed_control = 0; - } - - if (hwmgr->chip_id == CHIP_HAWAII) { - data->thermal_temp_setting.temperature_low = 94500; - data->thermal_temp_setting.temperature_high = 95000; - data->thermal_temp_setting.temperature_shutdown = 104000; - } else { - data->thermal_temp_setting.temperature_low = 99500; - data->thermal_temp_setting.temperature_high = 100000; - data->thermal_temp_setting.temperature_shutdown = 104000; - } - - data->fast_watermark_threshold = 100; - if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) - data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; - else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) - data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDGFX)) { - if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { - data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; - } - } - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableMVDDControl)) { - if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) - data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; - else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) - data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; - } - - if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDGFX); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI)) { - if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) - data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; - else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) - data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; - } - - if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableMVDDControl); - - if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI); - - if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) - && (table_info->cac_dtp_table->usClockStretchAmount != 0)) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher); - - data->pcie_gen_performance.max = PP_PCIEGen1; - data->pcie_gen_performance.min = PP_PCIEGen3; - data->pcie_gen_power_saving.max = PP_PCIEGen1; - data->pcie_gen_power_saving.min = PP_PCIEGen3; - data->pcie_lane_performance.max = 0; - data->pcie_lane_performance.min = 16; - data->pcie_lane_power_saving.max = 0; - data->pcie_lane_power_saving.min = 16; - - - if (adev->pg_flags & AMD_PG_SUPPORT_UVD) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - if (adev->pg_flags & AMD_PG_SUPPORT_VCE) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); -} - -/** -* Get Leakage VDDC based on leakage ID. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint16_t vv_id; - uint16_t vddc = 0; - uint16_t vddgfx = 0; - uint16_t i, j; - uint32_t sclk = 0; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; - - - for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { - vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; - - if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { - if ((hwmgr->pp_table_version == PP_TABLE_V1) - && !phm_get_sclk_for_voltage_evv(hwmgr, - table_info->vddgfx_lookup_table, vv_id, &sclk)) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher)) { - sclk_table = table_info->vdd_dep_on_sclk; - - for (j = 1; j < sclk_table->count; j++) { - if (sclk_table->entries[j].clk == sclk && - sclk_table->entries[j].cks_enable == 0) { - sclk += 5000; - break; - } - } - } - if (0 == atomctrl_get_voltage_evv_on_sclk - (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, - vv_id, &vddgfx)) { - /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ - PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL); - - /* the voltage should not be zero nor equal to leakage ID */ - if (vddgfx != 0 && vddgfx != vv_id) { - data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; - data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id; - data->vddcgfx_leakage.count++; - } - } else { - pr_info("Error retrieving EVV voltage value!\n"); - } - } - } else { - if ((hwmgr->pp_table_version == PP_TABLE_V0) - || !phm_get_sclk_for_voltage_evv(hwmgr, - table_info->vddc_lookup_table, vv_id, &sclk)) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher)) { - if (table_info == NULL) - return -EINVAL; - sclk_table = table_info->vdd_dep_on_sclk; - - for (j = 1; j < sclk_table->count; j++) { - if (sclk_table->entries[j].clk == sclk && - sclk_table->entries[j].cks_enable == 0) { - sclk += 5000; - break; - } - } - } - - if (phm_get_voltage_evv_on_sclk(hwmgr, - VOLTAGE_TYPE_VDDC, - sclk, vv_id, &vddc) == 0) { - if (vddc >= 2000 || vddc == 0) - return -EINVAL; - } else { - pr_debug("failed to retrieving EVV voltage!\n"); - continue; - } - - /* the voltage should not be zero nor equal to leakage ID */ - if (vddc != 0 && vddc != vv_id) { - data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc); - data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; - data->vddc_leakage.count++; - } - } - } - } - - return 0; -} - -/** - * Change virtual leakage voltage to actual value. - * - * @param hwmgr the address of the powerplay hardware manager. - * @param pointer to changing voltage - * @param pointer to leakage table - */ -static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr, - uint16_t *voltage, struct smu7_leakage_voltage *leakage_table) -{ - uint32_t index; - - /* search for leakage voltage ID 0xff01 ~ 0xff08 */ - for (index = 0; index < leakage_table->count; index++) { - /* if this voltage matches a leakage voltage ID */ - /* patch with actual leakage voltage */ - if (leakage_table->leakage_id[index] == *voltage) { - *voltage = leakage_table->actual_voltage[index]; - break; - } - } - - if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) - pr_err("Voltage value looks like a Leakage ID but it's not patched \n"); -} - -/** -* Patch voltage lookup table by EVV leakages. -* -* @param hwmgr the address of the powerplay hardware manager. -* @param pointer to voltage lookup table -* @param pointer to leakage table -* @return always 0 -*/ -static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table *lookup_table, - struct smu7_leakage_voltage *leakage_table) -{ - uint32_t i; - - for (i = 0; i < lookup_table->count; i++) - smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, - &lookup_table->entries[i].us_vdd, leakage_table); - - return 0; -} - -static int smu7_patch_clock_voltage_limits_with_vddc_leakage( - struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table, - uint16_t *vddc) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); - hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = - table_info->max_clock_voltage_on_dc.vddc; - return 0; -} - -static int smu7_patch_voltage_dependency_tables_with_lookup_table( - struct pp_hwmgr *hwmgr) -{ - uint8_t entry_id; - uint8_t voltage_id; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = - table_info->vdd_dep_on_sclk; - struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = - table_info->vdd_dep_on_mclk; - struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = - table_info->mm_dep_table; - - if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { - for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { - voltage_id = sclk_table->entries[entry_id].vddInd; - sclk_table->entries[entry_id].vddgfx = - table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd; - } - } else { - for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { - voltage_id = sclk_table->entries[entry_id].vddInd; - sclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - } - - for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { - voltage_id = mclk_table->entries[entry_id].vddInd; - mclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - - for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { - voltage_id = mm_table->entries[entry_id].vddcInd; - mm_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - - return 0; - -} - -static int phm_add_voltage(struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table *look_up_table, - phm_ppt_v1_voltage_lookup_record *record) -{ - uint32_t i; - - PP_ASSERT_WITH_CODE((NULL != look_up_table), - "Lookup Table empty.", return -EINVAL); - PP_ASSERT_WITH_CODE((0 != look_up_table->count), - "Lookup Table empty.", return -EINVAL); - - i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); - PP_ASSERT_WITH_CODE((i >= look_up_table->count), - "Lookup Table is full.", return -EINVAL); - - /* This is to avoid entering duplicate calculated records. */ - for (i = 0; i < look_up_table->count; i++) { - if (look_up_table->entries[i].us_vdd == record->us_vdd) { - if (look_up_table->entries[i].us_calculated == 1) - return 0; - break; - } - } - - look_up_table->entries[i].us_calculated = 1; - look_up_table->entries[i].us_vdd = record->us_vdd; - look_up_table->entries[i].us_cac_low = record->us_cac_low; - look_up_table->entries[i].us_cac_mid = record->us_cac_mid; - look_up_table->entries[i].us_cac_high = record->us_cac_high; - /* Only increment the count when we're appending, not replacing duplicate entry. */ - if (i == look_up_table->count) - look_up_table->count++; - - return 0; -} - - -static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) -{ - uint8_t entry_id; - struct phm_ppt_v1_voltage_lookup_record v_record; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - - phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; - phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; - - if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { - for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { - if (sclk_table->entries[entry_id].vdd_offset & (1 << 15)) - v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + - sclk_table->entries[entry_id].vdd_offset - 0xFFFF; - else - v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + - sclk_table->entries[entry_id].vdd_offset; - - sclk_table->entries[entry_id].vddc = - v_record.us_cac_low = v_record.us_cac_mid = - v_record.us_cac_high = v_record.us_vdd; - - phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); - } - - for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { - if (mclk_table->entries[entry_id].vdd_offset & (1 << 15)) - v_record.us_vdd = mclk_table->entries[entry_id].vddc + - mclk_table->entries[entry_id].vdd_offset - 0xFFFF; - else - v_record.us_vdd = mclk_table->entries[entry_id].vddc + - mclk_table->entries[entry_id].vdd_offset; - - mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low = - v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; - phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); - } - } - return 0; -} - -static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) -{ - uint8_t entry_id; - struct phm_ppt_v1_voltage_lookup_record v_record; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; - - if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { - for (entry_id = 0; entry_id < mm_table->count; entry_id++) { - if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15)) - v_record.us_vdd = mm_table->entries[entry_id].vddc + - mm_table->entries[entry_id].vddgfx_offset - 0xFFFF; - else - v_record.us_vdd = mm_table->entries[entry_id].vddc + - mm_table->entries[entry_id].vddgfx_offset; - - /* Add the calculated VDDGFX to the VDDGFX lookup table */ - mm_table->entries[entry_id].vddgfx = v_record.us_cac_low = - v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; - phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); - } - } - return 0; -} - -static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_voltage_lookup_table *lookup_table) -{ - uint32_t table_size, i, j; - table_size = lookup_table->count; - - PP_ASSERT_WITH_CODE(0 != lookup_table->count, - "Lookup table is empty", return -EINVAL); - - /* Sorting voltages */ - for (i = 0; i < table_size - 1; i++) { - for (j = i + 1; j > 0; j--) { - if (lookup_table->entries[j].us_vdd < - lookup_table->entries[j - 1].us_vdd) { - swap(lookup_table->entries[j - 1], - lookup_table->entries[j]); - } - } - } - - return 0; -} - -static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr) -{ - int result = 0; - int tmp_result; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { - tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, - table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); - if (tmp_result != 0) - result = tmp_result; - - smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, - &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage)); - } else { - - tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, - table_info->vddc_lookup_table, &(data->vddc_leakage)); - if (tmp_result) - result = tmp_result; - - tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, - &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); - if (tmp_result) - result = tmp_result; - } - - tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr); - if (tmp_result) - result = tmp_result; - - tmp_result = smu7_calc_voltage_dependency_tables(hwmgr); - if (tmp_result) - result = tmp_result; - - tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr); - if (tmp_result) - result = tmp_result; - - tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table); - if (tmp_result) - result = tmp_result; - - tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); - if (tmp_result) - result = tmp_result; - - return result; -} - -static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = - table_info->vdd_dep_on_sclk; - struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = - table_info->vdd_dep_on_mclk; - - PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, - "VDD dependency on SCLK table is missing.", - return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, - "VDD dependency on SCLK table has to have is missing.", - return -EINVAL); - - PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, - "VDD dependency on MCLK table is missing", - return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, - "VDD dependency on MCLK table has to have is missing.", - return -EINVAL); - - table_info->max_clock_voltage_on_ac.sclk = - allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; - table_info->max_clock_voltage_on_ac.mclk = - allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; - table_info->max_clock_voltage_on_ac.vddc = - allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; - table_info->max_clock_voltage_on_ac.vddci = - allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; - - hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; - hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; - hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; - hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci; - - return 0; -} - -static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; - struct phm_ppt_v1_voltage_lookup_table *lookup_table; - uint32_t i; - uint32_t hw_revision, sub_vendor_id, sub_sys_id; - struct amdgpu_device *adev = hwmgr->adev; - - if (table_info != NULL) { - dep_mclk_table = table_info->vdd_dep_on_mclk; - lookup_table = table_info->vddc_lookup_table; - } else - return 0; - - hw_revision = adev->pdev->revision; - sub_sys_id = adev->pdev->subsystem_device; - sub_vendor_id = adev->pdev->subsystem_vendor; - - if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 && - ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) || - (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) || - (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) { - if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000) - return 0; - - for (i = 0; i < lookup_table->count; i++) { - if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) { - dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i; - return 0; - } - } - } - return 0; -} - -static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) -{ - struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; - uint32_t temp_reg; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - - if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { - temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); - switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { - case 0: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); - break; - case 1: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); - break; - case 2: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); - break; - case 3: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); - break; - case 4: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); - break; - default: - break; - } - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); - } - - if (table_info == NULL) - return 0; - - if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 && - hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) { - hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit = - (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; - - hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit = - (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; - - hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1; - - hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; - - hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit = - (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; - - hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1; - - table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ? - (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0; - - table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp; - table_info->cac_dtp_table->usOperatingTempStep = 1; - table_info->cac_dtp_table->usOperatingTempHyst = 1; - - hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; - - hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM; - - hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = - table_info->cac_dtp_table->usOperatingTempMinLimit; - - hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = - table_info->cac_dtp_table->usOperatingTempMaxLimit; - - hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = - table_info->cac_dtp_table->usDefaultTargetOperatingTemp; - - hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = - table_info->cac_dtp_table->usOperatingTempStep; - - hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = - table_info->cac_dtp_table->usTargetOperatingTemp; - if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport); - } - - return 0; -} - -/** - * Change virtual leakage voltage to actual value. - * - * @param hwmgr the address of the powerplay hardware manager. - * @param pointer to changing voltage - * @param pointer to leakage table - */ -static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr, - uint32_t *voltage, struct smu7_leakage_voltage *leakage_table) -{ - uint32_t index; - - /* search for leakage voltage ID 0xff01 ~ 0xff08 */ - for (index = 0; index < leakage_table->count; index++) { - /* if this voltage matches a leakage voltage ID */ - /* patch with actual leakage voltage */ - if (leakage_table->leakage_id[index] == *voltage) { - *voltage = leakage_table->actual_voltage[index]; - break; - } - } - - if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) - pr_err("Voltage value looks like a Leakage ID but it's not patched \n"); -} - - -static int smu7_patch_vddc(struct pp_hwmgr *hwmgr, - struct phm_clock_voltage_dependency_table *tab) -{ - uint16_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) - for (i = 0; i < tab->count; i++) - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, - &data->vddc_leakage); - - return 0; -} - -static int smu7_patch_vddci(struct pp_hwmgr *hwmgr, - struct phm_clock_voltage_dependency_table *tab) -{ - uint16_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) - for (i = 0; i < tab->count; i++) - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, - &data->vddci_leakage); - - return 0; -} - -static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr, - struct phm_vce_clock_voltage_dependency_table *tab) -{ - uint16_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) - for (i = 0; i < tab->count; i++) - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, - &data->vddc_leakage); - - return 0; -} - - -static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr, - struct phm_uvd_clock_voltage_dependency_table *tab) -{ - uint16_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) - for (i = 0; i < tab->count; i++) - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, - &data->vddc_leakage); - - return 0; -} - -static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, - struct phm_phase_shedding_limits_table *tab) -{ - uint16_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) - for (i = 0; i < tab->count; i++) - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage, - &data->vddc_leakage); - - return 0; -} - -static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr, - struct phm_samu_clock_voltage_dependency_table *tab) -{ - uint16_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) - for (i = 0; i < tab->count; i++) - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, - &data->vddc_leakage); - - return 0; -} - -static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr, - struct phm_acp_clock_voltage_dependency_table *tab) -{ - uint16_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) - for (i = 0; i < tab->count; i++) - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, - &data->vddc_leakage); - - return 0; -} - -static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, - struct phm_clock_and_voltage_limits *tab) -{ - uint32_t vddc, vddci; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) { - vddc = tab->vddc; - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, - &data->vddc_leakage); - tab->vddc = vddc; - vddci = tab->vddci; - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, - &data->vddci_leakage); - tab->vddci = vddci; - } - - return 0; -} - -static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) -{ - uint32_t i; - uint32_t vddc; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (tab) { - for (i = 0; i < tab->count; i++) { - vddc = (uint32_t)(tab->entries[i].Vddc); - smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); - tab->entries[i].Vddc = (uint16_t)vddc; - } - } - - return 0; -} - -static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) -{ - int tmp; - - tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); - if (tmp) - return -EINVAL; - - tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); - if (tmp) - return -EINVAL; - - return 0; -} - - -static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; - struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; - struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk; - - PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, - "VDDC dependency on SCLK table is missing. This table is mandatory", - return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, - "VDDC dependency on SCLK table has to have is missing. This table is mandatory", - return -EINVAL); - - PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL, - "VDDC dependency on MCLK table is missing. This table is mandatory", - return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1, - "VDD dependency on MCLK table has to have is missing. This table is mandatory", - return -EINVAL); - - data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; - data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; - - hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = - allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; - hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = - allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk; - hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = - allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; - - if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) { - data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v; - data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; - } - - if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1) - hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; - - return 0; -} - -static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) -{ - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - kfree(hwmgr->backend); - hwmgr->backend = NULL; - - return 0; -} - -static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr) -{ - uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - int i; - - if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) { - for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { - virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; - if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci, - virtual_voltage_id, - efuse_voltage_id) == 0) { - if (vddc != 0 && vddc != virtual_voltage_id) { - data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; - data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; - data->vddc_leakage.count++; - } - if (vddci != 0 && vddci != virtual_voltage_id) { - data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci; - data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id; - data->vddci_leakage.count++; - } - } - } - } - return 0; -} - -static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data; - int result = 0; - - data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - - hwmgr->backend = data; - smu7_patch_voltage_workaround(hwmgr); - smu7_init_dpm_defaults(hwmgr); - - /* Get leakage voltage based on leakage ID. */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EVV)) { - result = smu7_get_evv_voltages(hwmgr); - if (result) { - pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); - return -EINVAL; - } - } else { - smu7_get_elb_voltages(hwmgr); - } - - if (hwmgr->pp_table_version == PP_TABLE_V1) { - smu7_complete_dependency_tables(hwmgr); - smu7_set_private_data_based_on_pptable_v1(hwmgr); - } else if (hwmgr->pp_table_version == PP_TABLE_V0) { - smu7_patch_dependency_tables_with_leakage(hwmgr); - smu7_set_private_data_based_on_pptable_v0(hwmgr); - } - - /* Initalize Dynamic State Adjustment Rule Settings */ - result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); - - if (0 == result) { - struct amdgpu_device *adev = hwmgr->adev; - - data->is_tlu_enabled = false; - - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = - SMU7_MAX_HARDWARE_POWERLEVELS; - hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; - hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - - data->pcie_gen_cap = adev->pm.pcie_gen_mask; - if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - data->pcie_spc_cap = 20; - data->pcie_lane_cap = adev->pm.pcie_mlw_mask; - - hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ -/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ - hwmgr->platform_descriptor.clockStep.engineClock = 500; - hwmgr->platform_descriptor.clockStep.memoryClock = 500; - smu7_thermal_parameter_init(hwmgr); - } else { - /* Ignore return value in here, we are cleaning up a mess. */ - smu7_hwmgr_backend_fini(hwmgr); - } - - return 0; -} - -static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t level, tmp; - - if (!data->pcie_dpm_key_disabled) { - if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { - level = 0; - tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; - while (tmp >>= 1) - level++; - - if (level) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_PCIeDPM_ForceLevel, level, - NULL); - } - } - - if (!data->sclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { - level = 0; - tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; - while (tmp >>= 1) - level++; - - if (level) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level), - NULL); - } - } - - if (!data->mclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { - level = 0; - tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; - while (tmp >>= 1) - level++; - - if (level) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level), - NULL); - } - } - - return 0; -} - -static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (hwmgr->pp_table_version == PP_TABLE_V1) - phm_apply_dal_min_voltage_request(hwmgr); -/* TO DO for v0 iceland and Ci*/ - - if (!data->sclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, - data->dpm_level_enable_mask.sclk_dpm_enable_mask, - NULL); - } - - if (!data->mclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, - data->dpm_level_enable_mask.mclk_dpm_enable_mask, - NULL); - } - - return 0; -} - -static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (!smum_is_dpm_running(hwmgr)) - return -EINVAL; - - if (!data->pcie_dpm_key_disabled) { - smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_PCIeDPM_UnForceLevel, - NULL); - } - - return smu7_upload_dpm_level_enable_mask(hwmgr); -} - -static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = - (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t level; - - if (!data->sclk_dpm_key_disabled) - if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { - level = phm_get_lowest_enabled_level(hwmgr, - data->dpm_level_enable_mask.sclk_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level), - NULL); - - } - - if (!data->mclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { - level = phm_get_lowest_enabled_level(hwmgr, - data->dpm_level_enable_mask.mclk_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level), - NULL); - } - } - - if (!data->pcie_dpm_key_disabled) { - if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { - level = phm_get_lowest_enabled_level(hwmgr, - data->dpm_level_enable_mask.pcie_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_PCIeDPM_ForceLevel, - (level), - NULL); - } - } - - return 0; -} - -static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, - uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) -{ - uint32_t percentage; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; - int32_t tmp_mclk; - int32_t tmp_sclk; - int32_t count; - - if (golden_dpm_table->mclk_table.count < 1) - return -EINVAL; - - percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / - golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; - - if (golden_dpm_table->mclk_table.count == 1) { - percentage = 70; - tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; - *mclk_mask = golden_dpm_table->mclk_table.count - 1; - } else { - tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; - *mclk_mask = golden_dpm_table->mclk_table.count - 2; - } - - tmp_sclk = tmp_mclk * percentage / 100; - - if (hwmgr->pp_table_version == PP_TABLE_V0) { - for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; - count >= 0; count--) { - if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { - tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; - *sclk_mask = count; - break; - } - } - if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { - *sclk_mask = 0; - tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; - } - - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; - } else if (hwmgr->pp_table_version == PP_TABLE_V1) { - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { - if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) { - tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk; - *sclk_mask = count; - break; - } - } - if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { - *sclk_mask = 0; - tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; - } - - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; - } - - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) - *mclk_mask = 0; - else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - *mclk_mask = golden_dpm_table->mclk_table.count - 1; - - *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; - hwmgr->pstate_sclk = tmp_sclk; - hwmgr->pstate_mclk = tmp_mclk; - - return 0; -} - -static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, - enum amd_dpm_forced_level level) -{ - int ret = 0; - uint32_t sclk_mask = 0; - uint32_t mclk_mask = 0; - uint32_t pcie_mask = 0; - - if (hwmgr->pstate_sclk == 0) - smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); - - switch (level) { - case AMD_DPM_FORCED_LEVEL_HIGH: - ret = smu7_force_dpm_highest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_LOW: - ret = smu7_force_dpm_lowest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_AUTO: - ret = smu7_unforce_dpm_levels(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: - ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); - if (ret) - return ret; - smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); - smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); - smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); - break; - case AMD_DPM_FORCED_LEVEL_MANUAL: - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: - default: - break; - } - - if (!ret) { - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); - else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); - } - return ret; -} - -static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) -{ - return sizeof(struct smu7_power_state); -} - -static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr, - uint32_t vblank_time_us) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t switch_limit_us; - - switch (hwmgr->chip_id) { - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_POLARIS12: - if (hwmgr->is_kicker) - switch_limit_us = data->is_memory_gddr5 ? 450 : 150; - else - switch_limit_us = data->is_memory_gddr5 ? 190 : 150; - break; - case CHIP_VEGAM: - switch_limit_us = 30; - break; - default: - switch_limit_us = data->is_memory_gddr5 ? 450 : 150; - break; - } - - if (vblank_time_us < switch_limit_us) - return true; - else - return false; -} - -static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, - struct pp_power_state *request_ps, - const struct pp_power_state *current_ps) -{ - struct amdgpu_device *adev = hwmgr->adev; - struct smu7_power_state *smu7_ps = - cast_phw_smu7_power_state(&request_ps->hardware); - uint32_t sclk; - uint32_t mclk; - struct PP_Clocks minimum_clocks = {0}; - bool disable_mclk_switching; - bool disable_mclk_switching_for_frame_lock; - const struct phm_clock_and_voltage_limits *max_limits; - uint32_t i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - int32_t count; - int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; - - data->battery_state = (PP_StateUILabel_Battery == - request_ps->classification.ui_label); - - PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2, - "VI should always have 2 performance levels", - ); - - max_limits = adev->pm.ac_power ? - &(hwmgr->dyn_state.max_clock_voltage_on_ac) : - &(hwmgr->dyn_state.max_clock_voltage_on_dc); - - /* Cap clock DPM tables at DC MAX if it is in DC. */ - if (!adev->pm.ac_power) { - for (i = 0; i < smu7_ps->performance_level_count; i++) { - if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) - smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; - if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) - smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; - } - } - - minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; - minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { - max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); - stable_pstate_sclk = (max_limits->sclk * 75) / 100; - - for (count = table_info->vdd_dep_on_sclk->count - 1; - count >= 0; count--) { - if (stable_pstate_sclk >= - table_info->vdd_dep_on_sclk->entries[count].clk) { - stable_pstate_sclk = - table_info->vdd_dep_on_sclk->entries[count].clk; - break; - } - } - - if (count < 0) - stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; - - stable_pstate_mclk = max_limits->mclk; - - minimum_clocks.engineClock = stable_pstate_sclk; - minimum_clocks.memoryClock = stable_pstate_mclk; - } - - disable_mclk_switching_for_frame_lock = phm_cap_enabled( - hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); - - - if (hwmgr->display_config->num_display == 0) - disable_mclk_switching = false; - else - disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && - !hwmgr->display_config->multi_monitor_in_sync) || - disable_mclk_switching_for_frame_lock || - smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time); - - sclk = smu7_ps->performance_levels[0].engine_clock; - mclk = smu7_ps->performance_levels[0].memory_clock; - - if (disable_mclk_switching) - mclk = smu7_ps->performance_levels - [smu7_ps->performance_level_count - 1].memory_clock; - - if (sclk < minimum_clocks.engineClock) - sclk = (minimum_clocks.engineClock > max_limits->sclk) ? - max_limits->sclk : minimum_clocks.engineClock; - - if (mclk < minimum_clocks.memoryClock) - mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? - max_limits->mclk : minimum_clocks.memoryClock; - - smu7_ps->performance_levels[0].engine_clock = sclk; - smu7_ps->performance_levels[0].memory_clock = mclk; - - smu7_ps->performance_levels[1].engine_clock = - (smu7_ps->performance_levels[1].engine_clock >= - smu7_ps->performance_levels[0].engine_clock) ? - smu7_ps->performance_levels[1].engine_clock : - smu7_ps->performance_levels[0].engine_clock; - - if (disable_mclk_switching) { - if (mclk < smu7_ps->performance_levels[1].memory_clock) - mclk = smu7_ps->performance_levels[1].memory_clock; - - smu7_ps->performance_levels[0].memory_clock = mclk; - smu7_ps->performance_levels[1].memory_clock = mclk; - } else { - if (smu7_ps->performance_levels[1].memory_clock < - smu7_ps->performance_levels[0].memory_clock) - smu7_ps->performance_levels[1].memory_clock = - smu7_ps->performance_levels[0].memory_clock; - } - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { - for (i = 0; i < smu7_ps->performance_level_count; i++) { - smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; - smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk; - smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; - smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; - } - } - return 0; -} - - -static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct pp_power_state *ps; - struct smu7_power_state *smu7_ps; - - if (hwmgr == NULL) - return -EINVAL; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - smu7_ps = cast_phw_smu7_power_state(&ps->hardware); - - if (low) - return smu7_ps->performance_levels[0].memory_clock; - else - return smu7_ps->performance_levels - [smu7_ps->performance_level_count-1].memory_clock; -} - -static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct pp_power_state *ps; - struct smu7_power_state *smu7_ps; - - if (hwmgr == NULL) - return -EINVAL; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - smu7_ps = cast_phw_smu7_power_state(&ps->hardware); - - if (low) - return smu7_ps->performance_levels[0].engine_clock; - else - return smu7_ps->performance_levels - [smu7_ps->performance_level_count-1].engine_clock; -} - -static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps; - ATOM_FIRMWARE_INFO_V2_2 *fw_info; - uint16_t size; - uint8_t frev, crev; - int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); - - /* First retrieve the Boot clocks and VDDC from the firmware info table. - * We assume here that fw_info is unchanged if this call fails. - */ - fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index, - &size, &frev, &crev); - if (!fw_info) - /* During a test, there is no firmware info table. */ - return 0; - - /* Patch the state. */ - data->vbios_boot_state.sclk_bootup_value = - le32_to_cpu(fw_info->ulDefaultEngineClock); - data->vbios_boot_state.mclk_bootup_value = - le32_to_cpu(fw_info->ulDefaultMemoryClock); - data->vbios_boot_state.mvdd_bootup_value = - le16_to_cpu(fw_info->usBootUpMVDDCVoltage); - data->vbios_boot_state.vddc_bootup_value = - le16_to_cpu(fw_info->usBootUpVDDCVoltage); - data->vbios_boot_state.vddci_bootup_value = - le16_to_cpu(fw_info->usBootUpVDDCIVoltage); - data->vbios_boot_state.pcie_gen_bootup_value = - smu7_get_current_pcie_speed(hwmgr); - - data->vbios_boot_state.pcie_lane_bootup_value = - (uint16_t)smu7_get_current_pcie_lane_number(hwmgr); - - /* set boot power state */ - ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; - ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; - ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; - ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; - - return 0; -} - -static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) -{ - int result; - unsigned long ret = 0; - - if (hwmgr->pp_table_version == PP_TABLE_V0) { - result = pp_tables_get_num_of_entries(hwmgr, &ret); - return result ? 0 : ret; - } else if (hwmgr->pp_table_version == PP_TABLE_V1) { - result = get_number_of_powerplay_table_entries_v1_0(hwmgr); - return result; - } - return 0; -} - -static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, - void *state, struct pp_power_state *power_state, - void *pp_table, uint32_t classification_flag) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_power_state *smu7_power_state = - (struct smu7_power_state *)(&(power_state->hardware)); - struct smu7_performance_level *performance_level; - ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; - ATOM_Tonga_POWERPLAYTABLE *powerplay_table = - (ATOM_Tonga_POWERPLAYTABLE *)pp_table; - PPTable_Generic_SubTable_Header *sclk_dep_table = - (PPTable_Generic_SubTable_Header *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); - - ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = - (ATOM_Tonga_MCLK_Dependency_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); - - /* The following fields are not initialized here: id orderedList allStatesList */ - power_state->classification.ui_label = - (le16_to_cpu(state_entry->usClassification) & - ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> - ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; - power_state->classification.flags = classification_flag; - /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ - - power_state->classification.temporary_state = false; - power_state->classification.to_be_deleted = false; - - power_state->validation.disallowOnDC = - (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & - ATOM_Tonga_DISALLOW_ON_DC)); - - power_state->pcie.lanes = 0; - - power_state->display.disableFrameModulation = false; - power_state->display.limitRefreshrate = false; - power_state->display.enableVariBright = - (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & - ATOM_Tonga_ENABLE_VARIBRIGHT)); - - power_state->validation.supportedPowerLevels = 0; - power_state->uvd_clocks.VCLK = 0; - power_state->uvd_clocks.DCLK = 0; - power_state->temperatures.min = 0; - power_state->temperatures.max = 0; - - performance_level = &(smu7_power_state->performance_levels - [smu7_power_state->performance_level_count++]); - - PP_ASSERT_WITH_CODE( - (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), - "Performance levels exceeds SMC limit!", - return -EINVAL); - - PP_ASSERT_WITH_CODE( - (smu7_power_state->performance_level_count <= - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), - "Performance levels exceeds Driver limit!", - return -EINVAL); - - /* Performance levels are arranged from low to high. */ - performance_level->memory_clock = mclk_dep_table->entries - [state_entry->ucMemoryClockIndexLow].ulMclk; - if (sclk_dep_table->ucRevId == 0) - performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries - [state_entry->ucEngineClockIndexLow].ulSclk; - else if (sclk_dep_table->ucRevId == 1) - performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries - [state_entry->ucEngineClockIndexLow].ulSclk; - performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, - state_entry->ucPCIEGenLow); - performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, - state_entry->ucPCIELaneLow); - - performance_level = &(smu7_power_state->performance_levels - [smu7_power_state->performance_level_count++]); - performance_level->memory_clock = mclk_dep_table->entries - [state_entry->ucMemoryClockIndexHigh].ulMclk; - - if (sclk_dep_table->ucRevId == 0) - performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries - [state_entry->ucEngineClockIndexHigh].ulSclk; - else if (sclk_dep_table->ucRevId == 1) - performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries - [state_entry->ucEngineClockIndexHigh].ulSclk; - - performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, - state_entry->ucPCIEGenHigh); - performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, - state_entry->ucPCIELaneHigh); - - return 0; -} - -static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, - unsigned long entry_index, struct pp_power_state *state) -{ - int result; - struct smu7_power_state *ps; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = - table_info->vdd_dep_on_mclk; - - state->hardware.magic = PHM_VIslands_Magic; - - ps = (struct smu7_power_state *)(&state->hardware); - - result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state, - smu7_get_pp_table_entry_callback_func_v1); - - /* This is the earliest time we have all the dependency table and the VBIOS boot state - * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state - * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state - */ - if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { - if (dep_mclk_table->entries[0].clk != - data->vbios_boot_state.mclk_bootup_value) - pr_debug("Single MCLK entry VDDCI/MCLK dependency table " - "does not match VBIOS boot MCLK level"); - if (dep_mclk_table->entries[0].vddci != - data->vbios_boot_state.vddci_bootup_value) - pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " - "does not match VBIOS boot VDDCI level"); - } - - /* set DC compatible flag if this state supports DC */ - if (!state->validation.disallowOnDC) - ps->dc_compatible = true; - - if (state->classification.flags & PP_StateClassificationFlag_ACPI) - data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; - - ps->uvd_clks.vclk = state->uvd_clocks.VCLK; - ps->uvd_clks.dclk = state->uvd_clocks.DCLK; - - if (!result) { - uint32_t i; - - switch (state->classification.ui_label) { - case PP_StateUILabel_Performance: - data->use_pcie_performance_levels = true; - for (i = 0; i < ps->performance_level_count; i++) { - if (data->pcie_gen_performance.max < - ps->performance_levels[i].pcie_gen) - data->pcie_gen_performance.max = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_gen_performance.min > - ps->performance_levels[i].pcie_gen) - data->pcie_gen_performance.min = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_lane_performance.max < - ps->performance_levels[i].pcie_lane) - data->pcie_lane_performance.max = - ps->performance_levels[i].pcie_lane; - if (data->pcie_lane_performance.min > - ps->performance_levels[i].pcie_lane) - data->pcie_lane_performance.min = - ps->performance_levels[i].pcie_lane; - } - break; - case PP_StateUILabel_Battery: - data->use_pcie_power_saving_levels = true; - - for (i = 0; i < ps->performance_level_count; i++) { - if (data->pcie_gen_power_saving.max < - ps->performance_levels[i].pcie_gen) - data->pcie_gen_power_saving.max = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_gen_power_saving.min > - ps->performance_levels[i].pcie_gen) - data->pcie_gen_power_saving.min = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_lane_power_saving.max < - ps->performance_levels[i].pcie_lane) - data->pcie_lane_power_saving.max = - ps->performance_levels[i].pcie_lane; - - if (data->pcie_lane_power_saving.min > - ps->performance_levels[i].pcie_lane) - data->pcie_lane_power_saving.min = - ps->performance_levels[i].pcie_lane; - } - break; - default: - break; - } - } - return 0; -} - -static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *power_state, - unsigned int index, const void *clock_info) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state); - const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info; - struct smu7_performance_level *performance_level; - uint32_t engine_clock, memory_clock; - uint16_t pcie_gen_from_bios; - - engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow; - memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow; - - if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) - data->highest_mclk = memory_clock; - - PP_ASSERT_WITH_CODE( - (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), - "Performance levels exceeds SMC limit!", - return -EINVAL); - - PP_ASSERT_WITH_CODE( - (ps->performance_level_count < - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), - "Performance levels exceeds Driver limit, Skip!", - return 0); - - performance_level = &(ps->performance_levels - [ps->performance_level_count++]); - - /* Performance levels are arranged from low to high. */ - performance_level->memory_clock = memory_clock; - performance_level->engine_clock = engine_clock; - - pcie_gen_from_bios = visland_clk_info->ucPCIEGen; - - performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios); - performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane); - - return 0; -} - -static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, - unsigned long entry_index, struct pp_power_state *state) -{ - int result; - struct smu7_power_state *ps; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_clock_voltage_dependency_table *dep_mclk_table = - hwmgr->dyn_state.vddci_dependency_on_mclk; - - memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state)); - - state->hardware.magic = PHM_VIslands_Magic; - - ps = (struct smu7_power_state *)(&state->hardware); - - result = pp_tables_get_entry(hwmgr, entry_index, state, - smu7_get_pp_table_entry_callback_func_v0); - - /* - * This is the earliest time we have all the dependency table - * and the VBIOS boot state as - * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot - * state if there is only one VDDCI/MCLK level, check if it's - * the same as VBIOS boot state - */ - if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { - if (dep_mclk_table->entries[0].clk != - data->vbios_boot_state.mclk_bootup_value) - pr_debug("Single MCLK entry VDDCI/MCLK dependency table " - "does not match VBIOS boot MCLK level"); - if (dep_mclk_table->entries[0].v != - data->vbios_boot_state.vddci_bootup_value) - pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " - "does not match VBIOS boot VDDCI level"); - } - - /* set DC compatible flag if this state supports DC */ - if (!state->validation.disallowOnDC) - ps->dc_compatible = true; - - if (state->classification.flags & PP_StateClassificationFlag_ACPI) - data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; - - ps->uvd_clks.vclk = state->uvd_clocks.VCLK; - ps->uvd_clks.dclk = state->uvd_clocks.DCLK; - - if (!result) { - uint32_t i; - - switch (state->classification.ui_label) { - case PP_StateUILabel_Performance: - data->use_pcie_performance_levels = true; - - for (i = 0; i < ps->performance_level_count; i++) { - if (data->pcie_gen_performance.max < - ps->performance_levels[i].pcie_gen) - data->pcie_gen_performance.max = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_gen_performance.min > - ps->performance_levels[i].pcie_gen) - data->pcie_gen_performance.min = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_lane_performance.max < - ps->performance_levels[i].pcie_lane) - data->pcie_lane_performance.max = - ps->performance_levels[i].pcie_lane; - - if (data->pcie_lane_performance.min > - ps->performance_levels[i].pcie_lane) - data->pcie_lane_performance.min = - ps->performance_levels[i].pcie_lane; - } - break; - case PP_StateUILabel_Battery: - data->use_pcie_power_saving_levels = true; - - for (i = 0; i < ps->performance_level_count; i++) { - if (data->pcie_gen_power_saving.max < - ps->performance_levels[i].pcie_gen) - data->pcie_gen_power_saving.max = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_gen_power_saving.min > - ps->performance_levels[i].pcie_gen) - data->pcie_gen_power_saving.min = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_lane_power_saving.max < - ps->performance_levels[i].pcie_lane) - data->pcie_lane_power_saving.max = - ps->performance_levels[i].pcie_lane; - - if (data->pcie_lane_power_saving.min > - ps->performance_levels[i].pcie_lane) - data->pcie_lane_power_saving.min = - ps->performance_levels[i].pcie_lane; - } - break; - default: - break; - } - } - return 0; -} - -static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, - unsigned long entry_index, struct pp_power_state *state) -{ - if (hwmgr->pp_table_version == PP_TABLE_V0) - return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state); - else if (hwmgr->pp_table_version == PP_TABLE_V1) - return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state); - - return 0; -} - -static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) -{ - struct amdgpu_device *adev = hwmgr->adev; - int i; - u32 tmp = 0; - - if (!query) - return -EINVAL; - - /* - * PPSMC_MSG_GetCurrPkgPwr is not supported on: - * - Hawaii - * - Bonaire - * - Fiji - * - Tonga - */ - if ((adev->asic_type != CHIP_HAWAII) && - (adev->asic_type != CHIP_BONAIRE) && - (adev->asic_type != CHIP_FIJI) && - (adev->asic_type != CHIP_TONGA)) { - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp); - *query = tmp; - - if (tmp != 0) - return 0; - } - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixSMU_PM_STATUS_95, 0); - - for (i = 0; i < 10; i++) { - msleep(500); - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL); - tmp = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, - ixSMU_PM_STATUS_95); - if (tmp != 0) - break; - } - *query = tmp; - - return 0; -} - -static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, - void *value, int *size) -{ - uint32_t sclk, mclk, activity_percent; - uint32_t offset, val_vid; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /* size must be at least 4 bytes for all sensors */ - if (*size < 4) - return -EINVAL; - - switch (idx) { - case AMDGPU_PP_SENSOR_GFX_SCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk); - *((uint32_t *)value) = sclk; - *size = 4; - return 0; - case AMDGPU_PP_SENSOR_GFX_MCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk); - *((uint32_t *)value) = mclk; - *size = 4; - return 0; - case AMDGPU_PP_SENSOR_GPU_LOAD: - case AMDGPU_PP_SENSOR_MEM_LOAD: - offset = data->soft_regs_start + smum_get_offsetof(hwmgr, - SMU_SoftRegisters, - (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ? - AverageGraphicsActivity: - AverageMemoryActivity); - - activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); - activity_percent += 0x80; - activity_percent >>= 8; - *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; - *size = 4; - return 0; - case AMDGPU_PP_SENSOR_GPU_TEMP: - *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr); - *size = 4; - return 0; - case AMDGPU_PP_SENSOR_UVD_POWER: - *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; - *size = 4; - return 0; - case AMDGPU_PP_SENSOR_VCE_POWER: - *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; - *size = 4; - return 0; - case AMDGPU_PP_SENSOR_GPU_POWER: - return smu7_get_gpu_power(hwmgr, (uint32_t *)value); - case AMDGPU_PP_SENSOR_VDDGFX: - if ((data->vr_config & 0xff) == 0x2) - val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID); - else - val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID); - - *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid); - return 0; - default: - return -EINVAL; - } -} - -static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) -{ - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - const struct smu7_power_state *smu7_ps = - cast_const_phw_smu7_power_state(states->pnew_state); - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); - uint32_t sclk = smu7_ps->performance_levels - [smu7_ps->performance_level_count - 1].engine_clock; - struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); - uint32_t mclk = smu7_ps->performance_levels - [smu7_ps->performance_level_count - 1].memory_clock; - struct PP_Clocks min_clocks = {0}; - uint32_t i; - - for (i = 0; i < sclk_table->count; i++) { - if (sclk == sclk_table->dpm_levels[i].value) - break; - } - - if (i >= sclk_table->count) { - if (sclk > sclk_table->dpm_levels[i-1].value) { - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; - sclk_table->dpm_levels[i-1].value = sclk; - } - } else { - /* TODO: Check SCLK in DAL's minimum clocks - * in case DeepSleep divider update is required. - */ - if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && - (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || - data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) - data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; - } - - for (i = 0; i < mclk_table->count; i++) { - if (mclk == mclk_table->dpm_levels[i].value) - break; - } - - if (i >= mclk_table->count) { - if (mclk > mclk_table->dpm_levels[i-1].value) { - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; - mclk_table->dpm_levels[i-1].value = mclk; - } - } - - if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) - data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; - - return 0; -} - -static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr, - const struct smu7_power_state *smu7_ps) -{ - uint32_t i; - uint32_t sclk, max_sclk = 0; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_dpm_table *dpm_table = &data->dpm_table; - - for (i = 0; i < smu7_ps->performance_level_count; i++) { - sclk = smu7_ps->performance_levels[i].engine_clock; - if (max_sclk < sclk) - max_sclk = sclk; - } - - for (i = 0; i < dpm_table->sclk_table.count; i++) { - if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) - return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? - dpm_table->pcie_speed_table.dpm_levels - [dpm_table->pcie_speed_table.count - 1].value : - dpm_table->pcie_speed_table.dpm_levels[i].value); - } - - return 0; -} - -static int smu7_request_link_speed_change_before_state_change( - struct pp_hwmgr *hwmgr, const void *input) -{ - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - const struct smu7_power_state *smu7_nps = - cast_const_phw_smu7_power_state(states->pnew_state); - const struct smu7_power_state *polaris10_cps = - cast_const_phw_smu7_power_state(states->pcurrent_state); - - uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps); - uint16_t current_link_speed; - - if (data->force_pcie_gen == PP_PCIEGenInvalid) - current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps); - else - current_link_speed = data->force_pcie_gen; - - data->force_pcie_gen = PP_PCIEGenInvalid; - data->pspp_notify_required = false; - - if (target_link_speed > current_link_speed) { - switch (target_link_speed) { -#ifdef CONFIG_ACPI - case PP_PCIEGen3: - if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false)) - break; - data->force_pcie_gen = PP_PCIEGen2; - if (current_link_speed == PP_PCIEGen2) - break; - fallthrough; - case PP_PCIEGen2: - if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false)) - break; - fallthrough; -#endif - default: - data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr); - break; - } - } else { - if (target_link_speed < current_link_speed) - data->pspp_notify_required = true; - } - - return 0; -} - -static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (0 == data->need_update_smu7_dpm_table) - return 0; - - if ((0 == data->sclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { - PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), - "Trying to freeze SCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_SCLKDPM_FreezeLevel, - NULL), - "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", - return -EINVAL); - } - - if ((0 == data->mclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & - DPMTABLE_OD_UPDATE_MCLK)) { - PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), - "Trying to freeze MCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_MCLKDPM_FreezeLevel, - NULL), - "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", - return -EINVAL); - } - - return 0; -} - -static int smu7_populate_and_upload_sclk_mclk_dpm_levels( - struct pp_hwmgr *hwmgr, const void *input) -{ - int result = 0; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_dpm_table *dpm_table = &data->dpm_table; - uint32_t count; - struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); - struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); - struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); - - if (0 == data->need_update_smu7_dpm_table) - return 0; - - if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { - for (count = 0; count < dpm_table->sclk_table.count; count++) { - dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled; - dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock; - } - } - - if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { - for (count = 0; count < dpm_table->mclk_table.count; count++) { - dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; - dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; - } - } - - if (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { - result = smum_populate_all_graphic_levels(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", - return result); - } - - if (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { - /*populate MCLK dpm table to SMU7 */ - result = smum_populate_all_memory_levels(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", - return result); - } - - return result; -} - -static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, - struct smu7_single_dpm_table *dpm_table, - uint32_t low_limit, uint32_t high_limit) -{ - uint32_t i; - - /* force the trim if mclk_switching is disabled to prevent flicker */ - bool force_trim = (low_limit == high_limit); - for (i = 0; i < dpm_table->count; i++) { - /*skip the trim if od is enabled*/ - if ((!hwmgr->od_enabled || force_trim) - && (dpm_table->dpm_levels[i].value < low_limit - || dpm_table->dpm_levels[i].value > high_limit)) - dpm_table->dpm_levels[i].enabled = false; - else - dpm_table->dpm_levels[i].enabled = true; - } - - return 0; -} - -static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr, - const struct smu7_power_state *smu7_ps) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t high_limit_count; - - PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1), - "power state did not have any performance level", - return -EINVAL); - - high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1; - - smu7_trim_single_dpm_states(hwmgr, - &(data->dpm_table.sclk_table), - smu7_ps->performance_levels[0].engine_clock, - smu7_ps->performance_levels[high_limit_count].engine_clock); - - smu7_trim_single_dpm_states(hwmgr, - &(data->dpm_table.mclk_table), - smu7_ps->performance_levels[0].memory_clock, - smu7_ps->performance_levels[high_limit_count].memory_clock); - - return 0; -} - -static int smu7_generate_dpm_level_enable_mask( - struct pp_hwmgr *hwmgr, const void *input) -{ - int result = 0; - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - const struct smu7_power_state *smu7_ps = - cast_const_phw_smu7_power_state(states->pnew_state); - - - result = smu7_trim_dpm_states(hwmgr, smu7_ps); - if (result) - return result; - - data->dpm_level_enable_mask.sclk_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); - data->dpm_level_enable_mask.mclk_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); - data->dpm_level_enable_mask.pcie_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); - - return 0; -} - -static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (0 == data->need_update_smu7_dpm_table) - return 0; - - if ((0 == data->sclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { - - PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), - "Trying to Unfreeze SCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_SCLKDPM_UnfreezeLevel, - NULL), - "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", - return -EINVAL); - } - - if ((0 == data->mclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { - - PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), - "Trying to Unfreeze MCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_MCLKDPM_UnfreezeLevel, - NULL), - "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", - return -EINVAL); - } - - data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; - - return 0; -} - -static int smu7_notify_link_speed_change_after_state_change( - struct pp_hwmgr *hwmgr, const void *input) -{ - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - const struct smu7_power_state *smu7_ps = - cast_const_phw_smu7_power_state(states->pnew_state); - uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps); - uint8_t request; - - if (data->pspp_notify_required) { - if (target_link_speed == PP_PCIEGen3) - request = PCIE_PERF_REQ_GEN3; - else if (target_link_speed == PP_PCIEGen2) - request = PCIE_PERF_REQ_GEN2; - else - request = PCIE_PERF_REQ_GEN1; - - if (request == PCIE_PERF_REQ_GEN1 && - smu7_get_current_pcie_speed(hwmgr) > 0) - return 0; - -#ifdef CONFIG_ACPI - if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) { - if (PP_PCIEGen2 == target_link_speed) - pr_info("PSPP request to switch to Gen2 from Gen3 Failed!"); - else - pr_info("PSPP request to switch to Gen1 from Gen2 Failed!"); - } -#endif - } - - return 0; -} - -static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { - if (hwmgr->chip_id == CHIP_VEGAM) - smum_send_msg_to_smc_with_parameter(hwmgr, - (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2, - NULL); - else - smum_send_msg_to_smc_with_parameter(hwmgr, - (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2, - NULL); - } - return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ? 0 : -EINVAL; -} - -static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) -{ - int tmp_result, result = 0; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to find DPM states clocks in DPM table!", - result = tmp_result); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PCIEPerformanceRequest)) { - tmp_result = - smu7_request_link_speed_change_before_state_change(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to request link speed change before state change!", - result = tmp_result); - } - - tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to freeze SCLK MCLK DPM!", result = tmp_result); - - tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to populate and upload SCLK MCLK DPM levels!", - result = tmp_result); - - /* - * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. - * That effectively disables AVFS feature. - */ - if (hwmgr->hardcode_pp_table != NULL) - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; - - tmp_result = smu7_update_avfs(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to update avfs voltages!", - result = tmp_result); - - tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to generate DPM level enabled mask!", - result = tmp_result); - - tmp_result = smum_update_sclk_threshold(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to update SCLK threshold!", - result = tmp_result); - - tmp_result = smu7_notify_smc_display(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to notify smc display settings!", - result = tmp_result); - - tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to unfreeze SCLK MCLK DPM!", - result = tmp_result); - - tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to upload DPM level enabled mask!", - result = tmp_result); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PCIEPerformanceRequest)) { - tmp_result = - smu7_notify_link_speed_change_after_state_change(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to notify link speed change after state change!", - result = tmp_result); - } - data->apply_optimized_settings = false; - return result; -} - -static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) -{ - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; - - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm, - NULL); -} - -static int -smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) -{ - PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; - - return (smum_send_msg_to_smc(hwmgr, msg, NULL) == 0) ? 0 : -1; -} - -static int -smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->display_config->num_display > 1 && - !hwmgr->display_config->multi_monitor_in_sync) - smu7_notify_smc_display_change(hwmgr, false); - - return 0; -} - -/** -* Programs the display gap -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always OK -*/ -static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); - uint32_t display_gap2; - uint32_t pre_vbi_time_in_us; - uint32_t frame_time_in_us; - uint32_t ref_clock, refresh_rate; - - display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); - - ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); - refresh_rate = hwmgr->display_config->vrefresh; - - if (0 == refresh_rate) - refresh_rate = 60; - - frame_time_in_us = 1000000 / refresh_rate; - - pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time; - - data->frame_time_x2 = frame_time_in_us * 2 / 100; - - if (data->frame_time_x2 < 280) { - pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2); - data->frame_time_x2 = 280; - } - - display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + smum_get_offsetof(hwmgr, - SMU_SoftRegisters, - PreVBlankGap), 0x64); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + smum_get_offsetof(hwmgr, - SMU_SoftRegisters, - VBlankTimeout), - (frame_time_in_us - pre_vbi_time_in_us)); - - return 0; -} - -static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) -{ - return smu7_program_display_gap(hwmgr); -} - -/** -* Set maximum target operating fan output RPM -* -* @param hwmgr: the address of the powerplay hardware manager. -* @param usMaxFanRpm: max operating fan RPM value. -* @return The response that came from the SMC. -*/ -static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) -{ - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; - - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm, - NULL); -} - -static const struct amdgpu_irq_src_funcs smu7_irq_funcs = { - .process = phm_irq_process, -}; - -static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_irq_src *source = - kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); - - if (!source) - return -ENOMEM; - - source->funcs = &smu7_irq_funcs; - - amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), - AMDGPU_IRQ_CLIENTID_LEGACY, - VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH, - source); - amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), - AMDGPU_IRQ_CLIENTID_LEGACY, - VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW, - source); - - /* Register CTF(GPIO_19) interrupt */ - amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), - AMDGPU_IRQ_CLIENTID_LEGACY, - VISLANDS30_IV_SRCID_GPIO_19, - source); - - return 0; -} - -static bool -smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - bool is_update_required = false; - - if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) - is_update_required = true; - - if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh) - is_update_required = true; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr && - (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK || - hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) - is_update_required = true; - } - return is_update_required; -} - -static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, - const struct smu7_performance_level *pl2) -{ - return ((pl1->memory_clock == pl2->memory_clock) && - (pl1->engine_clock == pl2->engine_clock) && - (pl1->pcie_gen == pl2->pcie_gen) && - (pl1->pcie_lane == pl2->pcie_lane)); -} - -static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, - const struct pp_hw_power_state *pstate1, - const struct pp_hw_power_state *pstate2, bool *equal) -{ - const struct smu7_power_state *psa; - const struct smu7_power_state *psb; - int i; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (pstate1 == NULL || pstate2 == NULL || equal == NULL) - return -EINVAL; - - psa = cast_const_phw_smu7_power_state(pstate1); - psb = cast_const_phw_smu7_power_state(pstate2); - /* If the two states don't even have the same number of performance levels they cannot be the same state. */ - if (psa->performance_level_count != psb->performance_level_count) { - *equal = false; - return 0; - } - - for (i = 0; i < psa->performance_level_count; i++) { - if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { - /* If we have found even one performance level pair that is different the states are different. */ - *equal = false; - return 0; - } - } - - /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ - *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); - *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); - *equal &= (psa->sclk_threshold == psb->sclk_threshold); - /* For OD call, set value based on flag */ - *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | - DPMTABLE_OD_UPDATE_MCLK | - DPMTABLE_OD_UPDATE_VDDC)); - - return 0; -} - -static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - uint32_t tmp; - - /* Read MC indirect register offset 0x9F bits [3:0] to see - * if VBIOS has already loaded a full version of MC ucode - * or not. - */ - - smu7_get_mc_microcode_version(hwmgr); - - data->need_long_memory_training = false; - - cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, - ixMC_IO_DEBUG_UP_13); - tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); - - if (tmp & (1 << 23)) { - data->mem_latency_high = MEM_LATENCY_HIGH; - data->mem_latency_low = MEM_LATENCY_LOW; - if ((hwmgr->chip_id == CHIP_POLARIS10) || - (hwmgr->chip_id == CHIP_POLARIS11) || - (hwmgr->chip_id == CHIP_POLARIS12)) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL); - } else { - data->mem_latency_high = 330; - data->mem_latency_low = 330; - if ((hwmgr->chip_id == CHIP_POLARIS10) || - (hwmgr->chip_id == CHIP_POLARIS11) || - (hwmgr->chip_id == CHIP_POLARIS12)) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL); - } - - return 0; -} - -static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - data->clock_registers.vCG_SPLL_FUNC_CNTL = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); - data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); - data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); - data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); - data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); - data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); - data->clock_registers.vDLL_CNTL = - cgs_read_register(hwmgr->device, mmDLL_CNTL); - data->clock_registers.vMCLK_PWRMGT_CNTL = - cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); - data->clock_registers.vMPLL_AD_FUNC_CNTL = - cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); - data->clock_registers.vMPLL_DQ_FUNC_CNTL = - cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); - data->clock_registers.vMPLL_FUNC_CNTL = - cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); - data->clock_registers.vMPLL_FUNC_CNTL_1 = - cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); - data->clock_registers.vMPLL_FUNC_CNTL_2 = - cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); - data->clock_registers.vMPLL_SS1 = - cgs_read_register(hwmgr->device, mmMPLL_SS1); - data->clock_registers.vMPLL_SS2 = - cgs_read_register(hwmgr->device, mmMPLL_SS2); - return 0; - -} - -/** - * Find out if memory is GDDR5. - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int smu7_get_memory_type(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct amdgpu_device *adev = hwmgr->adev; - - data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5); - - return 0; -} - -/** - * Enables Dynamic Power Management by SMC - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr) -{ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, STATIC_PM_EN, 1); - - return 0; -} - -/** - * Initialize PowerGating States for different engines - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - data->uvd_power_gated = false; - data->vce_power_gated = false; - - return 0; -} - -static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - data->low_sclk_interrupt_threshold = 0; - return 0; -} - -static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - - smu7_check_mc_firmware(hwmgr); - - tmp_result = smu7_read_clock_registers(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to read clock registers!", result = tmp_result); - - tmp_result = smu7_get_memory_type(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to get memory type!", result = tmp_result); - - tmp_result = smu7_enable_acpi_power_management(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable ACPI power management!", result = tmp_result); - - tmp_result = smu7_init_power_gate_state(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to init power gate state!", result = tmp_result); - - tmp_result = smu7_get_mc_microcode_version(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to get MC microcode version!", result = tmp_result); - - tmp_result = smu7_init_sclk_threshold(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to init sclk threshold!", result = tmp_result); - - return result; -} - -static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (mask == 0) - return -EINVAL; - - switch (type) { - case PP_SCLK: - if (!data->sclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, - data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask, - NULL); - break; - case PP_MCLK: - if (!data->mclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, - data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask, - NULL); - break; - case PP_PCIE: - { - uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; - - if (!data->pcie_dpm_key_disabled) { - if (fls(tmp) != ffs(tmp)) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel, - NULL); - else - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_PCIeDPM_ForceLevel, - fls(tmp) - 1, - NULL); - } - break; - } - default: - break; - } - - return 0; -} - -static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); - struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); - struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); - struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); - struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); - struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); - int i, now, size = 0; - uint32_t clock, pcie_speed; - - switch (type) { - case PP_SCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock); - - for (i = 0; i < sclk_table->count; i++) { - if (clock > sclk_table->dpm_levels[i].value) - continue; - break; - } - now = i; - - for (i = 0; i < sclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, sclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_MCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock); - - for (i = 0; i < mclk_table->count; i++) { - if (clock > mclk_table->dpm_levels[i].value) - continue; - break; - } - now = i; - - for (i = 0; i < mclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, mclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_PCIE: - pcie_speed = smu7_get_current_pcie_speed(hwmgr); - for (i = 0; i < pcie_table->count; i++) { - if (pcie_speed != pcie_table->dpm_levels[i].value) - continue; - break; - } - now = i; - - for (i = 0; i < pcie_table->count; i++) - size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" : - (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : - (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", - (i == now) ? "*" : ""); - break; - case OD_SCLK: - if (hwmgr->od_enabled) { - size = sprintf(buf, "%s:\n", "OD_SCLK"); - for (i = 0; i < odn_sclk_table->num_of_pl; i++) - size += sprintf(buf + size, "%d: %10uMHz %10umV\n", - i, odn_sclk_table->entries[i].clock/100, - odn_sclk_table->entries[i].vddc); - } - break; - case OD_MCLK: - if (hwmgr->od_enabled) { - size = sprintf(buf, "%s:\n", "OD_MCLK"); - for (i = 0; i < odn_mclk_table->num_of_pl; i++) - size += sprintf(buf + size, "%d: %10uMHz %10umV\n", - i, odn_mclk_table->entries[i].clock/100, - odn_mclk_table->entries[i].vddc); - } - break; - case OD_RANGE: - if (hwmgr->od_enabled) { - size = sprintf(buf, "%s:\n", "OD_RANGE"); - size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.engineClock/100); - size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); - size += sprintf(buf + size, "VDDC: %7umV %11umV\n", - data->odn_dpm_table.min_vddc, - data->odn_dpm_table.max_vddc); - } - break; - default: - break; - } - return size; -} - -static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - switch (mode) { - case AMD_FAN_CTRL_NONE: - smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); - break; - case AMD_FAN_CTRL_MANUAL: - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) - smu7_fan_ctrl_stop_smc_fan_control(hwmgr); - break; - case AMD_FAN_CTRL_AUTO: - if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode)) - smu7_fan_ctrl_start_smc_fan_control(hwmgr); - break; - default: - break; - } -} - -static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) -{ - return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL; -} - -static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); - struct smu7_single_dpm_table *golden_sclk_table = - &(data->golden_dpm_table.sclk_table); - int value = sclk_table->dpm_levels[sclk_table->count - 1].value; - int golden_value = golden_sclk_table->dpm_levels - [golden_sclk_table->count - 1].value; - - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_single_dpm_table *golden_sclk_table = - &(data->golden_dpm_table.sclk_table); - struct pp_power_state *ps; - struct smu7_power_state *smu7_ps; - - if (value > 20) - value = 20; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - smu7_ps = cast_phw_smu7_power_state(&ps->hardware); - - smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock = - golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * - value / 100 + - golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; - - return 0; -} - -static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); - struct smu7_single_dpm_table *golden_mclk_table = - &(data->golden_dpm_table.mclk_table); - int value = mclk_table->dpm_levels[mclk_table->count - 1].value; - int golden_value = golden_mclk_table->dpm_levels - [golden_mclk_table->count - 1].value; - - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_single_dpm_table *golden_mclk_table = - &(data->golden_dpm_table.mclk_table); - struct pp_power_state *ps; - struct smu7_power_state *smu7_ps; - - if (value > 20) - value = 20; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - smu7_ps = cast_phw_smu7_power_state(&ps->hardware); - - smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock = - golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * - value / 100 + - golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; - - return 0; -} - - -static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; - struct phm_clock_voltage_dependency_table *sclk_table; - int i; - - if (hwmgr->pp_table_version == PP_TABLE_V1) { - if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) - return -EINVAL; - dep_sclk_table = table_info->vdd_dep_on_sclk; - for (i = 0; i < dep_sclk_table->count; i++) - clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; - clocks->count = dep_sclk_table->count; - } else if (hwmgr->pp_table_version == PP_TABLE_V0) { - sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; - for (i = 0; i < sclk_table->count; i++) - clocks->clock[i] = sclk_table->entries[i].clk * 10; - clocks->count = sclk_table->count; - } - - return 0; -} - -static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY) - return data->mem_latency_high; - else if (clk >= MEM_FREQ_HIGH_LATENCY) - return data->mem_latency_low; - else - return MEM_LATENCY_ERR; -} - -static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; - int i; - struct phm_clock_voltage_dependency_table *mclk_table; - - if (hwmgr->pp_table_version == PP_TABLE_V1) { - if (table_info == NULL) - return -EINVAL; - dep_mclk_table = table_info->vdd_dep_on_mclk; - for (i = 0; i < dep_mclk_table->count; i++) { - clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; - clocks->latency[i] = smu7_get_mem_latency(hwmgr, - dep_mclk_table->entries[i].clk); - } - clocks->count = dep_mclk_table->count; - } else if (hwmgr->pp_table_version == PP_TABLE_V0) { - mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; - for (i = 0; i < mclk_table->count; i++) - clocks->clock[i] = mclk_table->entries[i].clk * 10; - clocks->count = mclk_table->count; - } - return 0; -} - -static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks) -{ - switch (type) { - case amd_pp_sys_clock: - smu7_get_sclks(hwmgr, clocks); - break; - case amd_pp_mem_clock: - smu7_get_mclks(hwmgr, clocks); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, - uint32_t virtual_addr_low, - uint32_t virtual_addr_hi, - uint32_t mc_addr_low, - uint32_t mc_addr_hi, - uint32_t size) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + - smum_get_offsetof(hwmgr, - SMU_SoftRegisters, DRAM_LOG_ADDR_H), - mc_addr_hi); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + - smum_get_offsetof(hwmgr, - SMU_SoftRegisters, DRAM_LOG_ADDR_L), - mc_addr_low); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + - smum_get_offsetof(hwmgr, - SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H), - virtual_addr_hi); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + - smum_get_offsetof(hwmgr, - SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L), - virtual_addr_low); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + - smum_get_offsetof(hwmgr, - SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE), - size); - return 0; -} - -static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr, - struct amd_pp_simple_clock_info *clocks) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); - struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); - - if (clocks == NULL) - return -EINVAL; - - clocks->memory_max_clock = mclk_table->count > 1 ? - mclk_table->dpm_levels[mclk_table->count-1].value : - mclk_table->dpm_levels[0].value; - clocks->engine_max_clock = sclk_table->count > 1 ? - sclk_table->dpm_levels[sclk_table->count-1].value : - sclk_table->dpm_levels[0].value; - return 0; -} - -static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *thermal_data) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - - memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); - - if (hwmgr->pp_table_version == PP_TABLE_V1) - thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - else if (hwmgr->pp_table_version == PP_TABLE_V0) - thermal_data->max = data->thermal_temp_setting.temperature_shutdown * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return 0; -} - -static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, - enum PP_OD_DPM_TABLE_COMMAND type, - uint32_t clk, - uint32_t voltage) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) { - pr_info("OD voltage is out of range [%d - %d] mV\n", - data->odn_dpm_table.min_vddc, - data->odn_dpm_table.max_vddc); - return false; - } - - if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { - if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk || - hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { - pr_info("OD engine clock is out of range [%d - %d] MHz\n", - data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.engineClock/100); - return false; - } - } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { - if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk || - hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { - pr_info("OD memory clock is out of range [%d - %d] MHz\n", - data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); - return false; - } - } else { - return false; - } - - return true; -} - -static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, - enum PP_OD_DPM_TABLE_COMMAND type, - long *input, uint32_t size) -{ - uint32_t i; - struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL; - struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL; - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - uint32_t input_clk; - uint32_t input_vol; - uint32_t input_level; - - PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", - return -EINVAL); - - if (!hwmgr->od_enabled) { - pr_info("OverDrive feature not enabled\n"); - return -EINVAL; - } - - if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { - podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels; - podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk; - PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), - "Failed to get ODN SCLK and Voltage tables", - return -EINVAL); - } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { - podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels; - podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk; - - PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), - "Failed to get ODN MCLK and Voltage tables", - return -EINVAL); - } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { - smu7_odn_initial_default_setting(hwmgr); - return 0; - } else if (PP_OD_COMMIT_DPM_TABLE == type) { - smu7_check_dpm_table_updated(hwmgr); - return 0; - } else { - return -EINVAL; - } - - for (i = 0; i < size; i += 3) { - if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) { - pr_info("invalid clock voltage input \n"); - return 0; - } - input_level = input[i]; - input_clk = input[i+1] * 100; - input_vol = input[i+2]; - - if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { - podn_dpm_table_in_backend->entries[input_level].clock = input_clk; - podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; - podn_dpm_table_in_backend->entries[input_level].vddc = input_vol; - podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol; - podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol; - } else { - return -EINVAL; - } - } - - return 0; -} - -static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t i, size = 0; - uint32_t len; - - static const char *profile_name[7] = {"BOOTUP_DEFAULT", - "3D_FULL_SCREEN", - "POWER_SAVING", - "VIDEO", - "VR", - "COMPUTE", - "CUSTOM"}; - - static const char *title[8] = {"NUM", - "MODE_NAME", - "SCLK_UP_HYST", - "SCLK_DOWN_HYST", - "SCLK_ACTIVE_LEVEL", - "MCLK_UP_HYST", - "MCLK_DOWN_HYST", - "MCLK_ACTIVE_LEVEL"}; - - if (!buf) - return -EINVAL; - - size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n", - title[0], title[1], title[2], title[3], - title[4], title[5], title[6], title[7]); - - len = ARRAY_SIZE(smu7_profiling); - - for (i = 0; i < len; i++) { - if (i == hwmgr->power_profile_mode) { - size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n", - i, profile_name[i], "*", - data->current_profile_setting.sclk_up_hyst, - data->current_profile_setting.sclk_down_hyst, - data->current_profile_setting.sclk_activity, - data->current_profile_setting.mclk_up_hyst, - data->current_profile_setting.mclk_down_hyst, - data->current_profile_setting.mclk_activity); - continue; - } - if (smu7_profiling[i].bupdate_sclk) - size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ", - i, profile_name[i], smu7_profiling[i].sclk_up_hyst, - smu7_profiling[i].sclk_down_hyst, - smu7_profiling[i].sclk_activity); - else - size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ", - i, profile_name[i], "-", "-", "-"); - - if (smu7_profiling[i].bupdate_mclk) - size += sprintf(buf + size, "%16d %16d %16d\n", - smu7_profiling[i].mclk_up_hyst, - smu7_profiling[i].mclk_down_hyst, - smu7_profiling[i].mclk_activity); - else - size += sprintf(buf + size, "%16s %16s %16s\n", - "-", "-", "-"); - } - - return size; -} - -static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr, - enum PP_SMC_POWER_PROFILE requst) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - uint32_t tmp, level; - - if (requst == PP_SMC_POWER_PROFILE_COMPUTE) { - if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { - level = 0; - tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; - while (tmp >>= 1) - level++; - if (level > 0) - smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); - } - } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) { - smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); - } -} - -static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct profile_mode_setting tmp; - enum PP_SMC_POWER_PROFILE mode; - - if (input == NULL) - return -EINVAL; - - mode = input[size]; - switch (mode) { - case PP_SMC_POWER_PROFILE_CUSTOM: - if (size < 8 && size != 0) - return -EINVAL; - /* If only CUSTOM is passed in, use the saved values. Check - * that we actually have a CUSTOM profile by ensuring that - * the "use sclk" or the "use mclk" bits are set - */ - tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM]; - if (size == 0) { - if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0) - return -EINVAL; - } else { - tmp.bupdate_sclk = input[0]; - tmp.sclk_up_hyst = input[1]; - tmp.sclk_down_hyst = input[2]; - tmp.sclk_activity = input[3]; - tmp.bupdate_mclk = input[4]; - tmp.mclk_up_hyst = input[5]; - tmp.mclk_down_hyst = input[6]; - tmp.mclk_activity = input[7]; - smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp; - } - if (!smum_update_dpm_settings(hwmgr, &tmp)) { - memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting)); - hwmgr->power_profile_mode = mode; - } - break; - case PP_SMC_POWER_PROFILE_FULLSCREEN3D: - case PP_SMC_POWER_PROFILE_POWERSAVING: - case PP_SMC_POWER_PROFILE_VIDEO: - case PP_SMC_POWER_PROFILE_VR: - case PP_SMC_POWER_PROFILE_COMPUTE: - if (mode == hwmgr->power_profile_mode) - return 0; - - memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting)); - if (!smum_update_dpm_settings(hwmgr, &tmp)) { - if (tmp.bupdate_sclk) { - data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk; - data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst; - data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst; - data->current_profile_setting.sclk_activity = tmp.sclk_activity; - } - if (tmp.bupdate_mclk) { - data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk; - data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst; - data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst; - data->current_profile_setting.mclk_activity = tmp.mclk_activity; - } - smu7_patch_compute_profile_mode(hwmgr, mode); - hwmgr->power_profile_mode = mode; - } - break; - default: - return -EINVAL; - } - - return 0; -} - -static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, - PHM_PerformanceLevelDesignation designation, uint32_t index, - PHM_PerformanceLevel *level) -{ - const struct smu7_power_state *ps; - uint32_t i; - - if (level == NULL || hwmgr == NULL || state == NULL) - return -EINVAL; - - ps = cast_const_phw_smu7_power_state(state); - - i = index > ps->performance_level_count - 1 ? - ps->performance_level_count - 1 : index; - - level->coreClock = ps->performance_levels[i].engine_clock; - level->memory_clock = ps->performance_levels[i].memory_clock; - - return 0; -} - -static int smu7_power_off_asic(struct pp_hwmgr *hwmgr) -{ - int result; - - result = smu7_disable_dpm_tasks(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "[disable_dpm_tasks] Failed to disable DPM!", - ); - - return result; -} - -static const struct pp_hwmgr_func smu7_hwmgr_funcs = { - .backend_init = &smu7_hwmgr_backend_init, - .backend_fini = &smu7_hwmgr_backend_fini, - .asic_setup = &smu7_setup_asic_task, - .dynamic_state_management_enable = &smu7_enable_dpm_tasks, - .apply_state_adjust_rules = smu7_apply_state_adjust_rules, - .force_dpm_level = &smu7_force_dpm_level, - .power_state_set = smu7_set_power_state_tasks, - .get_power_state_size = smu7_get_power_state_size, - .get_mclk = smu7_dpm_get_mclk, - .get_sclk = smu7_dpm_get_sclk, - .patch_boot_state = smu7_dpm_patch_boot_state, - .get_pp_table_entry = smu7_get_pp_table_entry, - .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries, - .powerdown_uvd = smu7_powerdown_uvd, - .powergate_uvd = smu7_powergate_uvd, - .powergate_vce = smu7_powergate_vce, - .disable_clock_power_gating = smu7_disable_clock_power_gating, - .update_clock_gatings = smu7_update_clock_gatings, - .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment, - .display_config_changed = smu7_display_configuration_changed_task, - .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output, - .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output, - .stop_thermal_controller = smu7_thermal_stop_thermal_controller, - .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info, - .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent, - .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent, - .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default, - .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm, - .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm, - .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller, - .register_irq_handlers = smu7_register_irq_handlers, - .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration, - .check_states_equal = smu7_check_states_equal, - .set_fan_control_mode = smu7_set_fan_control_mode, - .get_fan_control_mode = smu7_get_fan_control_mode, - .force_clock_level = smu7_force_clock_level, - .print_clock_levels = smu7_print_clock_levels, - .powergate_gfx = smu7_powergate_gfx, - .get_sclk_od = smu7_get_sclk_od, - .set_sclk_od = smu7_set_sclk_od, - .get_mclk_od = smu7_get_mclk_od, - .set_mclk_od = smu7_set_mclk_od, - .get_clock_by_type = smu7_get_clock_by_type, - .read_sensor = smu7_read_sensor, - .dynamic_state_management_disable = smu7_disable_dpm_tasks, - .avfs_control = smu7_avfs_control, - .disable_smc_firmware_ctf = smu7_thermal_disable_alert, - .start_thermal_controller = smu7_start_thermal_controller, - .notify_cac_buffer_info = smu7_notify_cac_buffer_info, - .get_max_high_clocks = smu7_get_max_high_clocks, - .get_thermal_temperature_range = smu7_get_thermal_temperature_range, - .odn_edit_dpm_table = smu7_odn_edit_dpm_table, - .set_power_limit = smu7_set_power_limit, - .get_power_profile_mode = smu7_get_power_profile_mode, - .set_power_profile_mode = smu7_set_power_profile_mode, - .get_performance_level = smu7_get_performance_level, - .get_asic_baco_capability = smu7_baco_get_capability, - .get_asic_baco_state = smu7_baco_get_state, - .set_asic_baco_state = smu7_baco_set_state, - .power_off_asic = smu7_power_off_asic, -}; - -uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, - uint32_t clock_insr) -{ - uint8_t i; - uint32_t temp; - uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); - - PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0); - for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { - temp = clock >> i; - - if (temp >= min || i == 0) - break; - } - return i; -} - -int smu7_init_function_pointers(struct pp_hwmgr *hwmgr) -{ - hwmgr->hwmgr_func = &smu7_hwmgr_funcs; - if (hwmgr->pp_table_version == PP_TABLE_V0) - hwmgr->pptable_func = &pptable_funcs; - else if (hwmgr->pp_table_version == PP_TABLE_V1) - hwmgr->pptable_func = &pptable_v1_0_funcs; - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h deleted file mode 100644 index 69d361f8dfca..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _SMU7_HWMGR_H -#define _SMU7_HWMGR_H - -#include "hwmgr.h" -#include "ppatomctrl.h" - -#define SMU7_MAX_HARDWARE_POWERLEVELS 2 - -#define SMU7_VOLTAGE_CONTROL_NONE 0x0 -#define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1 -#define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2 -#define SMU7_VOLTAGE_CONTROL_MERGED 0x3 - -enum gpu_pt_config_reg_type { - GPU_CONFIGREG_MMR = 0, - GPU_CONFIGREG_SMC_IND, - GPU_CONFIGREG_DIDT_IND, - GPU_CONFIGREG_GC_CAC_IND, - GPU_CONFIGREG_CACHE, - GPU_CONFIGREG_MAX -}; - -struct gpu_pt_config_reg { - uint32_t offset; - uint32_t mask; - uint32_t shift; - uint32_t value; - enum gpu_pt_config_reg_type type; -}; - -struct smu7_performance_level { - uint32_t memory_clock; - uint32_t engine_clock; - uint16_t pcie_gen; - uint16_t pcie_lane; -}; - -struct smu7_thermal_temperature_setting { - long temperature_low; - long temperature_high; - long temperature_shutdown; -}; - -struct smu7_uvd_clocks { - uint32_t vclk; - uint32_t dclk; -}; - -struct smu7_vce_clocks { - uint32_t evclk; - uint32_t ecclk; -}; - -struct smu7_power_state { - uint32_t magic; - struct smu7_uvd_clocks uvd_clks; - struct smu7_vce_clocks vce_clks; - uint32_t sam_clk; - uint16_t performance_level_count; - bool dc_compatible; - uint32_t sclk_threshold; - struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; -}; - -struct smu7_dpm_level { - bool enabled; - uint32_t value; - uint32_t param1; -}; - -#define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5 -#define MAX_REGULAR_DPM_NUMBER 8 -#define SMU7_MINIMUM_ENGINE_CLOCK 2500 - -struct smu7_single_dpm_table { - uint32_t count; - struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; -}; - -struct smu7_dpm_table { - struct smu7_single_dpm_table sclk_table; - struct smu7_single_dpm_table mclk_table; - struct smu7_single_dpm_table pcie_speed_table; - struct smu7_single_dpm_table vddc_table; - struct smu7_single_dpm_table vddci_table; - struct smu7_single_dpm_table mvdd_table; -}; - -struct smu7_clock_registers { - uint32_t vCG_SPLL_FUNC_CNTL; - uint32_t vCG_SPLL_FUNC_CNTL_2; - uint32_t vCG_SPLL_FUNC_CNTL_3; - uint32_t vCG_SPLL_FUNC_CNTL_4; - uint32_t vCG_SPLL_SPREAD_SPECTRUM; - uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; - uint32_t vDLL_CNTL; - uint32_t vMCLK_PWRMGT_CNTL; - uint32_t vMPLL_AD_FUNC_CNTL; - uint32_t vMPLL_DQ_FUNC_CNTL; - uint32_t vMPLL_FUNC_CNTL; - uint32_t vMPLL_FUNC_CNTL_1; - uint32_t vMPLL_FUNC_CNTL_2; - uint32_t vMPLL_SS1; - uint32_t vMPLL_SS2; -}; - -#define DISABLE_MC_LOADMICROCODE 1 -#define DISABLE_MC_CFGPROGRAMMING 2 - -struct smu7_voltage_smio_registers { - uint32_t vS0_VID_LOWER_SMIO_CNTL; -}; - -#define SMU7_MAX_LEAKAGE_COUNT 8 - -struct smu7_leakage_voltage { - uint16_t count; - uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT]; - uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT]; -}; - -struct smu7_vbios_boot_state { - uint16_t mvdd_bootup_value; - uint16_t vddc_bootup_value; - uint16_t vddci_bootup_value; - uint16_t vddgfx_bootup_value; - uint32_t sclk_bootup_value; - uint32_t mclk_bootup_value; - uint16_t pcie_gen_bootup_value; - uint16_t pcie_lane_bootup_value; -}; - -struct smu7_display_timing { - uint32_t min_clock_in_sr; - uint32_t num_existing_displays; - uint32_t vrefresh; -}; - -struct smu7_dpmlevel_enable_mask { - uint32_t uvd_dpm_enable_mask; - uint32_t vce_dpm_enable_mask; - uint32_t acp_dpm_enable_mask; - uint32_t samu_dpm_enable_mask; - uint32_t sclk_dpm_enable_mask; - uint32_t mclk_dpm_enable_mask; - uint32_t pcie_dpm_enable_mask; -}; - -struct smu7_pcie_perf_range { - uint16_t max; - uint16_t min; -}; - -struct smu7_odn_clock_voltage_dependency_table { - uint32_t count; - phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct smu7_odn_dpm_table { - struct phm_odn_clock_levels odn_core_clock_dpm_levels; - struct phm_odn_clock_levels odn_memory_clock_dpm_levels; - struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; - struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; - uint32_t odn_mclk_min_limit; - uint32_t min_vddc; - uint32_t max_vddc; -}; - -struct profile_mode_setting { - uint8_t bupdate_sclk; - uint8_t sclk_up_hyst; - uint8_t sclk_down_hyst; - uint16_t sclk_activity; - uint8_t bupdate_mclk; - uint8_t mclk_up_hyst; - uint8_t mclk_down_hyst; - uint16_t mclk_activity; -}; - -struct smu7_hwmgr { - struct smu7_dpm_table dpm_table; - struct smu7_dpm_table golden_dpm_table; - struct smu7_odn_dpm_table odn_dpm_table; - - uint32_t voting_rights_clients[8]; - uint32_t static_screen_threshold_unit; - uint32_t static_screen_threshold; - uint32_t voltage_control; - uint32_t vdd_gfx_control; - uint32_t vddc_vddgfx_delta; - uint32_t active_auto_throttle_sources; - - struct smu7_clock_registers clock_registers; - - bool is_memory_gddr5; - uint16_t acpi_vddc; - bool pspp_notify_required; - uint16_t force_pcie_gen; - uint16_t acpi_pcie_gen; - uint32_t pcie_gen_cap; - uint32_t pcie_lane_cap; - uint32_t pcie_spc_cap; - struct smu7_leakage_voltage vddc_leakage; - struct smu7_leakage_voltage vddci_leakage; - struct smu7_leakage_voltage vddcgfx_leakage; - - uint32_t mvdd_control; - uint32_t vddc_mask_low; - uint32_t mvdd_mask_low; - uint16_t max_vddc_in_pptable; - uint16_t min_vddc_in_pptable; - uint16_t max_vddci_in_pptable; - uint16_t min_vddci_in_pptable; - bool is_uvd_enabled; - struct smu7_vbios_boot_state vbios_boot_state; - - bool pcie_performance_request; - bool battery_state; - bool is_tlu_enabled; - bool disable_handshake; - bool smc_voltage_control_enabled; - bool vbi_time_out_support; - - uint32_t soft_regs_start; - /* ---- Stuff originally coming from Evergreen ---- */ - uint32_t vddci_control; - struct pp_atomctrl_voltage_table vddc_voltage_table; - struct pp_atomctrl_voltage_table vddci_voltage_table; - struct pp_atomctrl_voltage_table mvdd_voltage_table; - struct pp_atomctrl_voltage_table vddgfx_voltage_table; - - uint32_t mgcg_cgtt_local2; - uint32_t mgcg_cgtt_local3; - uint32_t gpio_debug; - uint32_t mc_micro_code_feature; - uint32_t highest_mclk; - uint16_t acpi_vddci; - uint8_t mvdd_high_index; - uint8_t mvdd_low_index; - bool dll_default_on; - bool performance_request_registered; - - /* ---- Low Power Features ---- */ - bool ulv_supported; - - /* ---- CAC Stuff ---- */ - uint32_t cac_table_start; - bool cac_configuration_required; - bool driver_calculate_cac_leakage; - bool cac_enabled; - - /* ---- DPM2 Parameters ---- */ - uint32_t power_containment_features; - bool enable_dte_feature; - bool enable_tdc_limit_feature; - bool enable_pkg_pwr_tracking_feature; - bool disable_uvd_power_tune_feature; - - - uint32_t dte_tj_offset; - uint32_t fast_watermark_threshold; - - /* ---- Phase Shedding ---- */ - uint8_t vddc_phase_shed_control; - - /* ---- DI/DT ---- */ - struct smu7_display_timing display_timing; - - /* ---- Thermal Temperature Setting ---- */ - struct smu7_thermal_temperature_setting thermal_temp_setting; - struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; - uint32_t need_update_smu7_dpm_table; - uint32_t sclk_dpm_key_disabled; - uint32_t mclk_dpm_key_disabled; - uint32_t pcie_dpm_key_disabled; - uint32_t min_engine_clocks; - struct smu7_pcie_perf_range pcie_gen_performance; - struct smu7_pcie_perf_range pcie_lane_performance; - struct smu7_pcie_perf_range pcie_gen_power_saving; - struct smu7_pcie_perf_range pcie_lane_power_saving; - bool use_pcie_performance_levels; - bool use_pcie_power_saving_levels; - uint32_t mclk_dpm0_activity_target; - uint32_t low_sclk_interrupt_threshold; - uint32_t last_mclk_dpm_enable_mask; - bool uvd_enabled; - - /* ---- Power Gating States ---- */ - bool uvd_power_gated; - bool vce_power_gated; - bool need_long_memory_training; - - /* Application power optimization parameters */ - bool update_up_hyst; - bool update_down_hyst; - uint32_t down_hyst; - uint32_t up_hyst; - uint32_t disable_dpm_mask; - bool apply_optimized_settings; - - uint32_t avfs_vdroop_override_setting; - bool apply_avfs_cks_off_voltage; - uint32_t frame_time_x2; - uint16_t mem_latency_high; - uint16_t mem_latency_low; - uint32_t vr_config; - struct profile_mode_setting current_profile_setting; -}; - -/* To convert to Q8.8 format for firmware */ -#define SMU7_Q88_FORMAT_CONVERSION_UNIT 256 - -enum SMU7_I2CLineID { - SMU7_I2CLineID_DDC1 = 0x90, - SMU7_I2CLineID_DDC2 = 0x91, - SMU7_I2CLineID_DDC3 = 0x92, - SMU7_I2CLineID_DDC4 = 0x93, - SMU7_I2CLineID_DDC5 = 0x94, - SMU7_I2CLineID_DDC6 = 0x95, - SMU7_I2CLineID_SCLSDA = 0x96, - SMU7_I2CLineID_DDCVGA = 0x97 -}; - -#define SMU7_I2C_DDC1DATA 0 -#define SMU7_I2C_DDC1CLK 1 -#define SMU7_I2C_DDC2DATA 2 -#define SMU7_I2C_DDC2CLK 3 -#define SMU7_I2C_DDC3DATA 4 -#define SMU7_I2C_DDC3CLK 5 -#define SMU7_I2C_SDA 40 -#define SMU7_I2C_SCL 41 -#define SMU7_I2C_DDC4DATA 65 -#define SMU7_I2C_DDC4CLK 66 -#define SMU7_I2C_DDC5DATA 0x48 -#define SMU7_I2C_DDC5CLK 0x49 -#define SMU7_I2C_DDC6DATA 0x4a -#define SMU7_I2C_DDC6CLK 0x4b -#define SMU7_I2C_DDCVGADATA 0x4c -#define SMU7_I2C_DDCVGACLK 0x4d - -#define SMU7_UNUSED_GPIO_PIN 0x7F -uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, - uint32_t clock_insr); -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c deleted file mode 100644 index 5d4971576111..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +++ /dev/null @@ -1,1239 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include "hwmgr.h" -#include "smumgr.h" -#include "smu7_hwmgr.h" -#include "smu7_powertune.h" -#include "smu7_common.h" - -#define VOLTAGE_SCALE 4 - -static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; - -static uint32_t Polaris11_DIDTBlock_Info = SQ_PCC_MASK | TCP_IR_MASK | TD_PCC_MASK; - -static const struct gpu_pt_config_reg GCCACConfig_Polaris10[] = { -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value Type - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060013, GPU_CONFIGREG_GC_CAC_IND }, - - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0013, GPU_CONFIGREG_GC_CAC_IND }, - - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900013, GPU_CONFIGREG_GC_CAC_IND }, - - { 0xFFFFFFFF } -}; - -static const struct gpu_pt_config_reg GCCACConfig_Polaris11[] = { -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value Type - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060011, GPU_CONFIGREG_GC_CAC_IND }, - - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0011, GPU_CONFIGREG_GC_CAC_IND }, - - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100011, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900011, GPU_CONFIGREG_GC_CAC_IND }, - - { 0xFFFFFFFF } -}; - -static const struct gpu_pt_config_reg DIDTConfig_Polaris10[] = { -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value Type - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0009, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0009, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { 0xFFFFFFFF } -}; - -static const struct gpu_pt_config_reg DIDTConfig_Polaris11[] = { -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value Type - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { 0xFFFFFFFF } -}; - -static const struct gpu_pt_config_reg DIDTConfig_Polaris12[] = { -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value Type - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { 0xFFFFFFFF } -}; - -static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value Type - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ */ - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x004c, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00d0, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0069, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x0048, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x005f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x007a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x001f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x002d, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x0088, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - /* DIDT_TD */ - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - /* DIDT_TCP */ - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct gpu_pt_config_reg GCCACConfig_VegaM[] = -{ -// --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -// Offset Mask Shift Value Type -// --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - // DIDT_SQ - // - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060013, GPU_CONFIGREG_GC_CAC_IND }, - - // DIDT_TD - // - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0013, GPU_CONFIGREG_GC_CAC_IND }, - - // DIDT_TCP - // - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100013, GPU_CONFIGREG_GC_CAC_IND }, - { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900013, GPU_CONFIGREG_GC_CAC_IND }, - - { 0xFFFFFFFF } // End of list -}; - -static const struct gpu_pt_config_reg DIDTConfig_VegaM[] = -{ -// --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -// Offset Mask Shift Value Type -// --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - // DIDT_SQ - // - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - // DIDT_TD - // - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0009, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0009, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - // DIDT_TCP - // - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,0x01aa, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, - - { 0xFFFFFFFF } // End of list -}; -static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) -{ - uint32_t en = enable ? 1 : 0; - uint32_t block_en = 0; - int32_t result = 0; - uint32_t didt_block; - - if (hwmgr->chip_id == CHIP_POLARIS11) - didt_block = Polaris11_DIDTBlock_Info; - else - didt_block = DIDTBlock_Info; - - block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0; - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_SQ_CTRL0, DIDT_CTRL_EN, block_en); - didt_block &= ~SQ_Enable_MASK; - didt_block |= block_en << SQ_Enable_SHIFT; - - block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0; - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_DB_CTRL0, DIDT_CTRL_EN, block_en); - didt_block &= ~DB_Enable_MASK; - didt_block |= block_en << DB_Enable_SHIFT; - - block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0; - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_TD_CTRL0, DIDT_CTRL_EN, block_en); - didt_block &= ~TD_Enable_MASK; - didt_block |= block_en << TD_Enable_SHIFT; - - block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0; - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_TCP_CTRL0, DIDT_CTRL_EN, block_en); - didt_block &= ~TCP_Enable_MASK; - didt_block |= block_en << TCP_Enable_SHIFT; - - if (enable) - result = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_Didt_Block_Function, - didt_block, - NULL); - - return result; -} - -static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr, - const struct gpu_pt_config_reg *cac_config_regs) -{ - const struct gpu_pt_config_reg *config_regs = cac_config_regs; - uint32_t cache = 0; - uint32_t data = 0; - - PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL); - - while (config_regs->offset != 0xFFFFFFFF) { - if (config_regs->type == GPU_CONFIGREG_CACHE) - cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); - else { - switch (config_regs->type) { - case GPU_CONFIGREG_SMC_IND: - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset); - break; - - case GPU_CONFIGREG_DIDT_IND: - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); - break; - - case GPU_CONFIGREG_GC_CAC_IND: - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); - break; - - default: - data = cgs_read_register(hwmgr->device, config_regs->offset); - break; - } - - data &= ~config_regs->mask; - data |= ((config_regs->value << config_regs->shift) & config_regs->mask); - data |= cache; - - switch (config_regs->type) { - case GPU_CONFIGREG_SMC_IND: - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data); - break; - - case GPU_CONFIGREG_DIDT_IND: - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); - break; - - case GPU_CONFIGREG_GC_CAC_IND: - cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); - break; - - default: - cgs_write_register(hwmgr->device, config_regs->offset, data); - break; - } - cache = 0; - } - - config_regs++; - } - - return 0; -} - -int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) -{ - int result; - uint32_t num_se = 0; - uint32_t count, value, value2; - struct amdgpu_device *adev = hwmgr->adev; - - num_se = adev->gfx.config.max_shader_engines; - - if (PP_CAP(PHM_PlatformCaps_SQRamping) || - PP_CAP(PHM_PlatformCaps_DBRamping) || - PP_CAP(PHM_PlatformCaps_TDRamping) || - PP_CAP(PHM_PlatformCaps_TCPRamping)) { - - amdgpu_gfx_rlc_enter_safe_mode(adev); - mutex_lock(&adev->grbm_idx_mutex); - value = 0; - value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); - for (count = 0; count < num_se; count++) { - value = SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK - | SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK - | (count << SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT); - cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value); - - if (hwmgr->chip_id == CHIP_POLARIS10) { - result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - } else if (hwmgr->chip_id == CHIP_POLARIS11) { - result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - if (hwmgr->is_kicker) - result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker); - else - result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - } else if (hwmgr->chip_id == CHIP_POLARIS12) { - result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris12); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - } else if (hwmgr->chip_id == CHIP_VEGAM) { - result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_VegaM); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_VegaM); - PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); - } - } - cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2); - - result = smu7_enable_didt(hwmgr, true); - PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error); - - if (hwmgr->chip_id == CHIP_POLARIS11) { - result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_EnableDpmDidt), - NULL); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to enable DPM DIDT.", goto error); - } - mutex_unlock(&adev->grbm_idx_mutex); - amdgpu_gfx_rlc_exit_safe_mode(adev); - } - - return 0; -error: - mutex_unlock(&adev->grbm_idx_mutex); - amdgpu_gfx_rlc_exit_safe_mode(adev); - return result; -} - -int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) -{ - int result; - struct amdgpu_device *adev = hwmgr->adev; - - if (PP_CAP(PHM_PlatformCaps_SQRamping) || - PP_CAP(PHM_PlatformCaps_DBRamping) || - PP_CAP(PHM_PlatformCaps_TDRamping) || - PP_CAP(PHM_PlatformCaps_TCPRamping)) { - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - result = smu7_enable_didt(hwmgr, false); - PP_ASSERT_WITH_CODE((result == 0), - "Post DIDT enable clock gating failed.", - goto error); - if (hwmgr->chip_id == CHIP_POLARIS11) { - result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_DisableDpmDidt), - NULL); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to disable DPM DIDT.", goto error); - } - amdgpu_gfx_rlc_exit_safe_mode(adev); - } - - return 0; -error: - amdgpu_gfx_rlc_exit_safe_mode(adev); - return result; -} - -int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - int result = 0; - - if (PP_CAP(PHM_PlatformCaps_CAC)) { - int smc_result; - smc_result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_EnableCac), - NULL); - PP_ASSERT_WITH_CODE((0 == smc_result), - "Failed to enable CAC in SMC.", result = -1); - - data->cac_enabled = (0 == smc_result) ? true : false; - } - return result; -} - -int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - int result = 0; - - if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) { - int smc_result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_DisableCac), - NULL); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable CAC in SMC.", result = -1); - - data->cac_enabled = false; - } - return result; -} - -int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_PkgPwrLimit) - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_PkgPwrSetLimit, - n<<8, - NULL); - return 0; -} - -static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, - uint32_t target_tdp) -{ - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_OverDriveSetTargetTdp, - target_tdp, - NULL); -} - -int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - int smc_result; - int result = 0; - struct phm_cac_tdp_table *cac_table; - - data->power_containment_features = 0; - if (hwmgr->pp_table_version == PP_TABLE_V1) - cac_table = table_info->cac_dtp_table; - else - cac_table = hwmgr->dyn_state.cac_dtp_table; - - if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { - if (data->enable_tdc_limit_feature) { - smc_result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_TDCLimitEnable), - NULL); - PP_ASSERT_WITH_CODE((0 == smc_result), - "Failed to enable TDCLimit in SMC.", result = -1;); - if (0 == smc_result) - data->power_containment_features |= - POWERCONTAINMENT_FEATURE_TDCLimit; - } - - if (data->enable_pkg_pwr_tracking_feature) { - smc_result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable), - NULL); - PP_ASSERT_WITH_CODE((0 == smc_result), - "Failed to enable PkgPwrTracking in SMC.", result = -1;); - if (0 == smc_result) { - hwmgr->default_power_limit = hwmgr->power_limit = - cac_table->usMaximumPowerDeliveryLimit; - data->power_containment_features |= - POWERCONTAINMENT_FEATURE_PkgPwrLimit; - - if (smu7_set_power_limit(hwmgr, hwmgr->power_limit)) - pr_err("Failed to set Default Power Limit in SMC!"); - } - } - } - return result; -} - -int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - int result = 0; - - if (PP_CAP(PHM_PlatformCaps_PowerContainment) && - data->power_containment_features) { - int smc_result; - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_TDCLimit) { - smc_result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_TDCLimitDisable), - NULL); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable TDCLimit in SMC.", - result = smc_result); - } - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_DTE) { - smc_result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_DisableDTE), - NULL); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable DTE in SMC.", - result = smc_result); - } - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_PkgPwrLimit) { - smc_result = smum_send_msg_to_smc(hwmgr, - (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable), - NULL); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable PkgPwrTracking in SMC.", - result = smc_result); - } - data->power_containment_features = 0; - } - - return result; -} - -int smu7_power_control_set_level(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_cac_tdp_table *cac_table; - - int adjust_percent, target_tdp; - int result = 0; - - if (hwmgr->pp_table_version == PP_TABLE_V1) - cac_table = table_info->cac_dtp_table; - else - cac_table = hwmgr->dyn_state.cac_dtp_table; - if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { - /* adjustment percentage has already been validated */ - adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? - hwmgr->platform_descriptor.TDPAdjustment : - (-1 * hwmgr->platform_descriptor.TDPAdjustment); - - if (hwmgr->chip_id > CHIP_TONGA) - target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100; - else - target_tdp = ((100 + adjust_percent) * (int)(cac_table->usConfigurableTDP * 256)) / 100; - - result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); - } - - return result; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h deleted file mode 100644 index 22f86b6bf1be..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _SMU7_POWERTUNE_H -#define _SMU7_POWERTUNE_H - -#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xfffc0000 -#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x12 -#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xfffc0000 -#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x12 -#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xfffc0000 -#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12 -#define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK 0xc0000000 -#define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e -#define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK 0xc0000000 -#define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e -#define DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK 0xc0000000 -#define DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e - -/* PowerContainment Features */ -#define POWERCONTAINMENT_FEATURE_DTE 0x00000001 -#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 -#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 - -#define ixGC_CAC_CNTL 0x0000 -#define ixDIDT_SQ_STALL_CTRL 0x0004 -#define ixDIDT_SQ_TUNING_CTRL 0x0005 -#define ixDIDT_TD_STALL_CTRL 0x0044 -#define ixDIDT_TD_TUNING_CTRL 0x0045 -#define ixDIDT_TCP_STALL_CTRL 0x0064 -#define ixDIDT_TCP_TUNING_CTRL 0x0065 - - -int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr); -int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr); -int smu7_enable_power_containment(struct pp_hwmgr *hwmgr); -int smu7_disable_power_containment(struct pp_hwmgr *hwmgr); -int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); -int smu7_power_control_set_level(struct pp_hwmgr *hwmgr); -int smu7_enable_didt_config(struct pp_hwmgr *hwmgr); -int smu7_disable_didt_config(struct pp_hwmgr *hwmgr); -#endif /* DGPU_POWERTUNE_H */ - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c deleted file mode 100644 index 0b30f73649a8..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include <asm/div64.h> -#include "smu7_thermal.h" -#include "smu7_hwmgr.h" -#include "smu7_common.h" - -int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info) -{ - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return -ENODEV; - - fan_speed_info->supports_percent_read = true; - fan_speed_info->supports_percent_write = true; - fan_speed_info->min_percent = 0; - fan_speed_info->max_percent = 100; - - if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { - fan_speed_info->supports_rpm_read = true; - fan_speed_info->supports_rpm_write = true; - fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; - fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM; - } else { - fan_speed_info->min_rpm = 0; - fan_speed_info->max_rpm = 0; - } - - return 0; -} - -int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t *speed) -{ - uint32_t duty100; - uint32_t duty; - uint64_t tmp64; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return -ENODEV; - - duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL1, FMAX_DUTY100); - duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_STATUS, FDO_PWM_DUTY); - - if (duty100 == 0) - return -EINVAL; - - - tmp64 = (uint64_t)duty * 100; - do_div(tmp64, duty100); - *speed = (uint32_t)tmp64; - - if (*speed > 100) - *speed = 100; - - return 0; -} - -int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) -{ - uint32_t tach_period; - uint32_t crystal_clock_freq; - - if (hwmgr->thermal_controller.fanInfo.bNoFan || - !hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) - return -ENODEV; - - tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_TACH_STATUS, TACH_PERIOD); - - if (tach_period == 0) - return -EINVAL; - - crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); - - *speed = 60 * crystal_clock_freq * 10000 / tach_period; - - return 0; -} - -/** -* Set Fan Speed Control to static mode, so that the user can decide what speed to use. -* @param hwmgr the address of the powerplay hardware manager. -* mode the fan control mode, 0 default, 1 by percent, 5, by RPM -* @exception Should always succeed. -*/ -int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - if (hwmgr->fan_ctrl_is_in_default_mode) { - hwmgr->fan_ctrl_default_mode = - PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, FDO_PWM_MODE); - hwmgr->tmin = - PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TMIN); - hwmgr->fan_ctrl_is_in_default_mode = false; - } - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TMIN, 0); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, FDO_PWM_MODE, mode); - - return 0; -} - -/** -* Reset Fan Speed Control to default mode. -* @param hwmgr the address of the powerplay hardware manager. -* @exception Should always succeed. -*/ -int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr->fan_ctrl_is_in_default_mode) { - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TMIN, hwmgr->tmin); - hwmgr->fan_ctrl_is_in_default_mode = true; - } - - return 0; -} - -int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - int result; - - if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) { - result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl, - FAN_CONTROL_FUZZY, NULL); - - if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM)) - hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanRPM); - else - hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr, - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanPWM); - - } else { - result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl, - FAN_CONTROL_TABLE, NULL); - } - - if (!result && hwmgr->thermal_controller. - advanceFanControlParameters.ucTargetTemperature) - result = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFanTemperatureTarget, - hwmgr->thermal_controller. - advanceFanControlParameters.ucTargetTemperature, - NULL); - hwmgr->fan_ctrl_enabled = true; - - return result; -} - - -int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - hwmgr->fan_ctrl_enabled = false; - return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl, NULL); -} - -/** -* Set Fan Speed in percent. -* @param hwmgr the address of the powerplay hardware manager. -* @param speed is the percentage value (0% - 100%) to be set. -* @exception Fails is the 100% setting appears to be 0. -*/ -int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t speed) -{ - uint32_t duty100; - uint32_t duty; - uint64_t tmp64; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - if (speed > 100) - speed = 100; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - smu7_fan_ctrl_stop_smc_fan_control(hwmgr); - - duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL1, FMAX_DUTY100); - - if (duty100 == 0) - return -EINVAL; - - tmp64 = (uint64_t)speed * duty100; - do_div(tmp64, 100); - duty = (uint32_t)tmp64; - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL0, FDO_STATIC_DUTY, duty); - - return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); -} - -/** -* Reset Fan Speed to default. -* @param hwmgr the address of the powerplay hardware manager. -* @exception Always succeeds. -*/ -int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) -{ - int result; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { - result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); - if (!result) - result = smu7_fan_ctrl_start_smc_fan_control(hwmgr); - } else - result = smu7_fan_ctrl_set_default_mode(hwmgr); - - return result; -} - -/** -* Set Fan Speed in RPM. -* @param hwmgr the address of the powerplay hardware manager. -* @param speed is the percentage value (min - max) to be set. -* @exception Fails is the speed not lie between min and max. -*/ -int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) -{ - uint32_t tach_period; - uint32_t crystal_clock_freq; - - if (hwmgr->thermal_controller.fanInfo.bNoFan || - (hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution == 0) || - speed == 0 || - (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || - (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) - return 0; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - smu7_fan_ctrl_stop_smc_fan_control(hwmgr); - - crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); - - tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_TACH_CTRL, TARGET_PERIOD, tach_period); - - return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM); -} - -/** -* Reads the remote temperature from the SIslands thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr) -{ - int temp; - - temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_MULT_THERMAL_STATUS, CTF_TEMP); - - /* Bit 9 means the reading is lower than the lowest usable value. */ - if (temp & 0x200) - temp = SMU7_THERMAL_MAXIMUM_TEMP_READING; - else - temp = temp & 0x1ff; - - temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return temp; -} - -/** -* Set the requested temperature range for high and low alert signals -* -* @param hwmgr The address of the hardware manager. -* @param range Temperature range to be programmed for high and low alert signals -* @exception PP_Result_BadInput if the input data is not valid. -*/ -static int smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - int low_temp, int high_temp) -{ - int low = SMU7_THERMAL_MINIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - int high = SMU7_THERMAL_MAXIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - if (low < low_temp) - low = low_temp; - if (high > high_temp) - high = high_temp; - - if (low > high) - return -EINVAL; - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, DIG_THERM_INTH, - (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, DIG_THERM_INTL, - (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_CTRL, DIG_THERM_DPM, - (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - - return 0; -} - -/** -* Programs thermal controller one-time setting registers -* -* @param hwmgr The address of the hardware manager. -*/ -static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_TACH_CTRL, EDGE_PER_REV, - hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution - 1); - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28); - - return 0; -} - -/** -* Enable thermal alerts on the RV770 thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr) -{ - uint32_t alert; - - alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK); - alert &= ~(SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK, alert); - - /* send message to SMU to enable internal thermal interrupts */ - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable, NULL); -} - -/** -* Disable thermal alerts on the RV770 thermal controller. -* @param hwmgr The address of the hardware manager. -*/ -int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr) -{ - uint32_t alert; - - alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK); - alert |= (SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK, alert); - - /* send message to SMU to disable internal thermal interrupts */ - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable, NULL); -} - -/** -* Uninitialize the thermal controller. -* Currently just disables alerts. -* @param hwmgr The address of the hardware manager. -*/ -int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) -{ - int result = smu7_thermal_disable_alert(hwmgr); - - if (!hwmgr->thermal_controller.fanInfo.bNoFan) - smu7_fan_ctrl_set_default_mode(hwmgr); - - return result; -} - -/** -* Start the fan control on the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ -/* If the fantable setup has failed we could have disabled - * PHM_PlatformCaps_MicrocodeFanControl even after - * this function was included in the table. - * Make sure that we still think controlling the fan is OK. -*/ - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { - smu7_fan_ctrl_start_smc_fan_control(hwmgr); - smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); - } - - return 0; -} - -int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range) -{ - int ret = 0; - - if (range == NULL) - return -EINVAL; - - smu7_thermal_initialize(hwmgr); - ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max); - if (ret) - return -EINVAL; - smu7_thermal_enable_alert(hwmgr); - ret = smum_thermal_avfs_enable(hwmgr); - if (ret) - return -EINVAL; - -/* We should restrict performance levels to low before we halt the SMC. - * On the other hand we are still in boot state when we do this - * so it would be pointless. - * If this assumption changes we have to revisit this table. - */ - smum_thermal_setup_fan_table(hwmgr); - smu7_thermal_start_smc_fan_control(hwmgr); - return 0; -} - - - -int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr->thermal_controller.fanInfo.bNoFan) - smu7_fan_ctrl_set_default_mode(hwmgr); - return 0; -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h deleted file mode 100644 index 42c1ba0fad78..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _SMU7_THERMAL_H_ -#define _SMU7_THERMAL_H_ - -#include "hwmgr.h" - -#define SMU7_THERMAL_HIGH_ALERT_MASK 0x1 -#define SMU7_THERMAL_LOW_ALERT_MASK 0x2 - -#define SMU7_THERMAL_MINIMUM_TEMP_READING -256 -#define SMU7_THERMAL_MAXIMUM_TEMP_READING 255 - -#define SMU7_THERMAL_MINIMUM_ALERT_TEMP 0 -#define SMU7_THERMAL_MAXIMUM_ALERT_TEMP 255 - -#define FDO_PWM_MODE_STATIC 1 -#define FDO_PWM_MODE_STATIC_RPM 5 - -extern int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr); -extern int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); -extern int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); -extern int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed); -extern int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); -extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); -extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); -extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); -extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr); -extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); -extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); -extern int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr); -extern int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *temperature_range); -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c deleted file mode 100644 index 35ed47ebaf09..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +++ /dev/null @@ -1,2049 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "pp_debug.h" -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include "atom-types.h" -#include "atombios.h" -#include "processpptables.h" -#include "cgs_common.h" -#include "smu/smu_8_0_d.h" -#include "smu8_fusion.h" -#include "smu/smu_8_0_sh_mask.h" -#include "smumgr.h" -#include "hwmgr.h" -#include "hardwaremanager.h" -#include "cz_ppsmc.h" -#include "smu8_hwmgr.h" -#include "power_state.h" -#include "pp_thermal.h" - -#define ixSMUSVI_NB_CURRENTVID 0xD8230044 -#define CURRENT_NB_VID_MASK 0xff000000 -#define CURRENT_NB_VID__SHIFT 24 -#define ixSMUSVI_GFX_CURRENTVID 0xD8230048 -#define CURRENT_GFX_VID_MASK 0xff000000 -#define CURRENT_GFX_VID__SHIFT 24 - -static const unsigned long smu8_magic = (unsigned long) PHM_Cz_Magic; - -static struct smu8_power_state *cast_smu8_power_state(struct pp_hw_power_state *hw_ps) -{ - if (smu8_magic != hw_ps->magic) - return NULL; - - return (struct smu8_power_state *)hw_ps; -} - -static const struct smu8_power_state *cast_const_smu8_power_state( - const struct pp_hw_power_state *hw_ps) -{ - if (smu8_magic != hw_ps->magic) - return NULL; - - return (struct smu8_power_state *)hw_ps; -} - -static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr, - uint32_t clock, uint32_t msg) -{ - int i = 0; - struct phm_vce_clock_voltage_dependency_table *ptable = - hwmgr->dyn_state.vce_clock_voltage_dependency_table; - - switch (msg) { - case PPSMC_MSG_SetEclkSoftMin: - case PPSMC_MSG_SetEclkHardMin: - for (i = 0; i < (int)ptable->count; i++) { - if (clock <= ptable->entries[i].ecclk) - break; - } - break; - - case PPSMC_MSG_SetEclkSoftMax: - case PPSMC_MSG_SetEclkHardMax: - for (i = ptable->count - 1; i >= 0; i--) { - if (clock >= ptable->entries[i].ecclk) - break; - } - break; - - default: - break; - } - - return i; -} - -static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr, - uint32_t clock, uint32_t msg) -{ - int i = 0; - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - - switch (msg) { - case PPSMC_MSG_SetSclkSoftMin: - case PPSMC_MSG_SetSclkHardMin: - for (i = 0; i < (int)table->count; i++) { - if (clock <= table->entries[i].clk) - break; - } - break; - - case PPSMC_MSG_SetSclkSoftMax: - case PPSMC_MSG_SetSclkHardMax: - for (i = table->count - 1; i >= 0; i--) { - if (clock >= table->entries[i].clk) - break; - } - break; - - default: - break; - } - return i; -} - -static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr, - uint32_t clock, uint32_t msg) -{ - int i = 0; - struct phm_uvd_clock_voltage_dependency_table *ptable = - hwmgr->dyn_state.uvd_clock_voltage_dependency_table; - - switch (msg) { - case PPSMC_MSG_SetUvdSoftMin: - case PPSMC_MSG_SetUvdHardMin: - for (i = 0; i < (int)ptable->count; i++) { - if (clock <= ptable->entries[i].vclk) - break; - } - break; - - case PPSMC_MSG_SetUvdSoftMax: - case PPSMC_MSG_SetUvdHardMax: - for (i = ptable->count - 1; i >= 0; i--) { - if (clock >= ptable->entries[i].vclk) - break; - } - break; - - default: - break; - } - - return i; -} - -static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - if (data->max_sclk_level == 0) { - smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_GetMaxSclkLevel, - &data->max_sclk_level); - data->max_sclk_level += 1; - } - - return data->max_sclk_level; -} - -static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct amdgpu_device *adev = hwmgr->adev; - - data->gfx_ramp_step = 256*25/100; - data->gfx_ramp_delay = 1; /* by default, we delay 1us */ - - data->mgcg_cgtt_local0 = 0x00000000; - data->mgcg_cgtt_local1 = 0x00000000; - data->clock_slow_down_freq = 25000; - data->skip_clock_slow_down = 1; - data->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */ - data->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */ - data->voting_rights_clients = 0x00C00033; - data->static_screen_threshold = 8; - data->ddi_power_gating_disabled = 0; - data->bapm_enabled = 1; - data->voltage_drop_threshold = 0; - data->gfx_power_gating_threshold = 500; - data->vce_slow_sclk_threshold = 20000; - data->dce_slow_sclk_threshold = 30000; - data->disable_driver_thermal_policy = 1; - data->disable_nb_ps3_in_battery = 0; - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ABM); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_NonABMSupportInPPLib); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicM3Arbiter); - - data->override_dynamic_mgpg = 1; - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPatchPowerState); - - data->thermal_auto_throttling_treshold = 0; - data->tdr_clock = 0; - data->disable_gfx_power_gating_in_uvd = 0; - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicUVDState); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDPM); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEDPM); - - data->cc6_settings.cpu_cc6_disable = false; - data->cc6_settings.cpu_pstate_disable = false; - data->cc6_settings.nb_pstate_switch_disable = false; - data->cc6_settings.cpu_pstate_separation_time = 0; - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DisableVoltageIsland); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); - - if (adev->pg_flags & AMD_PG_SUPPORT_UVD) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - if (adev->pg_flags & AMD_PG_SUPPORT_VCE) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); - - - return 0; -} - -/* convert form 8bit vid to real voltage in mV*4 */ -static uint32_t smu8_convert_8Bit_index_to_voltage( - struct pp_hwmgr *hwmgr, uint16_t voltage) -{ - return 6200 - (voltage * 25); -} - -static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, - struct phm_clock_and_voltage_limits *table) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct smu8_sys_info *sys_info = &data->sys_info; - struct phm_clock_voltage_dependency_table *dep_table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - - if (dep_table->count > 0) { - table->sclk = dep_table->entries[dep_table->count-1].clk; - table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr, - (uint16_t)dep_table->entries[dep_table->count-1].v); - } - table->mclk = sys_info->nbp_memory_clock[0]; - return 0; -} - -static int smu8_init_dynamic_state_adjustment_rule_settings( - struct pp_hwmgr *hwmgr, - ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table) -{ - struct phm_clock_voltage_dependency_table *table_clk_vlt; - - table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 7), - GFP_KERNEL); - - if (NULL == table_clk_vlt) { - pr_err("Can not allocate memory!\n"); - return -ENOMEM; - } - - table_clk_vlt->count = 8; - table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; - table_clk_vlt->entries[0].v = 0; - table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; - table_clk_vlt->entries[1].v = 1; - table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; - table_clk_vlt->entries[2].v = 2; - table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; - table_clk_vlt->entries[3].v = 3; - table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; - table_clk_vlt->entries[4].v = 4; - table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; - table_clk_vlt->entries[5].v = 5; - table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; - table_clk_vlt->entries[6].v = 6; - table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; - table_clk_vlt->entries[7].v = 7; - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; - - return 0; -} - -static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL; - uint32_t i; - int result = 0; - uint8_t frev, crev; - uint16_t size; - - info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev, - GetIndexIntoMasterTable(DATA, IntegratedSystemInfo), - &size, &frev, &crev); - - if (info == NULL) { - pr_err("Could not retrieve the Integrated System Info Table!\n"); - return -EINVAL; - } - - if (crev != 9) { - pr_err("Unsupported IGP table: %d %d\n", frev, crev); - return -EINVAL; - } - - data->sys_info.bootup_uma_clock = - le32_to_cpu(info->ulBootUpUMAClock); - - data->sys_info.bootup_engine_clock = - le32_to_cpu(info->ulBootUpEngineClock); - - data->sys_info.dentist_vco_freq = - le32_to_cpu(info->ulDentistVCOFreq); - - data->sys_info.system_config = - le32_to_cpu(info->ulSystemConfig); - - data->sys_info.bootup_nb_voltage_index = - le16_to_cpu(info->usBootUpNBVoltage); - - data->sys_info.htc_hyst_lmt = - (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt; - - data->sys_info.htc_tmp_lmt = - (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt; - - if (data->sys_info.htc_tmp_lmt <= - data->sys_info.htc_hyst_lmt) { - pr_err("The htcTmpLmt should be larger than htcHystLmt.\n"); - return -EINVAL; - } - - data->sys_info.nb_dpm_enable = - data->enable_nb_ps_policy && - (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1); - - for (i = 0; i < SMU8_NUM_NBPSTATES; i++) { - if (i < SMU8_NUM_NBPMEMORYCLOCK) { - data->sys_info.nbp_memory_clock[i] = - le32_to_cpu(info->ulNbpStateMemclkFreq[i]); - } - data->sys_info.nbp_n_clock[i] = - le32_to_cpu(info->ulNbpStateNClkFreq[i]); - } - - for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) { - data->sys_info.display_clock[i] = - le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK); - } - - /* Here use 4 levels, make sure not exceed */ - for (i = 0; i < SMU8_NUM_NBPSTATES; i++) { - data->sys_info.nbp_voltage_index[i] = - le16_to_cpu(info->usNBPStateVoltage[i]); - } - - if (!data->sys_info.nb_dpm_enable) { - for (i = 1; i < SMU8_NUM_NBPSTATES; i++) { - if (i < SMU8_NUM_NBPMEMORYCLOCK) { - data->sys_info.nbp_memory_clock[i] = - data->sys_info.nbp_memory_clock[0]; - } - data->sys_info.nbp_n_clock[i] = - data->sys_info.nbp_n_clock[0]; - data->sys_info.nbp_voltage_index[i] = - data->sys_info.nbp_voltage_index[0]; - } - } - - if (le32_to_cpu(info->ulGPUCapInfo) & - SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableDFSBypass); - } - - data->sys_info.uma_channel_number = info->ucUMAChannelNumber; - - smu8_construct_max_power_limits_table (hwmgr, - &hwmgr->dyn_state.max_clock_voltage_on_ac); - - smu8_init_dynamic_state_adjustment_rule_settings(hwmgr, - &info->sDISPCLK_Voltage[0]); - - return result; -} - -static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - data->boot_power_level.engineClock = - data->sys_info.bootup_engine_clock; - - data->boot_power_level.vddcIndex = - (uint8_t)data->sys_info.bootup_nb_voltage_index; - - data->boot_power_level.dsDividerIndex = 0; - data->boot_power_level.ssDividerIndex = 0; - data->boot_power_level.allowGnbSlow = 1; - data->boot_power_level.forceNBPstate = 0; - data->boot_power_level.hysteresis_up = 0; - data->boot_power_level.numSIMDToPowerDown = 0; - data->boot_power_level.display_wm = 0; - data->boot_power_level.vce_wm = 0; - - return 0; -} - -static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) -{ - struct SMU8_Fusion_ClkTable *clock_table; - int ret; - uint32_t i; - void *table = NULL; - pp_atomctrl_clock_dividers_kong dividers; - - struct phm_clock_voltage_dependency_table *vddc_table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - struct phm_clock_voltage_dependency_table *vdd_gfx_table = - hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; - struct phm_acp_clock_voltage_dependency_table *acp_table = - hwmgr->dyn_state.acp_clock_voltage_dependency_table; - struct phm_uvd_clock_voltage_dependency_table *uvd_table = - hwmgr->dyn_state.uvd_clock_voltage_dependency_table; - struct phm_vce_clock_voltage_dependency_table *vce_table = - hwmgr->dyn_state.vce_clock_voltage_dependency_table; - - if (!hwmgr->need_pp_table_upload) - return 0; - - ret = smum_download_powerplay_table(hwmgr, &table); - - PP_ASSERT_WITH_CODE((0 == ret && NULL != table), - "Fail to get clock table from SMU!", return -EINVAL;); - - clock_table = (struct SMU8_Fusion_ClkTable *)table; - - /* patch clock table */ - PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), - "Dependency table entry exceeds max limit!", return -EINVAL;); - PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), - "Dependency table entry exceeds max limit!", return -EINVAL;); - PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), - "Dependency table entry exceeds max limit!", return -EINVAL;); - PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), - "Dependency table entry exceeds max limit!", return -EINVAL;); - PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), - "Dependency table entry exceeds max limit!", return -EINVAL;); - - for (i = 0; i < SMU8_MAX_HARDWARE_POWERLEVELS; i++) { - - /* vddc_sclk */ - clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid = - (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0; - clock_table->SclkBreakdownTable.ClkLevel[i].Frequency = - (i < vddc_table->count) ? vddc_table->entries[i].clk : 0; - - atomctrl_get_engine_pll_dividers_kong(hwmgr, - clock_table->SclkBreakdownTable.ClkLevel[i].Frequency, - ÷rs); - - clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid = - (uint8_t)dividers.pll_post_divider; - - /* vddgfx_sclk */ - clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid = - (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0; - - /* acp breakdown */ - clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid = - (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0; - clock_table->AclkBreakdownTable.ClkLevel[i].Frequency = - (i < acp_table->count) ? acp_table->entries[i].acpclk : 0; - - atomctrl_get_engine_pll_dividers_kong(hwmgr, - clock_table->AclkBreakdownTable.ClkLevel[i].Frequency, - ÷rs); - - clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid = - (uint8_t)dividers.pll_post_divider; - - - /* uvd breakdown */ - clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid = - (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; - clock_table->VclkBreakdownTable.ClkLevel[i].Frequency = - (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; - - atomctrl_get_engine_pll_dividers_kong(hwmgr, - clock_table->VclkBreakdownTable.ClkLevel[i].Frequency, - ÷rs); - - clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid = - (uint8_t)dividers.pll_post_divider; - - clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid = - (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; - clock_table->DclkBreakdownTable.ClkLevel[i].Frequency = - (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0; - - atomctrl_get_engine_pll_dividers_kong(hwmgr, - clock_table->DclkBreakdownTable.ClkLevel[i].Frequency, - ÷rs); - - clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid = - (uint8_t)dividers.pll_post_divider; - - /* vce breakdown */ - clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid = - (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0; - clock_table->EclkBreakdownTable.ClkLevel[i].Frequency = - (i < vce_table->count) ? vce_table->entries[i].ecclk : 0; - - - atomctrl_get_engine_pll_dividers_kong(hwmgr, - clock_table->EclkBreakdownTable.ClkLevel[i].Frequency, - ÷rs); - - clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid = - (uint8_t)dividers.pll_post_divider; - - } - ret = smum_upload_powerplay_table(hwmgr); - - return ret; -} - -static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - unsigned long clock = 0, level; - - if (NULL == table || table->count <= 0) - return -EINVAL; - - data->sclk_dpm.soft_min_clk = table->entries[0].clk; - data->sclk_dpm.hard_min_clk = table->entries[0].clk; - - level = smu8_get_max_sclk_level(hwmgr) - 1; - - if (level < table->count) - clock = table->entries[level].clk; - else - clock = table->entries[table->count - 1].clk; - - data->sclk_dpm.soft_max_clk = clock; - data->sclk_dpm.hard_max_clk = clock; - - return 0; -} - -static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_uvd_clock_voltage_dependency_table *table = - hwmgr->dyn_state.uvd_clock_voltage_dependency_table; - unsigned long clock = 0; - uint32_t level; - - if (NULL == table || table->count <= 0) - return -EINVAL; - - data->uvd_dpm.soft_min_clk = 0; - data->uvd_dpm.hard_min_clk = 0; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel, &level); - - if (level < table->count) - clock = table->entries[level].vclk; - else - clock = table->entries[table->count - 1].vclk; - - data->uvd_dpm.soft_max_clk = clock; - data->uvd_dpm.hard_max_clk = clock; - - return 0; -} - -static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_vce_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vce_clock_voltage_dependency_table; - unsigned long clock = 0; - uint32_t level; - - if (NULL == table || table->count <= 0) - return -EINVAL; - - data->vce_dpm.soft_min_clk = 0; - data->vce_dpm.hard_min_clk = 0; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel, &level); - - if (level < table->count) - clock = table->entries[level].ecclk; - else - clock = table->entries[table->count - 1].ecclk; - - data->vce_dpm.soft_max_clk = clock; - data->vce_dpm.hard_max_clk = clock; - - return 0; -} - -static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_acp_clock_voltage_dependency_table *table = - hwmgr->dyn_state.acp_clock_voltage_dependency_table; - unsigned long clock = 0; - uint32_t level; - - if (NULL == table || table->count <= 0) - return -EINVAL; - - data->acp_dpm.soft_min_clk = 0; - data->acp_dpm.hard_min_clk = 0; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel, &level); - - if (level < table->count) - clock = table->entries[level].acpclk; - else - clock = table->entries[table->count - 1].acpclk; - - data->acp_dpm.soft_max_clk = clock; - data->acp_dpm.hard_max_clk = clock; - return 0; -} - -static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - data->uvd_power_gated = false; - data->vce_power_gated = false; - data->samu_power_gated = false; -#ifdef CONFIG_DRM_AMD_ACP - data->acp_power_gated = false; -#else - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); - data->acp_power_gated = true; -#endif - -} - -static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - data->low_sclk_interrupt_threshold = 0; -} - -static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - - unsigned long clock = 0; - unsigned long level; - unsigned long stable_pstate_sclk; - unsigned long percentage; - - data->sclk_dpm.soft_min_clk = table->entries[0].clk; - level = smu8_get_max_sclk_level(hwmgr) - 1; - - if (level < table->count) - data->sclk_dpm.soft_max_clk = table->entries[level].clk; - else - data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk; - - clock = hwmgr->display_config->min_core_set_clock; - if (clock == 0) - pr_debug("min_core_set_clock not set\n"); - - if (data->sclk_dpm.hard_min_clk != clock) { - data->sclk_dpm.hard_min_clk = clock; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkHardMin, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.hard_min_clk, - PPSMC_MSG_SetSclkHardMin), - NULL); - } - - clock = data->sclk_dpm.soft_min_clk; - - /* update minimum clocks for Stable P-State feature */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { - percentage = 75; - /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */ - stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * - percentage) / 100; - - if (clock < stable_pstate_sclk) - clock = stable_pstate_sclk; - } - - if (data->sclk_dpm.soft_min_clk != clock) { - data->sclk_dpm.soft_min_clk = clock; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMin, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_min_clk, - PPSMC_MSG_SetSclkSoftMin), - NULL); - } - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState) && - data->sclk_dpm.soft_max_clk != clock) { - data->sclk_dpm.soft_max_clk = clock; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMax, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_max_clk, - PPSMC_MSG_SetSclkSoftMax), - NULL); - } - - return 0; -} - -static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep)) { - uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; - if (clks == 0) - clks = SMU8_MIN_DEEP_SLEEP_SCLK; - - PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetMinDeepSleepSclk, - clks, - NULL); - } - - return 0; -} - -static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = - hwmgr->backend; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetWatermarkFrequency, - data->sclk_dpm.soft_max_clk, - NULL); - - return 0; -} - -static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock) -{ - struct smu8_hwmgr *hw_data = hwmgr->backend; - - if (hw_data->is_nb_dpm_enabled) { - if (enable) { - PP_DBG_LOG("enable Low Memory PState.\n"); - - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_EnableLowMemoryPstate, - (lock ? 1 : 0), - NULL); - } else { - PP_DBG_LOG("disable Low Memory PState.\n"); - - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DisableLowMemoryPstate, - (lock ? 1 : 0), - NULL); - } - } - - return 0; -} - -static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - - struct smu8_hwmgr *data = hwmgr->backend; - unsigned long dpm_features = 0; - - if (data->is_nb_dpm_enabled) { - smu8_nbdpm_pstate_enable_disable(hwmgr, true, true); - dpm_features |= NB_DPM_MASK; - ret = smum_send_msg_to_smc_with_parameter( - hwmgr, - PPSMC_MSG_DisableAllSmuFeatures, - dpm_features, - NULL); - if (ret == 0) - data->is_nb_dpm_enabled = false; - } - - return ret; -} - -static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - - struct smu8_hwmgr *data = hwmgr->backend; - unsigned long dpm_features = 0; - - if (!data->is_nb_dpm_enabled) { - PP_DBG_LOG("enabling ALL SMU features.\n"); - dpm_features |= NB_DPM_MASK; - ret = smum_send_msg_to_smc_with_parameter( - hwmgr, - PPSMC_MSG_EnableAllSmuFeatures, - dpm_features, - NULL); - if (ret == 0) - data->is_nb_dpm_enabled = true; - } - - return ret; -} - -static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input) -{ - bool disable_switch; - bool enable_low_mem_state; - struct smu8_hwmgr *hw_data = hwmgr->backend; - const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input; - const struct smu8_power_state *pnew_state = cast_const_smu8_power_state(states->pnew_state); - - if (hw_data->sys_info.nb_dpm_enable) { - disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false; - enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true; - - if (pnew_state->action == FORCE_HIGH) - smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch); - else if (pnew_state->action == CANCEL_FORCE_HIGH) - smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch); - else - smu8_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch); - } - return 0; -} - -static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) -{ - int ret = 0; - - smu8_update_sclk_limit(hwmgr); - smu8_set_deep_sleep_sclk_threshold(hwmgr); - smu8_set_watermark_threshold(hwmgr); - ret = smu8_enable_nb_dpm(hwmgr); - if (ret) - return ret; - smu8_update_low_mem_pstate(hwmgr, input); - - return 0; -} - - -static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr) -{ - int ret; - - ret = smu8_upload_pptable_to_smu(hwmgr); - if (ret) - return ret; - ret = smu8_init_sclk_limit(hwmgr); - if (ret) - return ret; - ret = smu8_init_uvd_limit(hwmgr); - if (ret) - return ret; - ret = smu8_init_vce_limit(hwmgr); - if (ret) - return ret; - ret = smu8_init_acp_limit(hwmgr); - if (ret) - return ret; - - smu8_init_power_gate_state(hwmgr); - smu8_init_sclk_threshold(hwmgr); - - return 0; -} - -static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *hw_data = hwmgr->backend; - - hw_data->disp_clk_bypass_pending = false; - hw_data->disp_clk_bypass = false; -} - -static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *hw_data = hwmgr->backend; - - hw_data->is_nb_dpm_enabled = false; -} - -static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *hw_data = hwmgr->backend; - - hw_data->cc6_settings.cc6_setting_changed = false; - hw_data->cc6_settings.cpu_pstate_separation_time = 0; - hw_data->cc6_settings.cpu_cc6_disable = false; - hw_data->cc6_settings.cpu_pstate_disable = false; -} - -static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr) -{ - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0, - SMU8_VOTINGRIGHTSCLIENTS_DFLT0); -} - -static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr) -{ - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0, 0); -} - -static int smu8_start_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - data->dpm_flags |= DPMFlags_SCLK_Enabled; - - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_EnableAllSmuFeatures, - SCLK_DPM_MASK, - NULL); -} - -static int smu8_stop_dpm(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - struct smu8_hwmgr *data = hwmgr->backend; - unsigned long dpm_features = 0; - - if (data->dpm_flags & DPMFlags_SCLK_Enabled) { - dpm_features |= SCLK_DPM_MASK; - data->dpm_flags &= ~DPMFlags_SCLK_Enabled; - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DisableAllSmuFeatures, - dpm_features, - NULL); - } - return ret; -} - -static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - data->sclk_dpm.soft_min_clk = data->sys_info.bootup_engine_clock; - data->sclk_dpm.soft_max_clk = data->sys_info.bootup_engine_clock; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMin, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_min_clk, - PPSMC_MSG_SetSclkSoftMin), - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMax, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_max_clk, - PPSMC_MSG_SetSclkSoftMax), - NULL); - - return 0; -} - -static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - data->acp_boot_level = 0xff; -} - -static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - smu8_program_voting_clients(hwmgr); - if (smu8_start_dpm(hwmgr)) - return -EINVAL; - smu8_program_bootup_state(hwmgr); - smu8_reset_acp_boot_level(hwmgr); - - return 0; -} - -static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - smu8_disable_nb_dpm(hwmgr); - - smu8_clear_voting_clients(hwmgr); - if (smu8_stop_dpm(hwmgr)) - return -EINVAL; - - return 0; -} - -static int smu8_power_off_asic(struct pp_hwmgr *hwmgr) -{ - smu8_disable_dpm_tasks(hwmgr); - smu8_power_up_display_clock_sys_pll(hwmgr); - smu8_clear_nb_dpm_flag(hwmgr); - smu8_reset_cc6_data(hwmgr); - return 0; -} - -static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, - struct pp_power_state *prequest_ps, - const struct pp_power_state *pcurrent_ps) -{ - struct smu8_power_state *smu8_ps = - cast_smu8_power_state(&prequest_ps->hardware); - - const struct smu8_power_state *smu8_current_ps = - cast_const_smu8_power_state(&pcurrent_ps->hardware); - - struct smu8_hwmgr *data = hwmgr->backend; - struct PP_Clocks clocks = {0, 0, 0, 0}; - bool force_high; - - smu8_ps->need_dfs_bypass = true; - - data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); - - clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? - hwmgr->display_config->min_mem_set_clock : - data->sys_info.nbp_memory_clock[1]; - - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; - - force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]) - || (hwmgr->display_config->num_display >= 3); - - smu8_ps->action = smu8_current_ps->action; - - if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - smu8_nbdpm_pstate_enable_disable(hwmgr, false, false); - else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) - smu8_nbdpm_pstate_enable_disable(hwmgr, false, true); - else if (!force_high && (smu8_ps->action == FORCE_HIGH)) - smu8_ps->action = CANCEL_FORCE_HIGH; - else if (force_high && (smu8_ps->action != FORCE_HIGH)) - smu8_ps->action = FORCE_HIGH; - else - smu8_ps->action = DO_NOTHING; - - return 0; -} - -static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr) -{ - int result = 0; - struct smu8_hwmgr *data; - - data = kzalloc(sizeof(struct smu8_hwmgr), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - - hwmgr->backend = data; - - result = smu8_initialize_dpm_defaults(hwmgr); - if (result != 0) { - pr_err("smu8_initialize_dpm_defaults failed\n"); - return result; - } - - result = smu8_get_system_info_data(hwmgr); - if (result != 0) { - pr_err("smu8_get_system_info_data failed\n"); - return result; - } - - smu8_construct_boot_state(hwmgr); - - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = SMU8_MAX_HARDWARE_POWERLEVELS; - - return result; -} - -static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) -{ - if (hwmgr != NULL) { - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - - kfree(hwmgr->backend); - hwmgr->backend = NULL; - } - return 0; -} - -static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMin, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_max_clk, - PPSMC_MSG_SetSclkSoftMin), - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMax, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_max_clk, - PPSMC_MSG_SetSclkSoftMax), - NULL); - - return 0; -} - -static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - unsigned long clock = 0, level; - - if (NULL == table || table->count <= 0) - return -EINVAL; - - data->sclk_dpm.soft_min_clk = table->entries[0].clk; - data->sclk_dpm.hard_min_clk = table->entries[0].clk; - hwmgr->pstate_sclk = table->entries[0].clk; - hwmgr->pstate_mclk = 0; - - level = smu8_get_max_sclk_level(hwmgr) - 1; - - if (level < table->count) - clock = table->entries[level].clk; - else - clock = table->entries[table->count - 1].clk; - - data->sclk_dpm.soft_max_clk = clock; - data->sclk_dpm.hard_max_clk = clock; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMin, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_min_clk, - PPSMC_MSG_SetSclkSoftMin), - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMax, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_max_clk, - PPSMC_MSG_SetSclkSoftMax), - NULL); - - return 0; -} - -static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMax, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_min_clk, - PPSMC_MSG_SetSclkSoftMax), - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMin, - smu8_get_sclk_level(hwmgr, - data->sclk_dpm.soft_min_clk, - PPSMC_MSG_SetSclkSoftMin), - NULL); - - return 0; -} - -static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, - enum amd_dpm_forced_level level) -{ - int ret = 0; - - switch (level) { - case AMD_DPM_FORCED_LEVEL_HIGH: - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: - ret = smu8_phm_force_dpm_highest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_LOW: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: - ret = smu8_phm_force_dpm_lowest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_AUTO: - ret = smu8_phm_unforce_dpm_levels(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_MANUAL: - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: - default: - break; - } - - return ret; -} - -static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) -{ - if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF, NULL); - return 0; -} - -static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) -{ - if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) { - return smum_send_msg_to_smc_with_parameter( - hwmgr, - PPSMC_MSG_UVDPowerON, - PP_CAP(PHM_PlatformCaps_UVDDynamicPowerGating) ? 1 : 0, - NULL); - } - - return 0; -} - -static int smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_vce_clock_voltage_dependency_table *ptable = - hwmgr->dyn_state.vce_clock_voltage_dependency_table; - - /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */ - if (PP_CAP(PHM_PlatformCaps_StablePState) || - hwmgr->en_umd_pstate) { - data->vce_dpm.hard_min_clk = - ptable->entries[ptable->count - 1].ecclk; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetEclkHardMin, - smu8_get_eclk_level(hwmgr, - data->vce_dpm.hard_min_clk, - PPSMC_MSG_SetEclkHardMin), - NULL); - } else { - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetEclkHardMin, - 0, - NULL); - /* disable ECLK DPM 0. Otherwise VCE could hang if - * switching SCLK from DPM 0 to 6/7 */ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetEclkSoftMin, - 1, - NULL); - } - return 0; -} - -static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) -{ - if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) - return smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_VCEPowerOFF, - NULL); - return 0; -} - -static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr) -{ - if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) - return smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_VCEPowerON, - NULL); - return 0; -} - -static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - return data->sys_info.bootup_uma_clock; -} - -static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct pp_power_state *ps; - struct smu8_power_state *smu8_ps; - - if (hwmgr == NULL) - return -EINVAL; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - smu8_ps = cast_smu8_power_state(&ps->hardware); - - if (low) - return smu8_ps->levels[0].engineClock; - else - return smu8_ps->levels[smu8_ps->level-1].engineClock; -} - -static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); - - smu8_ps->level = 1; - smu8_ps->nbps_flags = 0; - smu8_ps->bapm_flags = 0; - smu8_ps->levels[0] = data->boot_power_level; - - return 0; -} - -static int smu8_dpm_get_pp_table_entry_callback( - struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps, - unsigned int index, - const void *clock_info) -{ - struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); - - const ATOM_PPLIB_CZ_CLOCK_INFO *smu8_clock_info = clock_info; - - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - uint8_t clock_info_index = smu8_clock_info->index; - - if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) - clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); - - smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; - smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v; - - smu8_ps->level = index + 1; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - smu8_ps->levels[index].dsDividerIndex = 5; - smu8_ps->levels[index].ssDividerIndex = 5; - } - - return 0; -} - -static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) -{ - int result; - unsigned long ret = 0; - - result = pp_tables_get_num_of_entries(hwmgr, &ret); - - return result ? 0 : ret; -} - -static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, - unsigned long entry, struct pp_power_state *ps) -{ - int result; - struct smu8_power_state *smu8_ps; - - ps->hardware.magic = smu8_magic; - - smu8_ps = cast_smu8_power_state(&(ps->hardware)); - - result = pp_tables_get_entry(hwmgr, entry, ps, - smu8_dpm_get_pp_table_entry_callback); - - smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; - smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; - - return result; -} - -static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr) -{ - return sizeof(struct smu8_power_state); -} - -static void smu8_hw_print_display_cfg( - const struct cc6_settings *cc6_settings) -{ - PP_DBG_LOG("New Display Configuration:\n"); - - PP_DBG_LOG(" cpu_cc6_disable: %d\n", - cc6_settings->cpu_cc6_disable); - PP_DBG_LOG(" cpu_pstate_disable: %d\n", - cc6_settings->cpu_pstate_disable); - PP_DBG_LOG(" nb_pstate_switch_disable: %d\n", - cc6_settings->nb_pstate_switch_disable); - PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n", - cc6_settings->cpu_pstate_separation_time); -} - - static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr) -{ - struct smu8_hwmgr *hw_data = hwmgr->backend; - uint32_t data = 0; - - if (hw_data->cc6_settings.cc6_setting_changed) { - - hw_data->cc6_settings.cc6_setting_changed = false; - - smu8_hw_print_display_cfg(&hw_data->cc6_settings); - - data |= (hw_data->cc6_settings.cpu_pstate_separation_time - & PWRMGT_SEPARATION_TIME_MASK) - << PWRMGT_SEPARATION_TIME_SHIFT; - - data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0) - << PWRMGT_DISABLE_CPU_CSTATES_SHIFT; - - data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0) - << PWRMGT_DISABLE_CPU_PSTATES_SHIFT; - - PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n", - data); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetDisplaySizePowerParams, - data, - NULL); - } - - return 0; -} - - -static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, - bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) -{ - struct smu8_hwmgr *hw_data = hwmgr->backend; - - if (separation_time != - hw_data->cc6_settings.cpu_pstate_separation_time || - cc6_disable != hw_data->cc6_settings.cpu_cc6_disable || - pstate_disable != hw_data->cc6_settings.cpu_pstate_disable || - pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) { - - hw_data->cc6_settings.cc6_setting_changed = true; - - hw_data->cc6_settings.cpu_pstate_separation_time = - separation_time; - hw_data->cc6_settings.cpu_cc6_disable = - cc6_disable; - hw_data->cc6_settings.cpu_pstate_disable = - pstate_disable; - hw_data->cc6_settings.nb_pstate_switch_disable = - pstate_switch_disable; - - } - - return 0; -} - -static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr, - struct amd_pp_simple_clock_info *info) -{ - uint32_t i; - const struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dep_on_dal_pwrl; - const struct phm_clock_and_voltage_limits *limits = - &hwmgr->dyn_state.max_clock_voltage_on_ac; - - info->engine_max_clock = limits->sclk; - info->memory_max_clock = limits->mclk; - - for (i = table->count - 1; i > 0; i--) { - if (limits->vddc >= table->entries[i].v) { - info->level = table->entries[i].clk; - return 0; - } - } - return -EINVAL; -} - -static int smu8_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask) -{ - switch (type) { - case PP_SCLK: - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMin, - mask, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSclkSoftMax, - mask, - NULL); - break; - default: - break; - } - - return 0; -} - -static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_clock_voltage_dependency_table *sclk_table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - int i, now, size = 0; - - switch (type) { - case PP_SCLK: - now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, - ixTARGET_AND_CURRENT_PROFILE_INDEX), - TARGET_AND_CURRENT_PROFILE_INDEX, - CURR_SCLK_INDEX); - - for (i = 0; i < sclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, sclk_table->entries[i].clk / 100, - (i == now) ? "*" : ""); - break; - case PP_MCLK: - now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, - ixTARGET_AND_CURRENT_PROFILE_INDEX), - TARGET_AND_CURRENT_PROFILE_INDEX, - CURR_MCLK_INDEX); - - for (i = SMU8_NUM_NBPMEMORYCLOCK; i > 0; i--) - size += sprintf(buf + size, "%d: %uMhz %s\n", - SMU8_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100, - (SMU8_NUM_NBPMEMORYCLOCK-i == now) ? "*" : ""); - break; - default: - break; - } - return size; -} - -static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, - PHM_PerformanceLevelDesignation designation, uint32_t index, - PHM_PerformanceLevel *level) -{ - const struct smu8_power_state *ps; - struct smu8_hwmgr *data; - uint32_t level_index; - uint32_t i; - - if (level == NULL || hwmgr == NULL || state == NULL) - return -EINVAL; - - data = hwmgr->backend; - ps = cast_const_smu8_power_state(state); - - level_index = index > ps->level - 1 ? ps->level - 1 : index; - level->coreClock = ps->levels[level_index].engineClock; - - if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { - for (i = 1; i < ps->level; i++) { - if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { - level->coreClock = ps->levels[i].engineClock; - break; - } - } - } - - if (level_index == 0) - level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; - else - level->memory_clock = data->sys_info.nbp_memory_clock[0]; - - level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4; - level->nonLocalMemoryFreq = 0; - level->nonLocalMemoryWidth = 0; - - return 0; -} - -static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, - const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) -{ - const struct smu8_power_state *ps = cast_const_smu8_power_state(state); - - clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); - clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex)); - - return 0; -} - -static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks) -{ - struct smu8_hwmgr *data = hwmgr->backend; - int i; - struct phm_clock_voltage_dependency_table *table; - - clocks->count = smu8_get_max_sclk_level(hwmgr); - switch (type) { - case amd_pp_disp_clock: - for (i = 0; i < clocks->count; i++) - clocks->clock[i] = data->sys_info.display_clock[i] * 10; - break; - case amd_pp_sys_clock: - table = hwmgr->dyn_state.vddc_dependency_on_sclk; - for (i = 0; i < clocks->count; i++) - clocks->clock[i] = table->entries[i].clk * 10; - break; - case amd_pp_mem_clock: - clocks->count = SMU8_NUM_NBPMEMORYCLOCK; - for (i = 0; i < clocks->count; i++) - clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10; - break; - default: - return -1; - } - - return 0; -} - -static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) -{ - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - unsigned long level; - const struct phm_clock_and_voltage_limits *limits = - &hwmgr->dyn_state.max_clock_voltage_on_ac; - - if ((NULL == table) || (table->count <= 0) || (clocks == NULL)) - return -EINVAL; - - level = smu8_get_max_sclk_level(hwmgr) - 1; - - if (level < table->count) - clocks->engine_max_clock = table->entries[level].clk; - else - clocks->engine_max_clock = table->entries[table->count - 1].clk; - - clocks->memory_max_clock = limits->mclk; - - return 0; -} - -static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr) -{ - int actual_temp = 0; - uint32_t val = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP); - uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP); - - if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL)) - actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - else - actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return actual_temp; -} - -static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx, - void *value, int *size) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - - struct phm_vce_clock_voltage_dependency_table *vce_table = - hwmgr->dyn_state.vce_clock_voltage_dependency_table; - - struct phm_uvd_clock_voltage_dependency_table *uvd_table = - hwmgr->dyn_state.uvd_clock_voltage_dependency_table; - - uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX), - TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX); - uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), - TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX); - uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), - TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX); - - uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; - uint16_t vddnb, vddgfx; - int result; - - /* size must be at least 4 bytes for all sensors */ - if (*size < 4) - return -EINVAL; - *size = 4; - - switch (idx) { - case AMDGPU_PP_SENSOR_GFX_SCLK: - if (sclk_index < NUM_SCLK_LEVELS) { - sclk = table->entries[sclk_index].clk; - *((uint32_t *)value) = sclk; - return 0; - } - return -EINVAL; - case AMDGPU_PP_SENSOR_VDDNB: - tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & - CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT; - vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4; - *((uint32_t *)value) = vddnb; - return 0; - case AMDGPU_PP_SENSOR_VDDGFX: - tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & - CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT; - vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4; - *((uint32_t *)value) = vddgfx; - return 0; - case AMDGPU_PP_SENSOR_UVD_VCLK: - if (!data->uvd_power_gated) { - if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { - return -EINVAL; - } else { - vclk = uvd_table->entries[uvd_index].vclk; - *((uint32_t *)value) = vclk; - return 0; - } - } - *((uint32_t *)value) = 0; - return 0; - case AMDGPU_PP_SENSOR_UVD_DCLK: - if (!data->uvd_power_gated) { - if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { - return -EINVAL; - } else { - dclk = uvd_table->entries[uvd_index].dclk; - *((uint32_t *)value) = dclk; - return 0; - } - } - *((uint32_t *)value) = 0; - return 0; - case AMDGPU_PP_SENSOR_VCE_ECCLK: - if (!data->vce_power_gated) { - if (vce_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { - return -EINVAL; - } else { - ecclk = vce_table->entries[vce_index].ecclk; - *((uint32_t *)value) = ecclk; - return 0; - } - } - *((uint32_t *)value) = 0; - return 0; - case AMDGPU_PP_SENSOR_GPU_LOAD: - result = smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_GetAverageGraphicsActivity, - &activity_percent); - if (0 == result) { - activity_percent = activity_percent > 100 ? 100 : activity_percent; - } else { - activity_percent = 50; - } - *((uint32_t *)value) = activity_percent; - return 0; - case AMDGPU_PP_SENSOR_UVD_POWER: - *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; - return 0; - case AMDGPU_PP_SENSOR_VCE_POWER: - *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; - return 0; - case AMDGPU_PP_SENSOR_GPU_TEMP: - *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr); - return 0; - default: - return -EINVAL; - } -} - -static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, - uint32_t virtual_addr_low, - uint32_t virtual_addr_hi, - uint32_t mc_addr_low, - uint32_t mc_addr_hi, - uint32_t size) -{ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramAddrHiVirtual, - mc_addr_hi, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramAddrLoVirtual, - mc_addr_low, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramAddrHiPhysical, - virtual_addr_hi, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramAddrLoPhysical, - virtual_addr_low, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramBufferSize, - size, - NULL); - return 0; -} - -static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *thermal_data) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); - - thermal_data->max = (data->thermal_auto_throttling_treshold + - data->sys_info.htc_hyst_lmt) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return 0; -} - -static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct smu8_hwmgr *data = hwmgr->backend; - uint32_t dpm_features = 0; - - if (enable && - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDPM)) { - data->dpm_flags |= DPMFlags_UVD_Enabled; - dpm_features |= UVD_DPM_MASK; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_EnableAllSmuFeatures, - dpm_features, - NULL); - } else { - dpm_features |= UVD_DPM_MASK; - data->dpm_flags &= ~DPMFlags_UVD_Enabled; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DisableAllSmuFeatures, - dpm_features, - NULL); - } - return 0; -} - -static int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct smu8_hwmgr *data = hwmgr->backend; - struct phm_uvd_clock_voltage_dependency_table *ptable = - hwmgr->dyn_state.uvd_clock_voltage_dependency_table; - - if (!bgate) { - /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */ - if (PP_CAP(PHM_PlatformCaps_StablePState) || - hwmgr->en_umd_pstate) { - data->uvd_dpm.hard_min_clk = - ptable->entries[ptable->count - 1].vclk; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetUvdHardMin, - smu8_get_uvd_level(hwmgr, - data->uvd_dpm.hard_min_clk, - PPSMC_MSG_SetUvdHardMin), - NULL); - - smu8_enable_disable_uvd_dpm(hwmgr, true); - } else { - smu8_enable_disable_uvd_dpm(hwmgr, true); - } - } else { - smu8_enable_disable_uvd_dpm(hwmgr, false); - } - - return 0; -} - -static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct smu8_hwmgr *data = hwmgr->backend; - uint32_t dpm_features = 0; - - if (enable && phm_cap_enabled( - hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEDPM)) { - data->dpm_flags |= DPMFlags_VCE_Enabled; - dpm_features |= VCE_DPM_MASK; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_EnableAllSmuFeatures, - dpm_features, - NULL); - } else { - dpm_features |= VCE_DPM_MASK; - data->dpm_flags &= ~DPMFlags_VCE_Enabled; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DisableAllSmuFeatures, - dpm_features, - NULL); - } - - return 0; -} - - -static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - if (data->acp_power_gated == bgate) - return; - - if (bgate) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); - else - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON, NULL); -} - -static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - data->uvd_power_gated = bgate; - - if (bgate) { - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_GATE); - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); - smu8_dpm_update_uvd_dpm(hwmgr, true); - smu8_dpm_powerdown_uvd(hwmgr); - } else { - smu8_dpm_powerup_uvd(hwmgr); - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_UNGATE); - smu8_dpm_update_uvd_dpm(hwmgr, false); - } - -} - -static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct smu8_hwmgr *data = hwmgr->backend; - - if (bgate) { - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_GATE); - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_GATE); - smu8_enable_disable_vce_dpm(hwmgr, false); - smu8_dpm_powerdown_vce(hwmgr); - data->vce_power_gated = true; - } else { - smu8_dpm_powerup_vce(hwmgr); - data->vce_power_gated = false; - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_UNGATE); - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_UNGATE); - smu8_dpm_update_vce_dpm(hwmgr); - smu8_enable_disable_vce_dpm(hwmgr, true); - } -} - -static const struct pp_hwmgr_func smu8_hwmgr_funcs = { - .backend_init = smu8_hwmgr_backend_init, - .backend_fini = smu8_hwmgr_backend_fini, - .apply_state_adjust_rules = smu8_apply_state_adjust_rules, - .force_dpm_level = smu8_dpm_force_dpm_level, - .get_power_state_size = smu8_get_power_state_size, - .powerdown_uvd = smu8_dpm_powerdown_uvd, - .powergate_uvd = smu8_dpm_powergate_uvd, - .powergate_vce = smu8_dpm_powergate_vce, - .powergate_acp = smu8_dpm_powergate_acp, - .get_mclk = smu8_dpm_get_mclk, - .get_sclk = smu8_dpm_get_sclk, - .patch_boot_state = smu8_dpm_patch_boot_state, - .get_pp_table_entry = smu8_dpm_get_pp_table_entry, - .get_num_of_pp_table_entries = smu8_dpm_get_num_of_pp_table_entries, - .set_cpu_power_state = smu8_set_cpu_power_state, - .store_cc6_data = smu8_store_cc6_data, - .force_clock_level = smu8_force_clock_level, - .print_clock_levels = smu8_print_clock_levels, - .get_dal_power_level = smu8_get_dal_power_level, - .get_performance_level = smu8_get_performance_level, - .get_current_shallow_sleep_clocks = smu8_get_current_shallow_sleep_clocks, - .get_clock_by_type = smu8_get_clock_by_type, - .get_max_high_clocks = smu8_get_max_high_clocks, - .read_sensor = smu8_read_sensor, - .power_off_asic = smu8_power_off_asic, - .asic_setup = smu8_setup_asic_task, - .dynamic_state_management_enable = smu8_enable_dpm_tasks, - .power_state_set = smu8_set_power_state_tasks, - .dynamic_state_management_disable = smu8_disable_dpm_tasks, - .notify_cac_buffer_info = smu8_notify_cac_buffer_info, - .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable, - .get_thermal_temperature_range = smu8_get_thermal_temperature_range, -}; - -int smu8_init_function_pointers(struct pp_hwmgr *hwmgr) -{ - hwmgr->hwmgr_func = &smu8_hwmgr_funcs; - hwmgr->pptable_func = &pptable_funcs; - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h deleted file mode 100644 index 05a06083e1b8..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _SMU8_HWMGR_H_ -#define _SMU8_HWMGR_H_ - -#include "cgs_common.h" -#include "ppatomctrl.h" - -#define SMU8_NUM_NBPSTATES 4 -#define SMU8_NUM_NBPMEMORYCLOCK 2 -#define MAX_DISPLAY_CLOCK_LEVEL 8 -#define SMU8_MAX_HARDWARE_POWERLEVELS 8 -#define SMU8_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 -#define SMU8_MIN_DEEP_SLEEP_SCLK 800 - -/* Carrizo device IDs */ -#define DEVICE_ID_CZ_9870 0x9870 -#define DEVICE_ID_CZ_9874 0x9874 -#define DEVICE_ID_CZ_9875 0x9875 -#define DEVICE_ID_CZ_9876 0x9876 -#define DEVICE_ID_CZ_9877 0x9877 - -struct smu8_dpm_entry { - uint32_t soft_min_clk; - uint32_t hard_min_clk; - uint32_t soft_max_clk; - uint32_t hard_max_clk; -}; - -struct smu8_sys_info { - uint32_t bootup_uma_clock; - uint32_t bootup_engine_clock; - uint32_t dentist_vco_freq; - uint32_t nb_dpm_enable; - uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK]; - uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES]; - uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES]; - uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL]; - uint16_t bootup_nb_voltage_index; - uint8_t htc_tmp_lmt; - uint8_t htc_hyst_lmt; - uint32_t system_config; - uint32_t uma_channel_number; -}; - -#define MAX_DISPLAYPHY_IDS 0x8 -#define DISPLAYPHY_LANEMASK 0xF -#define UNKNOWN_TRANSMITTER_PHY_ID (-1) - -#define DISPLAYPHY_PHYID_SHIFT 24 -#define DISPLAYPHY_LANESELECT_SHIFT 16 - -#define DISPLAYPHY_RX_SELECT 0x1 -#define DISPLAYPHY_TX_SELECT 0x2 -#define DISPLAYPHY_CORE_SELECT 0x4 - -#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \ - (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \ - ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \ - ((rx) ? DISPLAYPHY_RX_SELECT : 0) | \ - ((tx) ? DISPLAYPHY_TX_SELECT : 0) | \ - ((core) ? DISPLAYPHY_CORE_SELECT : 0)) - -struct smu8_display_phy_info_entry { - uint8_t phy_present; - uint8_t active_lane_mapping; - uint8_t display_config_type; - uint8_t active_number_of_lanes; -}; - -#define SMU8_MAX_DISPLAYPHY_IDS 10 - -struct smu8_display_phy_info { - bool display_phy_access_initialized; - struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS]; -}; - -struct smu8_power_level { - uint32_t engineClock; - uint8_t vddcIndex; - uint8_t dsDividerIndex; - uint8_t ssDividerIndex; - uint8_t allowGnbSlow; - uint8_t forceNBPstate; - uint8_t display_wm; - uint8_t vce_wm; - uint8_t numSIMDToPowerDown; - uint8_t hysteresis_up; - uint8_t rsv[3]; -}; - -struct smu8_uvd_clocks { - uint32_t vclk; - uint32_t dclk; - uint32_t vclk_low_divider; - uint32_t vclk_high_divider; - uint32_t dclk_low_divider; - uint32_t dclk_high_divider; -}; - -enum smu8_pstate_previous_action { - DO_NOTHING = 1, - FORCE_HIGH, - CANCEL_FORCE_HIGH -}; - -struct pp_disable_nb_ps_flags { - union { - struct { - uint32_t entry : 1; - uint32_t display : 1; - uint32_t driver: 1; - uint32_t vce : 1; - uint32_t uvd : 1; - uint32_t acp : 1; - uint32_t reserved: 26; - } bits; - uint32_t u32All; - }; -}; - -struct smu8_power_state { - unsigned int magic; - uint32_t level; - struct smu8_uvd_clocks uvd_clocks; - uint32_t evclk; - uint32_t ecclk; - uint32_t samclk; - uint32_t acpclk; - bool need_dfs_bypass; - uint32_t nbps_flags; - uint32_t bapm_flags; - uint8_t dpm_0_pg_nb_ps_low; - uint8_t dpm_0_pg_nb_ps_high; - uint8_t dpm_x_nb_ps_low; - uint8_t dpm_x_nb_ps_high; - enum smu8_pstate_previous_action action; - struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS]; - struct pp_disable_nb_ps_flags disable_nb_ps_flag; -}; - -#define DPMFlags_SCLK_Enabled 0x00000001 -#define DPMFlags_UVD_Enabled 0x00000002 -#define DPMFlags_VCE_Enabled 0x00000004 -#define DPMFlags_ACP_Enabled 0x00000008 -#define DPMFlags_ForceHighestValid 0x40000000 -#define DPMFlags_Debug 0x80000000 - -#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 /* bit 0 */ -#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */ -#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */ - -struct cc6_settings { - bool cc6_setting_changed; - bool nb_pstate_switch_disable;/* controls NB PState switch */ - bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ - bool cpu_pstate_disable; - uint32_t cpu_pstate_separation_time; -}; - -struct smu8_hwmgr { - uint32_t dpm_interval; - - uint32_t voltage_drop_threshold; - - uint32_t voting_rights_clients; - - uint32_t disable_driver_thermal_policy; - - uint32_t static_screen_threshold; - - uint32_t gfx_power_gating_threshold; - - uint32_t activity_hysteresis; - uint32_t bootup_sclk_divider; - uint32_t gfx_ramp_step; - uint32_t gfx_ramp_delay; /* in micro-seconds */ - - uint32_t thermal_auto_throttling_treshold; - - struct smu8_sys_info sys_info; - - struct smu8_power_level boot_power_level; - struct smu8_power_state *smu8_current_ps; - struct smu8_power_state *smu8_requested_ps; - - uint32_t mgcg_cgtt_local0; - uint32_t mgcg_cgtt_local1; - - uint32_t tdr_clock; /* in 10khz unit */ - - uint32_t ddi_power_gating_disabled; - uint32_t disable_gfx_power_gating_in_uvd; - uint32_t disable_nb_ps3_in_battery; - - uint32_t lock_nb_ps_in_uvd_play_back; - - struct smu8_display_phy_info display_phy_info; - uint32_t vce_slow_sclk_threshold; /* default 200mhz */ - uint32_t dce_slow_sclk_threshold; /* default 300mhz */ - uint32_t min_sclk_did; /* minimum sclk divider */ - - bool disp_clk_bypass; - bool disp_clk_bypass_pending; - uint32_t bapm_enabled; - uint32_t clock_slow_down_freq; - uint32_t skip_clock_slow_down; - uint32_t enable_nb_ps_policy; - uint32_t voltage_drop_in_dce_power_gating; - uint32_t uvd_dpm_interval; - uint32_t override_dynamic_mgpg; - uint32_t lclk_deep_enabled; - - uint32_t uvd_performance; - - bool video_start; - bool battery_state; - uint32_t lowest_valid; - uint32_t highest_valid; - uint32_t high_voltage_threshold; - uint32_t is_nb_dpm_enabled; - struct cc6_settings cc6_settings; - uint32_t is_voltage_island_enabled; - - bool pgacpinit; - - uint8_t disp_config; - - /* PowerTune */ - uint32_t power_containment_features; - bool cac_enabled; - bool disable_uvd_power_tune_feature; - bool enable_ba_pm_feature; - bool enable_tdc_limit_feature; - - uint32_t sram_end; - uint32_t dpm_table_start; - uint32_t soft_regs_start; - - uint8_t uvd_level_count; - uint8_t vce_level_count; - - uint8_t acp_level_count; - uint8_t samu_level_count; - uint32_t fps_high_threshold; - uint32_t fps_low_threshold; - - uint32_t dpm_flags; - struct smu8_dpm_entry sclk_dpm; - struct smu8_dpm_entry uvd_dpm; - struct smu8_dpm_entry vce_dpm; - struct smu8_dpm_entry acp_dpm; - - uint8_t uvd_boot_level; - uint8_t vce_boot_level; - uint8_t acp_boot_level; - uint8_t samu_boot_level; - uint8_t uvd_interval; - uint8_t vce_interval; - uint8_t acp_interval; - uint8_t samu_interval; - - uint8_t graphics_interval; - uint8_t graphics_therm_throttle_enable; - uint8_t graphics_voltage_change_enable; - - uint8_t graphics_clk_slow_enable; - uint8_t graphics_clk_slow_divider; - - uint32_t display_cac; - uint32_t low_sclk_interrupt_threshold; - - uint32_t dram_log_addr_h; - uint32_t dram_log_addr_l; - uint32_t dram_log_phy_addr_h; - uint32_t dram_log_phy_addr_l; - uint32_t dram_log_buff_size; - - bool uvd_power_gated; - bool vce_power_gated; - bool samu_power_gated; - bool acp_power_gated; - bool acp_power_up_no_dsp; - uint32_t active_process_mask; - - uint32_t max_sclk_level; - uint32_t num_of_clk_entries; -}; - -#endif /* _SMU8_HWMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c deleted file mode 100644 index de0a37f7c632..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "soc15.h" -#include "soc15_hw_ip.h" -#include "vega10_ip_offset.h" -#include "soc15_common.h" -#include "vega10_inc.h" -#include "smu9_baco.h" - -int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - uint32_t reg, data; - - *cap = false; - if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) - return 0; - - WREG32(0x12074, 0xFFF0003B); - data = RREG32(0x12075); - - if (data == 0x1) { - reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); - - if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) - *cap = true; - } - - return 0; -} - -int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - uint32_t reg; - - reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); - - if (reg & BACO_CNTL__BACO_MODE_MASK) - /* gfx has already entered BACO state */ - *state = BACO_STATE_IN; - else - *state = BACO_STATE_OUT; - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h deleted file mode 100644 index 84e90f801ac3..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __SMU9_BACO_H__ -#define __SMU9_BACO_H__ -#include "hwmgr.h" -#include "common_baco.h" - -extern int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); -extern int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c deleted file mode 100644 index 60b5ca974356..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c +++ /dev/null @@ -1,767 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include <linux/pci.h> -#include <linux/reboot.h> - -#include "hwmgr.h" -#include "pp_debug.h" -#include "ppatomctrl.h" -#include "ppsmc.h" -#include "atom.h" -#include "ivsrcid/thm/irqsrcs_thm_9_0.h" -#include "ivsrcid/smuio/irqsrcs_smuio_9_0.h" -#include "ivsrcid/ivsrcid_vislands30.h" - -uint8_t convert_to_vid(uint16_t vddc) -{ - return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); -} - -uint16_t convert_to_vddc(uint8_t vid) -{ - return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE); -} - -int phm_copy_clock_limits_array( - struct pp_hwmgr *hwmgr, - uint32_t **pptable_info_array, - const uint32_t *pptable_array, - uint32_t power_saving_clock_count) -{ - uint32_t array_size, i; - uint32_t *table; - - array_size = sizeof(uint32_t) * power_saving_clock_count; - table = kzalloc(array_size, GFP_KERNEL); - if (NULL == table) - return -ENOMEM; - - for (i = 0; i < power_saving_clock_count; i++) - table[i] = le32_to_cpu(pptable_array[i]); - - *pptable_info_array = table; - - return 0; -} - -int phm_copy_overdrive_settings_limits_array( - struct pp_hwmgr *hwmgr, - uint32_t **pptable_info_array, - const uint32_t *pptable_array, - uint32_t od_setting_count) -{ - uint32_t array_size, i; - uint32_t *table; - - array_size = sizeof(uint32_t) * od_setting_count; - table = kzalloc(array_size, GFP_KERNEL); - if (NULL == table) - return -ENOMEM; - - for (i = 0; i < od_setting_count; i++) - table[i] = le32_to_cpu(pptable_array[i]); - - *pptable_info_array = table; - - return 0; -} - -uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size) -{ - u32 mask = 0; - u32 shift = 0; - - shift = (offset % 4) << 3; - if (size == sizeof(uint8_t)) - mask = 0xFF << shift; - else if (size == sizeof(uint16_t)) - mask = 0xFFFF << shift; - - original_data &= ~mask; - original_data |= (field << shift); - return original_data; -} - -/** - * Returns once the part of the register indicated by the mask has - * reached the given value. - */ -int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, - uint32_t value, uint32_t mask) -{ - uint32_t i; - uint32_t cur_value; - - if (hwmgr == NULL || hwmgr->device == NULL) { - pr_err("Invalid Hardware Manager!"); - return -EINVAL; - } - - for (i = 0; i < hwmgr->usec_timeout; i++) { - cur_value = cgs_read_register(hwmgr->device, index); - if ((cur_value & mask) == (value & mask)) - break; - udelay(1); - } - - /* timeout means wrong logic*/ - if (i == hwmgr->usec_timeout) - return -1; - return 0; -} - - -/** - * Returns once the part of the register indicated by the mask has - * reached the given value.The indirect space is described by giving - * the memory-mapped index of the indirect index register. - */ -int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, - uint32_t indirect_port, - uint32_t index, - uint32_t value, - uint32_t mask) -{ - if (hwmgr == NULL || hwmgr->device == NULL) { - pr_err("Invalid Hardware Manager!"); - return -EINVAL; - } - - cgs_write_register(hwmgr->device, indirect_port, index); - return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value); -} - -int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, - uint32_t index, - uint32_t value, uint32_t mask) -{ - uint32_t i; - uint32_t cur_value; - - if (hwmgr == NULL || hwmgr->device == NULL) - return -EINVAL; - - for (i = 0; i < hwmgr->usec_timeout; i++) { - cur_value = cgs_read_register(hwmgr->device, - index); - if ((cur_value & mask) != (value & mask)) - break; - udelay(1); - } - - /* timeout means wrong logic */ - if (i == hwmgr->usec_timeout) - return -ETIME; - return 0; -} - -int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr, - uint32_t indirect_port, - uint32_t index, - uint32_t value, - uint32_t mask) -{ - if (hwmgr == NULL || hwmgr->device == NULL) - return -EINVAL; - - cgs_write_register(hwmgr->device, indirect_port, index); - return phm_wait_for_register_unequal(hwmgr, indirect_port + 1, - value, mask); -} - -bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr) -{ - return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating); -} - -bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr) -{ - return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating); -} - - -int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table) -{ - uint32_t i, j; - uint16_t vvalue; - bool found = false; - struct pp_atomctrl_voltage_table *table; - - PP_ASSERT_WITH_CODE((NULL != vol_table), - "Voltage Table empty.", return -EINVAL); - - table = kzalloc(sizeof(struct pp_atomctrl_voltage_table), - GFP_KERNEL); - - if (NULL == table) - return -EINVAL; - - table->mask_low = vol_table->mask_low; - table->phase_delay = vol_table->phase_delay; - - for (i = 0; i < vol_table->count; i++) { - vvalue = vol_table->entries[i].value; - found = false; - - for (j = 0; j < table->count; j++) { - if (vvalue == table->entries[j].value) { - found = true; - break; - } - } - - if (!found) { - table->entries[table->count].value = vvalue; - table->entries[table->count].smio_low = - vol_table->entries[i].smio_low; - table->count++; - } - } - - memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table)); - kfree(table); - table = NULL; - return 0; -} - -int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, - phm_ppt_v1_clock_voltage_dependency_table *dep_table) -{ - uint32_t i; - int result; - - PP_ASSERT_WITH_CODE((0 != dep_table->count), - "Voltage Dependency Table empty.", return -EINVAL); - - PP_ASSERT_WITH_CODE((NULL != vol_table), - "vol_table empty.", return -EINVAL); - - vol_table->mask_low = 0; - vol_table->phase_delay = 0; - vol_table->count = dep_table->count; - - for (i = 0; i < dep_table->count; i++) { - vol_table->entries[i].value = dep_table->entries[i].mvdd; - vol_table->entries[i].smio_low = 0; - } - - result = phm_trim_voltage_table(vol_table); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to trim MVDD table.", return result); - - return 0; -} - -int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, - phm_ppt_v1_clock_voltage_dependency_table *dep_table) -{ - uint32_t i; - int result; - - PP_ASSERT_WITH_CODE((0 != dep_table->count), - "Voltage Dependency Table empty.", return -EINVAL); - - PP_ASSERT_WITH_CODE((NULL != vol_table), - "vol_table empty.", return -EINVAL); - - vol_table->mask_low = 0; - vol_table->phase_delay = 0; - vol_table->count = dep_table->count; - - for (i = 0; i < dep_table->count; i++) { - vol_table->entries[i].value = dep_table->entries[i].vddci; - vol_table->entries[i].smio_low = 0; - } - - result = phm_trim_voltage_table(vol_table); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to trim VDDCI table.", return result); - - return 0; -} - -int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, - phm_ppt_v1_voltage_lookup_table *lookup_table) -{ - int i = 0; - - PP_ASSERT_WITH_CODE((0 != lookup_table->count), - "Voltage Lookup Table empty.", return -EINVAL); - - PP_ASSERT_WITH_CODE((NULL != vol_table), - "vol_table empty.", return -EINVAL); - - vol_table->mask_low = 0; - vol_table->phase_delay = 0; - - vol_table->count = lookup_table->count; - - for (i = 0; i < vol_table->count; i++) { - vol_table->entries[i].value = lookup_table->entries[i].us_vdd; - vol_table->entries[i].smio_low = 0; - } - - return 0; -} - -void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, - struct pp_atomctrl_voltage_table *vol_table) -{ - unsigned int i, diff; - - if (vol_table->count <= max_vol_steps) - return; - - diff = vol_table->count - max_vol_steps; - - for (i = 0; i < max_vol_steps; i++) - vol_table->entries[i] = vol_table->entries[i + diff]; - - vol_table->count = max_vol_steps; - - return; -} - -int phm_reset_single_dpm_table(void *table, - uint32_t count, int max) -{ - int i; - - struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; - - dpm_table->count = count > max ? max : count; - - for (i = 0; i < dpm_table->count; i++) - dpm_table->dpm_level[i].enabled = false; - - return 0; -} - -void phm_setup_pcie_table_entry( - void *table, - uint32_t index, uint32_t pcie_gen, - uint32_t pcie_lanes) -{ - struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; - dpm_table->dpm_level[index].value = pcie_gen; - dpm_table->dpm_level[index].param1 = pcie_lanes; - dpm_table->dpm_level[index].enabled = 1; -} - -int32_t phm_get_dpm_level_enable_mask_value(void *table) -{ - int32_t i; - int32_t mask = 0; - struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; - - for (i = dpm_table->count; i > 0; i--) { - mask = mask << 1; - if (dpm_table->dpm_level[i - 1].enabled) - mask |= 0x1; - else - mask &= 0xFFFFFFFE; - } - - return mask; -} - -uint8_t phm_get_voltage_index( - struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage) -{ - uint8_t count = (uint8_t) (lookup_table->count); - uint8_t i; - - PP_ASSERT_WITH_CODE((NULL != lookup_table), - "Lookup Table empty.", return 0); - PP_ASSERT_WITH_CODE((0 != count), - "Lookup Table empty.", return 0); - - for (i = 0; i < lookup_table->count; i++) { - /* find first voltage equal or bigger than requested */ - if (lookup_table->entries[i].us_vdd >= voltage) - return i; - } - /* voltage is bigger than max voltage in the table */ - return i - 1; -} - -uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, - uint32_t voltage) -{ - uint8_t count = (uint8_t) (voltage_table->count); - uint8_t i = 0; - - PP_ASSERT_WITH_CODE((NULL != voltage_table), - "Voltage Table empty.", return 0;); - PP_ASSERT_WITH_CODE((0 != count), - "Voltage Table empty.", return 0;); - - for (i = 0; i < count; i++) { - /* find first voltage bigger than requested */ - if (voltage_table->entries[i].value >= voltage) - return i; - } - - /* voltage is bigger than max voltage in the table */ - return i - 1; -} - -uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci) -{ - uint32_t i; - - for (i = 0; i < vddci_table->count; i++) { - if (vddci_table->entries[i].value >= vddci) - return vddci_table->entries[i].value; - } - - pr_debug("vddci is larger than max value in vddci_table\n"); - return vddci_table->entries[i-1].value; -} - -int phm_find_boot_level(void *table, - uint32_t value, uint32_t *boot_level) -{ - int result = -EINVAL; - uint32_t i; - struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; - - for (i = 0; i < dpm_table->count; i++) { - if (value == dpm_table->dpm_level[i].value) { - *boot_level = i; - result = 0; - } - } - - return result; -} - -int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table *lookup_table, - uint16_t virtual_voltage_id, int32_t *sclk) -{ - uint8_t entry_id; - uint8_t voltage_id; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL); - - /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ - for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { - voltage_id = table_info->vdd_dep_on_sclk->entries[entry_id].vddInd; - if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id) - break; - } - - if (entry_id >= table_info->vdd_dep_on_sclk->count) { - pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n"); - return -EINVAL; - } - - *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk; - - return 0; -} - -/** - * Initialize Dynamic State Adjustment Rule Settings - * - * @param hwmgr the address of the powerplay hardware manager. - */ -int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr) -{ - uint32_t table_size; - struct phm_clock_voltage_dependency_table *table_clk_vlt; - struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - - /* initialize vddc_dep_on_dal_pwrl table */ - table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record); - table_clk_vlt = kzalloc(table_size, GFP_KERNEL); - - if (NULL == table_clk_vlt) { - pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n"); - return -ENOMEM; - } else { - table_clk_vlt->count = 4; - table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW; - table_clk_vlt->entries[0].v = 0; - table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW; - table_clk_vlt->entries[1].v = 720; - table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL; - table_clk_vlt->entries[2].v = 810; - table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE; - table_clk_vlt->entries[3].v = 900; - if (pptable_info != NULL) - pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt; - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; - } - - return 0; -} - -uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask) -{ - uint32_t level = 0; - - while (0 == (mask & (1 << level))) - level++; - - return level; -} - -void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_clock_voltage_dependency_table *table = - table_info->vddc_dep_on_dal_pwrl; - struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table; - enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level; - uint32_t req_vddc = 0, req_volt, i; - - if (!table || table->count <= 0 - || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW - || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE) - return; - - for (i = 0; i < table->count; i++) { - if (dal_power_level == table->entries[i].clk) { - req_vddc = table->entries[i].v; - break; - } - } - - vddc_table = table_info->vdd_dep_on_sclk; - for (i = 0; i < vddc_table->count; i++) { - if (req_vddc <= vddc_table->entries[i].vddc) { - req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_VddC_Request, - req_volt, - NULL); - return; - } - } - pr_err("DAL requested level can not" - " found a available voltage in VDDC DPM Table \n"); -} - -int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint32_t sclk, uint16_t id, uint16_t *voltage) -{ - uint32_t vol; - int ret = 0; - - if (hwmgr->chip_id < CHIP_TONGA) { - ret = atomctrl_get_voltage_evv(hwmgr, id, voltage); - } else if (hwmgr->chip_id < CHIP_POLARIS10) { - ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); - if (*voltage >= 2000 || *voltage == 0) - *voltage = 1150; - } else { - ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol); - *voltage = (uint16_t)(vol/100); - } - return ret; -} - - -int phm_irq_process(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry) -{ - uint32_t client_id = entry->client_id; - uint32_t src_id = entry->src_id; - - if (client_id == AMDGPU_IRQ_CLIENTID_LEGACY) { - if (src_id == VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH) { - dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); - /* - * SW CTF just occurred. - * Try to do a graceful shutdown to prevent further damage. - */ - dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); - orderly_poweroff(true); - } else if (src_id == VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW) - dev_emerg(adev->dev, "ERROR: GPU under temperature range detected!\n"); - else if (src_id == VISLANDS30_IV_SRCID_GPIO_19) { - dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); - /* - * HW CTF just occurred. Shutdown to prevent further damage. - */ - dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); - orderly_poweroff(true); - } - } else if (client_id == SOC15_IH_CLIENTID_THM) { - if (src_id == 0) { - dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); - /* - * SW CTF just occurred. - * Try to do a graceful shutdown to prevent further damage. - */ - dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); - orderly_poweroff(true); - } else - dev_emerg(adev->dev, "ERROR: GPU under temperature range detected!\n"); - } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { - dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); - /* - * HW CTF just occurred. Shutdown to prevent further damage. - */ - dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); - orderly_poweroff(true); - } - - return 0; -} - -static const struct amdgpu_irq_src_funcs smu9_irq_funcs = { - .process = phm_irq_process, -}; - -int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_irq_src *source = - kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); - - if (!source) - return -ENOMEM; - - source->funcs = &smu9_irq_funcs; - - amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), - SOC15_IH_CLIENTID_THM, - THM_9_0__SRCID__THM_DIG_THERM_L2H, - source); - amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), - SOC15_IH_CLIENTID_THM, - THM_9_0__SRCID__THM_DIG_THERM_H2L, - source); - - /* Register CTF(GPIO_19) interrupt */ - amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), - SOC15_IH_CLIENTID_ROM_SMUIO, - SMUIO_9_0__SRCID__SMUIO_GPIO19, - source); - - return 0; -} - -void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, - uint8_t *frev, uint8_t *crev) -{ - struct amdgpu_device *adev = dev; - uint16_t data_start; - - if (amdgpu_atom_parse_data_header( - adev->mode_info.atom_context, table, size, - frev, crev, &data_start)) - return (uint8_t *)adev->mode_info.atom_context->bios + - data_start; - - return NULL; -} - -int smu_get_voltage_dependency_table_ppt_v1( - const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table, - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) -{ - uint8_t i = 0; - PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count), - "Voltage Lookup Table empty", - return -EINVAL); - - dep_table->count = allowed_dep_table->count; - for (i=0; i<dep_table->count; i++) { - dep_table->entries[i].clk = allowed_dep_table->entries[i].clk; - dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd; - dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset; - dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc; - dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx; - dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci; - dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd; - dep_table->entries[i].phases = allowed_dep_table->entries[i].phases; - dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable; - dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset; - } - - return 0; -} - -int smu_set_watermarks_for_clocks_ranges(void *wt_table, - struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) -{ - uint32_t i; - struct watermarks *table = wt_table; - - if (!table || !wm_with_clock_ranges) - return -EINVAL; - - if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4) - return -EINVAL; - - for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { - table->WatermarkRow[1][i].MinClock = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / - 1000)); - table->WatermarkRow[1][i].MaxClock = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / - 1000)); - table->WatermarkRow[1][i].MinUclk = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / - 1000)); - table->WatermarkRow[1][i].MaxUclk = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / - 1000)); - table->WatermarkRow[1][i].WmSetting = (uint8_t) - wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; - } - - for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) { - table->WatermarkRow[0][i].MinClock = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / - 1000)); - table->WatermarkRow[0][i].MaxClock = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / - 1000)); - table->WatermarkRow[0][i].MinUclk = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz / - 1000)); - table->WatermarkRow[0][i].MaxUclk = - cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / - 1000)); - table->WatermarkRow[0][i].WmSetting = (uint8_t) - wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; - } - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h deleted file mode 100644 index ad33983a8064..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _SMU_HELPER_H_ -#define _SMU_HELPER_H_ - -struct pp_atomctrl_voltage_table; -struct pp_hwmgr; -struct phm_ppt_v1_voltage_lookup_table; -struct Watermarks_t; -struct pp_wm_sets_with_clock_ranges_soc15; - -uint8_t convert_to_vid(uint16_t vddc); -uint16_t convert_to_vddc(uint8_t vid); - -struct watermark_row_generic_t { - uint16_t MinClock; - uint16_t MaxClock; - uint16_t MinUclk; - uint16_t MaxUclk; - - uint8_t WmSetting; - uint8_t Padding[3]; -}; - -struct watermarks { - struct watermark_row_generic_t WatermarkRow[2][4]; - uint32_t padding[7]; -}; - -int phm_copy_clock_limits_array( - struct pp_hwmgr *hwmgr, - uint32_t **pptable_info_array, - const uint32_t *pptable_array, - uint32_t power_saving_clock_count); - -int phm_copy_overdrive_settings_limits_array( - struct pp_hwmgr *hwmgr, - uint32_t **pptable_info_array, - const uint32_t *pptable_array, - uint32_t od_setting_count); - -extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, - uint32_t index, - uint32_t value, uint32_t mask); -extern int phm_wait_for_indirect_register_unequal( - struct pp_hwmgr *hwmgr, - uint32_t indirect_port, uint32_t index, - uint32_t value, uint32_t mask); - - -extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr); -extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr); -extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr); - -extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table); -extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); -extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); -extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table); -extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table); -extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max); -extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes); -extern int32_t phm_get_dpm_level_enable_mask_value(void *table); -extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table, - uint32_t voltage); -extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage); -extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci); -extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); -extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, - uint16_t virtual_voltage_id, int32_t *sclk); -extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); -extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); -extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); - -extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, - uint32_t sclk, uint16_t id, uint16_t *voltage); - -extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size); - -extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, - uint32_t value, uint32_t mask); - -extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, - uint32_t indirect_port, - uint32_t index, - uint32_t value, - uint32_t mask); - -int phm_irq_process(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry); - -int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr); - -void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, - uint8_t *frev, uint8_t *crev); - -int smu_get_voltage_dependency_table_ppt_v1( - const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table, - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table); - -int smu_set_watermarks_for_clocks_ranges(void *wt_table, - struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); - -#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT -#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK - -#define PHM_SET_FIELD(origval, reg, field, fieldval) \ - (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ - (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) - -#define PHM_GET_FIELD(value, reg, field) \ - (((value) & PHM_FIELD_MASK(reg, field)) >> \ - PHM_FIELD_SHIFT(reg, field)) - - -/* Operations on named fields. */ - -#define PHM_READ_FIELD(device, reg, field) \ - PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) - -#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \ - PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field) - -#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ - PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field) - -#define PHM_WRITE_FIELD(device, reg, field, fieldval) \ - cgs_write_register(device, mm##reg, PHM_SET_FIELD( \ - cgs_read_register(device, mm##reg), reg, field, fieldval)) - -#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ - cgs_write_ind_register(device, port, ix##reg, \ - PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field, fieldval)) - -#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ - cgs_write_ind_register(device, port, ix##reg, \ - PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field, fieldval)) - -#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ - phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask) - - -#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ - PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) - -#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ - PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ - << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) - -#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ - phm_wait_for_indirect_register_unequal(hwmgr, \ - mm##port##_INDEX, index, value, mask) - -#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ - PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) - -#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ - PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ - (fieldval) << PHM_FIELD_SHIFT(reg, field), \ - PHM_FIELD_MASK(reg, field) ) - - -#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ - port, index, value, mask) \ - phm_wait_for_indirect_register_unequal(hwmgr, \ - mm##port##_INDEX_11, index, value, mask) - -#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ - PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) - -#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ - PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ - (fieldval) << PHM_FIELD_SHIFT(reg, field), \ - PHM_FIELD_MASK(reg, field)) - - -#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \ - port, index, value, mask) \ - phm_wait_on_indirect_register(hwmgr, \ - mm##port##_INDEX_11, index, value, mask) - -#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ - PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) - -#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ - PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \ - (fieldval) << PHM_FIELD_SHIFT(reg, field), \ - PHM_FIELD_MASK(reg, field)) - -#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ - index, value, mask) \ - phm_wait_for_register_unequal(hwmgr, \ - index, value, mask) - -#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ - PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ - mm##reg, value, mask) - -#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ - PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \ - (fieldval) << PHM_FIELD_SHIFT(reg, field), \ - PHM_FIELD_MASK(reg, field)) - -#endif /* _SMU_HELPER_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c deleted file mode 100644 index ea743bea8e29..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "tonga_baco.h" - -#include "gmc/gmc_8_1_d.h" -#include "gmc/gmc_8_1_sh_mask.h" - -#include "bif/bif_5_0_d.h" -#include "bif/bif_5_0_sh_mask.h" - -#include "dce/dce_10_0_d.h" -#include "dce/dce_10_0_sh_mask.h" - -#include "smu/smu_7_1_2_d.h" -#include "smu/smu_7_1_2_sh_mask.h" - - -static const struct baco_cmd_entry gpio_tbl[] = -{ - { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, - { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, - { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, - { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } -}; - -static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, - { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } -}; - -static const struct baco_cmd_entry use_bclk_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, - { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 } -}; - -static const struct baco_cmd_entry turn_off_plls_tbl[] = -{ - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 }, - { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 }, - { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 }, - { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 }, - { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 }, - { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 } -}; - -static const struct baco_cmd_entry enter_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } -}; - -#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK - -static const struct baco_cmd_entry exit_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } -}; - -static const struct baco_cmd_entry clean_baco_tbl[] = -{ - { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, - { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } -}; - -static const struct baco_cmd_entry gpio_tbl_iceland[] = -{ - { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, - { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff } -}; - -static const struct baco_cmd_entry exit_baco_tbl_iceland[] = -{ - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, - { CMD_DELAY_MS, 0, 0, 0, 20, 0 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, - { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } -}; - -static const struct baco_cmd_entry clean_baco_tbl_iceland[] = -{ - { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } -}; - -int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - enum BACO_STATE cur_state; - - smu7_baco_get_state(hwmgr, &cur_state); - - if (cur_state == state) - /* aisc already in the target state */ - return 0; - - if (state == BACO_STATE_IN) { - if (hwmgr->chip_id == CHIP_TOPAZ) - baco_program_registers(hwmgr, gpio_tbl_iceland, ARRAY_SIZE(gpio_tbl_iceland)); - else - baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); - baco_program_registers(hwmgr, enable_fb_req_rej_tbl, - ARRAY_SIZE(enable_fb_req_rej_tbl)); - baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); - baco_program_registers(hwmgr, turn_off_plls_tbl, - ARRAY_SIZE(turn_off_plls_tbl)); - if (baco_program_registers(hwmgr, enter_baco_tbl, - ARRAY_SIZE(enter_baco_tbl))) - return 0; - - } else if (state == BACO_STATE_OUT) { - /* HW requires at least 20ms between regulator off and on */ - msleep(20); - /* Execute Hardware BACO exit sequence */ - if (hwmgr->chip_id == CHIP_TOPAZ) { - if (baco_program_registers(hwmgr, exit_baco_tbl_iceland, - ARRAY_SIZE(exit_baco_tbl_iceland))) { - if (baco_program_registers(hwmgr, clean_baco_tbl_iceland, - ARRAY_SIZE(clean_baco_tbl_iceland))) - return 0; - } - } else { - if (baco_program_registers(hwmgr, exit_baco_tbl, - ARRAY_SIZE(exit_baco_tbl))) { - if (baco_program_registers(hwmgr, clean_baco_tbl, - ARRAY_SIZE(clean_baco_tbl))) - return 0; - } - } - } - - return -EINVAL; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h deleted file mode 100644 index 5dc16cc8a295..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __TONGA_BACO_H__ -#define __TONGA_BACO_H__ -#include "smu7_baco.h" - -extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c deleted file mode 100644 index 46bb16c29cf6..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "soc15.h" -#include "soc15_hw_ip.h" -#include "vega10_ip_offset.h" -#include "soc15_common.h" -#include "vega10_inc.h" -#include "vega10_ppsmc.h" -#include "vega10_baco.h" - - - -static const struct soc15_baco_cmd_entry pre_baco_tbl[] = -{ - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_DOORBELL_CNTL), BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK, BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT, 0, 1}, - {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_FB_EN), 0, 0, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DSTATE_BYPASS_MASK, BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_RST_INTR_MASK_MASK, BACO_CNTL__BACO_RST_INTR_MASK__SHIFT, 0, 1} -}; - -static const struct soc15_baco_cmd_entry enter_baco_tbl[] = -{ - {CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK, THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT, 0xffffffff, 0x80000000}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT,0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT,0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 1}, - {CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 5, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 0}, - {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MODE__SHIFT, 0xffffffff, 0x100} -}; - -static const struct soc15_baco_cmd_entry exit_baco_tbl[] = -{ - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0}, - {CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 10,0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0,0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT,0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, THM_BACO_CNTL__BACO_EXIT__SHIFT, 0, 1}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0}, - {CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffffff, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK, THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK ,BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 0}, - {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK , BACO_CNTL__BACO_EN__SHIFT, 0,0}, - {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0} - }; - -static const struct soc15_baco_cmd_entry clean_baco_tbl[] = -{ - {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0}, - {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0}, -}; - -int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - enum BACO_STATE cur_state; - - smu9_baco_get_state(hwmgr, &cur_state); - - if (cur_state == state) - /* aisc already in the target state */ - return 0; - - if (state == BACO_STATE_IN) { - if (soc15_baco_program_registers(hwmgr, pre_baco_tbl, - ARRAY_SIZE(pre_baco_tbl))) { - if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnterBaco, NULL)) - return -EINVAL; - - if (soc15_baco_program_registers(hwmgr, enter_baco_tbl, - ARRAY_SIZE(enter_baco_tbl))) - return 0; - } - } else if (state == BACO_STATE_OUT) { - /* HW requires at least 20ms between regulator off and on */ - msleep(20); - /* Execute Hardware BACO exit sequence */ - if (soc15_baco_program_registers(hwmgr, exit_baco_tbl, - ARRAY_SIZE(exit_baco_tbl))) { - if (soc15_baco_program_registers(hwmgr, clean_baco_tbl, - ARRAY_SIZE(clean_baco_tbl))) - return 0; - } - } - - return -EINVAL; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h deleted file mode 100644 index 96d793f026a5..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __VEGA10_BACO_H__ -#define __VEGA10_BACO_H__ -#include "smu9_baco.h" - -extern int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c deleted file mode 100644 index c378a000c934..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ /dev/null @@ -1,5482 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/module.h> -#include <linux/pci.h> -#include <linux/slab.h> - -#include "hwmgr.h" -#include "amd_powerplay.h" -#include "hardwaremanager.h" -#include "ppatomfwctrl.h" -#include "atomfirmware.h" -#include "cgs_common.h" -#include "vega10_powertune.h" -#include "smu9.h" -#include "smu9_driver_if.h" -#include "vega10_inc.h" -#include "soc15_common.h" -#include "pppcielanes.h" -#include "vega10_hwmgr.h" -#include "vega10_smumgr.h" -#include "vega10_processpptables.h" -#include "vega10_pptable.h" -#include "vega10_thermal.h" -#include "pp_debug.h" -#include "amd_pcie_helpers.h" -#include "ppinterrupt.h" -#include "pp_overdriver.h" -#include "pp_thermal.h" -#include "vega10_baco.h" - -#include "smuio/smuio_9_0_offset.h" -#include "smuio/smuio_9_0_sh_mask.h" - -#define HBM_MEMORY_CHANNEL_WIDTH 128 - -static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; - -#define mmDF_CS_AON0_DramBaseAddress0 0x0044 -#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 - -//DF_CS_AON0_DramBaseAddress0 -#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 -#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 -#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 -#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 -#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc -#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L -#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L -#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L -#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L -#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L - -typedef enum { - CLK_SMNCLK = 0, - CLK_SOCCLK, - CLK_MP0CLK, - CLK_MP1CLK, - CLK_LCLK, - CLK_DCEFCLK, - CLK_VCLK, - CLK_DCLK, - CLK_ECLK, - CLK_UCLK, - CLK_GFXCLK, - CLK_COUNT, -} CLOCK_ID_e; - -static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic); - -static struct vega10_power_state *cast_phw_vega10_power_state( - struct pp_hw_power_state *hw_ps) -{ - PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), - "Invalid Powerstate Type!", - return NULL;); - - return (struct vega10_power_state *)hw_ps; -} - -static const struct vega10_power_state *cast_const_phw_vega10_power_state( - const struct pp_hw_power_state *hw_ps) -{ - PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), - "Invalid Powerstate Type!", - return NULL;); - - return (const struct vega10_power_state *)hw_ps; -} - -static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - data->registry_data.sclk_dpm_key_disabled = - hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; - data->registry_data.socclk_dpm_key_disabled = - hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; - data->registry_data.mclk_dpm_key_disabled = - hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; - data->registry_data.pcie_dpm_key_disabled = - hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; - - data->registry_data.dcefclk_dpm_key_disabled = - hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; - - if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { - data->registry_data.power_containment_support = 1; - data->registry_data.enable_pkg_pwr_tracking_feature = 1; - data->registry_data.enable_tdc_limit_feature = 1; - } - - data->registry_data.clock_stretcher_support = - hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; - - data->registry_data.ulv_support = - hwmgr->feature_mask & PP_ULV_MASK ? true : false; - - data->registry_data.sclk_deep_sleep_support = - hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; - - data->registry_data.disable_water_mark = 0; - - data->registry_data.fan_control_support = 1; - data->registry_data.thermal_support = 1; - data->registry_data.fw_ctf_enabled = 1; - - data->registry_data.avfs_support = - hwmgr->feature_mask & PP_AVFS_MASK ? true : false; - data->registry_data.led_dpm_enabled = 1; - - data->registry_data.vr0hot_enabled = 1; - data->registry_data.vr1hot_enabled = 1; - data->registry_data.regulator_hot_gpio_support = 1; - - data->registry_data.didt_support = 1; - if (data->registry_data.didt_support) { - data->registry_data.didt_mode = 6; - data->registry_data.sq_ramping_support = 1; - data->registry_data.db_ramping_support = 0; - data->registry_data.td_ramping_support = 0; - data->registry_data.tcp_ramping_support = 0; - data->registry_data.dbr_ramping_support = 0; - data->registry_data.edc_didt_support = 1; - data->registry_data.gc_didt_support = 0; - data->registry_data.psm_didt_support = 0; - } - - data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT; - data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; - - data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT; - data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT; - data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT; - data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT; -} - -static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct amdgpu_device *adev = hwmgr->adev; - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPatchPowerState); - - if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableSMU7ThermalManagement); - - if (adev->pg_flags & AMD_PG_SUPPORT_UVD) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - - if (adev->pg_flags & AMD_PG_SUPPORT_VCE) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UnTabledHardwareInterface); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPowerManagement); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMC); - - /* power tune caps */ - /* assume disabled */ - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtSupport); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtEDCEnable); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_GCEDC); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PSM); - - if (data->registry_data.didt_support) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); - if (data->registry_data.sq_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); - if (data->registry_data.db_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); - if (data->registry_data.td_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); - if (data->registry_data.tcp_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); - if (data->registry_data.dbr_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); - if (data->registry_data.edc_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); - if (data->registry_data.gc_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); - if (data->registry_data.psm_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); - } - - if (data->registry_data.power_containment_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - - if (table_info->tdp_table->usClockStretchAmount && - data->registry_data.clock_stretcher_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDPM); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEDPM); - - return 0; -} - -static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); - struct vega10_odn_vddc_lookup_table *od_lookup_table; - struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3]; - struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3]; - struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; - uint32_t i; - int result; - - result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); - if (!result) { - data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc; - data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc; - } - - od_lookup_table = &odn_table->vddc_lookup_table; - vddc_lookup_table = table_info->vddc_lookup_table; - - for (i = 0; i < vddc_lookup_table->count; i++) - od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd; - - od_lookup_table->count = vddc_lookup_table->count; - - dep_table[0] = table_info->vdd_dep_on_sclk; - dep_table[1] = table_info->vdd_dep_on_mclk; - dep_table[2] = table_info->vdd_dep_on_socclk; - od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk; - od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk; - od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk; - - for (i = 0; i < 3; i++) - smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]); - - if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000) - odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc; - if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000) - odn_table->min_vddc = dep_table[0]->entries[0].vddc; - - i = od_table[2]->count - 1; - od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ? - hwmgr->platform_descriptor.overdriveLimit.memoryClock : - od_table[2]->entries[i].clk; - od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ? - odn_table->max_vddc : - od_table[2]->entries[i].vddc; - - return 0; -} - -static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - int i; - uint32_t sub_vendor_id, hw_revision; - uint32_t top32, bottom32; - struct amdgpu_device *adev = hwmgr->adev; - - vega10_initialize_power_tune_defaults(hwmgr); - - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - data->smu_features[i].smu_feature_id = 0xffff; - data->smu_features[i].smu_feature_bitmap = 1 << i; - data->smu_features[i].enabled = false; - data->smu_features[i].supported = false; - } - - data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = - FEATURE_DPM_PREFETCHER_BIT; - data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = - FEATURE_DPM_GFXCLK_BIT; - data->smu_features[GNLD_DPM_UCLK].smu_feature_id = - FEATURE_DPM_UCLK_BIT; - data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = - FEATURE_DPM_SOCCLK_BIT; - data->smu_features[GNLD_DPM_UVD].smu_feature_id = - FEATURE_DPM_UVD_BIT; - data->smu_features[GNLD_DPM_VCE].smu_feature_id = - FEATURE_DPM_VCE_BIT; - data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = - FEATURE_DPM_MP0CLK_BIT; - data->smu_features[GNLD_DPM_LINK].smu_feature_id = - FEATURE_DPM_LINK_BIT; - data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = - FEATURE_DPM_DCEFCLK_BIT; - data->smu_features[GNLD_ULV].smu_feature_id = - FEATURE_ULV_BIT; - data->smu_features[GNLD_AVFS].smu_feature_id = - FEATURE_AVFS_BIT; - data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = - FEATURE_DS_GFXCLK_BIT; - data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = - FEATURE_DS_SOCCLK_BIT; - data->smu_features[GNLD_DS_LCLK].smu_feature_id = - FEATURE_DS_LCLK_BIT; - data->smu_features[GNLD_PPT].smu_feature_id = - FEATURE_PPT_BIT; - data->smu_features[GNLD_TDC].smu_feature_id = - FEATURE_TDC_BIT; - data->smu_features[GNLD_THERMAL].smu_feature_id = - FEATURE_THERMAL_BIT; - data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = - FEATURE_GFX_PER_CU_CG_BIT; - data->smu_features[GNLD_RM].smu_feature_id = - FEATURE_RM_BIT; - data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = - FEATURE_DS_DCEFCLK_BIT; - data->smu_features[GNLD_ACDC].smu_feature_id = - FEATURE_ACDC_BIT; - data->smu_features[GNLD_VR0HOT].smu_feature_id = - FEATURE_VR0HOT_BIT; - data->smu_features[GNLD_VR1HOT].smu_feature_id = - FEATURE_VR1HOT_BIT; - data->smu_features[GNLD_FW_CTF].smu_feature_id = - FEATURE_FW_CTF_BIT; - data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = - FEATURE_LED_DISPLAY_BIT; - data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = - FEATURE_FAN_CONTROL_BIT; - data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; - data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; - data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT; - - if (!data->registry_data.prefetcher_dpm_key_disabled) - data->smu_features[GNLD_DPM_PREFETCHER].supported = true; - - if (!data->registry_data.sclk_dpm_key_disabled) - data->smu_features[GNLD_DPM_GFXCLK].supported = true; - - if (!data->registry_data.mclk_dpm_key_disabled) - data->smu_features[GNLD_DPM_UCLK].supported = true; - - if (!data->registry_data.socclk_dpm_key_disabled) - data->smu_features[GNLD_DPM_SOCCLK].supported = true; - - if (PP_CAP(PHM_PlatformCaps_UVDDPM)) - data->smu_features[GNLD_DPM_UVD].supported = true; - - if (PP_CAP(PHM_PlatformCaps_VCEDPM)) - data->smu_features[GNLD_DPM_VCE].supported = true; - - if (!data->registry_data.pcie_dpm_key_disabled) - data->smu_features[GNLD_DPM_LINK].supported = true; - - if (!data->registry_data.dcefclk_dpm_key_disabled) - data->smu_features[GNLD_DPM_DCEFCLK].supported = true; - - if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) && - data->registry_data.sclk_deep_sleep_support) { - data->smu_features[GNLD_DS_GFXCLK].supported = true; - data->smu_features[GNLD_DS_SOCCLK].supported = true; - data->smu_features[GNLD_DS_LCLK].supported = true; - data->smu_features[GNLD_DS_DCEFCLK].supported = true; - } - - if (data->registry_data.enable_pkg_pwr_tracking_feature) - data->smu_features[GNLD_PPT].supported = true; - - if (data->registry_data.enable_tdc_limit_feature) - data->smu_features[GNLD_TDC].supported = true; - - if (data->registry_data.thermal_support) - data->smu_features[GNLD_THERMAL].supported = true; - - if (data->registry_data.fan_control_support) - data->smu_features[GNLD_FAN_CONTROL].supported = true; - - if (data->registry_data.fw_ctf_enabled) - data->smu_features[GNLD_FW_CTF].supported = true; - - if (data->registry_data.avfs_support) - data->smu_features[GNLD_AVFS].supported = true; - - if (data->registry_data.led_dpm_enabled) - data->smu_features[GNLD_LED_DISPLAY].supported = true; - - if (data->registry_data.vr1hot_enabled) - data->smu_features[GNLD_VR1HOT].supported = true; - - if (data->registry_data.vr0hot_enabled) - data->smu_features[GNLD_VR0HOT].supported = true; - - smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_GetSmuVersion, - &hwmgr->smu_version); - /* ACG firmware has major version 5 */ - if ((hwmgr->smu_version & 0xff000000) == 0x5000000) - data->smu_features[GNLD_ACG].supported = true; - if (data->registry_data.didt_support) - data->smu_features[GNLD_DIDT].supported = true; - - hw_revision = adev->pdev->revision; - sub_vendor_id = adev->pdev->subsystem_vendor; - - if ((hwmgr->chip_id == 0x6862 || - hwmgr->chip_id == 0x6861 || - hwmgr->chip_id == 0x6868) && - (hw_revision == 0) && - (sub_vendor_id != 0x1002)) - data->smu_features[GNLD_PCC_LIMIT].supported = true; - - /* Get the SN to turn into a Unique ID */ - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); - - adev->unique_id = ((uint64_t)bottom32 << 32) | top32; -} - -#ifdef PPLIB_VEGA10_EVV_SUPPORT -static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table *lookup_table, - uint16_t virtual_voltage_id, int32_t *socclk) -{ - uint8_t entry_id; - uint8_t voltage_id; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - - PP_ASSERT_WITH_CODE(lookup_table->count != 0, - "Lookup table is empty", - return -EINVAL); - - /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */ - for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { - voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd; - if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id) - break; - } - - PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count, - "Can't find requested voltage id in vdd_dep_on_socclk table!", - return -EINVAL); - - *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk; - - return 0; -} - -#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 -/** -* Get Leakage VDDC based on leakage ID. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0. -*/ -static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint16_t vv_id; - uint32_t vddc = 0; - uint16_t i, j; - uint32_t sclk = 0; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = - table_info->vdd_dep_on_socclk; - int result; - - for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) { - vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; - - if (!vega10_get_socclk_for_voltage_evv(hwmgr, - table_info->vddc_lookup_table, vv_id, &sclk)) { - if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) { - for (j = 1; j < socclk_table->count; j++) { - if (socclk_table->entries[j].clk == sclk && - socclk_table->entries[j].cks_enable == 0) { - sclk += 5000; - break; - } - } - } - - PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, - VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), - "Error retrieving EVV voltage value!", - continue); - - - /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ - PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), - "Invalid VDDC value", result = -EINVAL;); - - /* the voltage should not be zero nor equal to leakage ID */ - if (vddc != 0 && vddc != vv_id) { - data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); - data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; - data->vddc_leakage.count++; - } - } - } - - return 0; -} - -/** - * Change virtual leakage voltage to actual value. - * - * @param hwmgr the address of the powerplay hardware manager. - * @param pointer to changing voltage - * @param pointer to leakage table - */ -static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, - uint16_t *voltage, struct vega10_leakage_voltage *leakage_table) -{ - uint32_t index; - - /* search for leakage voltage ID 0xff01 ~ 0xff08 */ - for (index = 0; index < leakage_table->count; index++) { - /* if this voltage matches a leakage voltage ID */ - /* patch with actual leakage voltage */ - if (leakage_table->leakage_id[index] == *voltage) { - *voltage = leakage_table->actual_voltage[index]; - break; - } - } - - if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) - pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); -} - -/** -* Patch voltage lookup table by EVV leakages. -* -* @param hwmgr the address of the powerplay hardware manager. -* @param pointer to voltage lookup table -* @param pointer to leakage table -* @return always 0 -*/ -static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table *lookup_table, - struct vega10_leakage_voltage *leakage_table) -{ - uint32_t i; - - for (i = 0; i < lookup_table->count; i++) - vega10_patch_with_vdd_leakage(hwmgr, - &lookup_table->entries[i].us_vdd, leakage_table); - - return 0; -} - -static int vega10_patch_clock_voltage_limits_with_vddc_leakage( - struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table, - uint16_t *vddc) -{ - vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); - - return 0; -} -#endif - -static int vega10_patch_voltage_dependency_tables_with_lookup_table( - struct pp_hwmgr *hwmgr) -{ - uint8_t entry_id, voltage_id; - unsigned i; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = - table_info->mm_dep_table; - struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = - table_info->vdd_dep_on_mclk; - - for (i = 0; i < 6; i++) { - struct phm_ppt_v1_clock_voltage_dependency_table *vdt; - switch (i) { - case 0: vdt = table_info->vdd_dep_on_socclk; break; - case 1: vdt = table_info->vdd_dep_on_sclk; break; - case 2: vdt = table_info->vdd_dep_on_dcefclk; break; - case 3: vdt = table_info->vdd_dep_on_pixclk; break; - case 4: vdt = table_info->vdd_dep_on_dispclk; break; - case 5: vdt = table_info->vdd_dep_on_phyclk; break; - } - - for (entry_id = 0; entry_id < vdt->count; entry_id++) { - voltage_id = vdt->entries[entry_id].vddInd; - vdt->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - } - - for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { - voltage_id = mm_table->entries[entry_id].vddcInd; - mm_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - - for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { - voltage_id = mclk_table->entries[entry_id].vddInd; - mclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - voltage_id = mclk_table->entries[entry_id].vddciInd; - mclk_table->entries[entry_id].vddci = - table_info->vddci_lookup_table->entries[voltage_id].us_vdd; - voltage_id = mclk_table->entries[entry_id].mvddInd; - mclk_table->entries[entry_id].mvdd = - table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; - } - - - return 0; - -} - -static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_voltage_lookup_table *lookup_table) -{ - uint32_t table_size, i, j; - - PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, - "Lookup table is empty", return -EINVAL); - - table_size = lookup_table->count; - - /* Sorting voltages */ - for (i = 0; i < table_size - 1; i++) { - for (j = i + 1; j > 0; j--) { - if (lookup_table->entries[j].us_vdd < - lookup_table->entries[j - 1].us_vdd) { - swap(lookup_table->entries[j - 1], - lookup_table->entries[j]); - } - } - } - - return 0; -} - -static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) -{ - int result = 0; - int tmp_result; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); -#ifdef PPLIB_VEGA10_EVV_SUPPORT - struct vega10_hwmgr *data = hwmgr->backend; - - tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr, - table_info->vddc_lookup_table, &(data->vddc_leakage)); - if (tmp_result) - result = tmp_result; - - tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, - &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); - if (tmp_result) - result = tmp_result; -#endif - - tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); - if (tmp_result) - result = tmp_result; - - tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); - if (tmp_result) - result = tmp_result; - - return result; -} - -static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = - table_info->vdd_dep_on_socclk; - struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = - table_info->vdd_dep_on_mclk; - - PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, - "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, - "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); - - PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, - "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, - "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); - - table_info->max_clock_voltage_on_ac.sclk = - allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; - table_info->max_clock_voltage_on_ac.mclk = - allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; - table_info->max_clock_voltage_on_ac.vddc = - allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; - table_info->max_clock_voltage_on_ac.vddci = - allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; - - hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = - table_info->max_clock_voltage_on_ac.sclk; - hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = - table_info->max_clock_voltage_on_ac.mclk; - hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = - table_info->max_clock_voltage_on_ac.vddc; - hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = - table_info->max_clock_voltage_on_ac.vddci; - - return 0; -} - -static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) -{ - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - - kfree(hwmgr->backend); - hwmgr->backend = NULL; - - return 0; -} - -static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) -{ - int result = 0; - struct vega10_hwmgr *data; - uint32_t config_telemetry = 0; - struct pp_atomfwctrl_voltage_table vol_table; - struct amdgpu_device *adev = hwmgr->adev; - - data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - - hwmgr->backend = data; - - hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; - hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - - vega10_set_default_registry_data(hwmgr); - data->disable_dpm_mask = 0xff; - - /* need to set voltage control types before EVV patching */ - data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE; - data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE; - data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE; - - /* VDDCR_SOC */ - if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, - VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { - if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, - VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2, - &vol_table)) { - config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) | - (vol_table.telemetry_offset & 0xff); - data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; - } - } else { - kfree(hwmgr->backend); - hwmgr->backend = NULL; - PP_ASSERT_WITH_CODE(false, - "VDDCR_SOC is not SVID2!", - return -1); - } - - /* MVDDC */ - if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) { - if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2, - &vol_table)) { - config_telemetry |= - ((vol_table.telemetry_slope << 24) & 0xff000000) | - ((vol_table.telemetry_offset << 16) & 0xff0000); - data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; - } - } - - /* VDDCI_MEM */ - if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) { - if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, - VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) - data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO; - } - - data->config_telemetry = config_telemetry; - - vega10_set_features_platform_caps(hwmgr); - - vega10_init_dpm_defaults(hwmgr); - -#ifdef PPLIB_VEGA10_EVV_SUPPORT - /* Get leakage voltage based on leakage ID. */ - PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr), - "Get EVV Voltage Failed. Abort Driver loading!", - return -1); -#endif - - /* Patch our voltage dependency table with actual leakage voltage - * We need to perform leakage translation before it's used by other functions - */ - vega10_complete_dependency_tables(hwmgr); - - /* Parse pptable data read from VBIOS */ - vega10_set_private_data_based_on_pptable(hwmgr); - - data->is_tlu_enabled = false; - - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = - VEGA10_MAX_HARDWARE_POWERLEVELS; - hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; - hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - - hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ - /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ - hwmgr->platform_descriptor.clockStep.engineClock = 500; - hwmgr->platform_descriptor.clockStep.memoryClock = 500; - - data->total_active_cus = adev->gfx.cu_info.number; - if (!hwmgr->not_vf) - return result; - - /* Setup default Overdrive Fan control settings */ - data->odn_fan_table.target_fan_speed = - hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; - data->odn_fan_table.target_temperature = - hwmgr->thermal_controller. - advanceFanControlParameters.ucTargetTemperature; - data->odn_fan_table.min_performance_clock = - hwmgr->thermal_controller.advanceFanControlParameters. - ulMinFanSCLKAcousticLimit; - data->odn_fan_table.min_fan_limit = - hwmgr->thermal_controller. - advanceFanControlParameters.usFanPWMMinLimit * - hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; - - data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & - DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> - DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; - PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), - "Mem Channel Index Exceeded maximum!", - return -EINVAL); - - return result; -} - -static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - data->low_sclk_interrupt_threshold = 0; - - return 0; -} - -static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - - struct pp_atomfwctrl_voltage_table table; - uint8_t i, j; - uint32_t mask = 0; - uint32_t tmp; - int32_t ret = 0; - - ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM, - VOLTAGE_OBJ_GPIO_LUT, &table); - - if (!ret) { - tmp = table.mask_low; - for (i = 0, j = 0; i < 32; i++) { - if (tmp & 1) { - mask |= (uint32_t)(i << (8 * j)); - if (++j >= 3) - break; - } - tmp >>= 1; - } - } - - pp_table->LedPin0 = (uint8_t)(mask & 0xff); - pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff); - pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff); - return 0; -} - -static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr->not_vf) - return 0; - - PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr), - "Failed to init sclk threshold!", - return -EINVAL); - - PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr), - "Failed to set up led dpm config!", - return -EINVAL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, - 0, - NULL); - - return 0; -} - -/** -* Remove repeated voltage values and create table with unique values. -* -* @param hwmgr the address of the powerplay hardware manager. -* @param vol_table the pointer to changing voltage table -* @return 0 in success -*/ - -static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr, - struct pp_atomfwctrl_voltage_table *vol_table) -{ - uint32_t i, j; - uint16_t vvalue; - bool found = false; - struct pp_atomfwctrl_voltage_table *table; - - PP_ASSERT_WITH_CODE(vol_table, - "Voltage Table empty.", return -EINVAL); - table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table), - GFP_KERNEL); - - if (!table) - return -ENOMEM; - - table->mask_low = vol_table->mask_low; - table->phase_delay = vol_table->phase_delay; - - for (i = 0; i < vol_table->count; i++) { - vvalue = vol_table->entries[i].value; - found = false; - - for (j = 0; j < table->count; j++) { - if (vvalue == table->entries[j].value) { - found = true; - break; - } - } - - if (!found) { - table->entries[table->count].value = vvalue; - table->entries[table->count].smio_low = - vol_table->entries[i].smio_low; - table->count++; - } - } - - memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table)); - kfree(table); - - return 0; -} - -static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr, - phm_ppt_v1_clock_voltage_dependency_table *dep_table, - struct pp_atomfwctrl_voltage_table *vol_table) -{ - int i; - - PP_ASSERT_WITH_CODE(dep_table->count, - "Voltage Dependency Table empty.", - return -EINVAL); - - vol_table->mask_low = 0; - vol_table->phase_delay = 0; - vol_table->count = dep_table->count; - - for (i = 0; i < vol_table->count; i++) { - vol_table->entries[i].value = dep_table->entries[i].mvdd; - vol_table->entries[i].smio_low = 0; - } - - PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, - vol_table), - "Failed to trim MVDD Table!", - return -1); - - return 0; -} - -static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr, - phm_ppt_v1_clock_voltage_dependency_table *dep_table, - struct pp_atomfwctrl_voltage_table *vol_table) -{ - uint32_t i; - - PP_ASSERT_WITH_CODE(dep_table->count, - "Voltage Dependency Table empty.", - return -EINVAL); - - vol_table->mask_low = 0; - vol_table->phase_delay = 0; - vol_table->count = dep_table->count; - - for (i = 0; i < dep_table->count; i++) { - vol_table->entries[i].value = dep_table->entries[i].vddci; - vol_table->entries[i].smio_low = 0; - } - - PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table), - "Failed to trim VDDCI table.", - return -1); - - return 0; -} - -static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr, - phm_ppt_v1_clock_voltage_dependency_table *dep_table, - struct pp_atomfwctrl_voltage_table *vol_table) -{ - int i; - - PP_ASSERT_WITH_CODE(dep_table->count, - "Voltage Dependency Table empty.", - return -EINVAL); - - vol_table->mask_low = 0; - vol_table->phase_delay = 0; - vol_table->count = dep_table->count; - - for (i = 0; i < vol_table->count; i++) { - vol_table->entries[i].value = dep_table->entries[i].vddc; - vol_table->entries[i].smio_low = 0; - } - - return 0; -} - -/* ---- Voltage Tables ---- - * If the voltage table would be bigger than - * what will fit into the state table on - * the SMC keep only the higher entries. - */ -static void vega10_trim_voltage_table_to_fit_state_table( - struct pp_hwmgr *hwmgr, - uint32_t max_vol_steps, - struct pp_atomfwctrl_voltage_table *vol_table) -{ - unsigned int i, diff; - - if (vol_table->count <= max_vol_steps) - return; - - diff = vol_table->count - max_vol_steps; - - for (i = 0; i < max_vol_steps; i++) - vol_table->entries[i] = vol_table->entries[i + diff]; - - vol_table->count = max_vol_steps; -} - -/** -* Create Voltage Tables. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - int result; - - if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || - data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) { - result = vega10_get_mvdd_voltage_table(hwmgr, - table_info->vdd_dep_on_mclk, - &(data->mvdd_voltage_table)); - PP_ASSERT_WITH_CODE(!result, - "Failed to retrieve MVDDC table!", - return result); - } - - if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) { - result = vega10_get_vddci_voltage_table(hwmgr, - table_info->vdd_dep_on_mclk, - &(data->vddci_voltage_table)); - PP_ASSERT_WITH_CODE(!result, - "Failed to retrieve VDDCI_MEM table!", - return result); - } - - if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || - data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) { - result = vega10_get_vdd_voltage_table(hwmgr, - table_info->vdd_dep_on_sclk, - &(data->vddc_voltage_table)); - PP_ASSERT_WITH_CODE(!result, - "Failed to retrieve VDDCR_SOC table!", - return result); - } - - PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16, - "Too many voltage values for VDDC. Trimming to fit state table.", - vega10_trim_voltage_table_to_fit_state_table(hwmgr, - 16, &(data->vddc_voltage_table))); - - PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16, - "Too many voltage values for VDDCI. Trimming to fit state table.", - vega10_trim_voltage_table_to_fit_state_table(hwmgr, - 16, &(data->vddci_voltage_table))); - - PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16, - "Too many voltage values for MVDD. Trimming to fit state table.", - vega10_trim_voltage_table_to_fit_state_table(hwmgr, - 16, &(data->mvdd_voltage_table))); - - - return 0; -} - -/* - * @fn vega10_init_dpm_state - * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. - * - * @param dpm_state - the address of the DPM Table to initiailize. - * @return None. - */ -static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state) -{ - dpm_state->soft_min_level = 0xff; - dpm_state->soft_max_level = 0xff; - dpm_state->hard_min_level = 0xff; - dpm_state->hard_max_level = 0xff; -} - -static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, - struct vega10_single_dpm_table *dpm_table, - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) -{ - int i; - - dpm_table->count = 0; - - for (i = 0; i < dep_table->count; i++) { - if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= - dep_table->entries[i].clk) { - dpm_table->dpm_levels[dpm_table->count].value = - dep_table->entries[i].clk; - dpm_table->dpm_levels[dpm_table->count].enabled = true; - dpm_table->count++; - } - } -} -static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_pcie_table *bios_pcie_table = - table_info->pcie_table; - uint32_t i; - - PP_ASSERT_WITH_CODE(bios_pcie_table->count, - "Incorrect number of PCIE States from VBIOS!", - return -1); - - for (i = 0; i < NUM_LINK_LEVELS; i++) { - if (data->registry_data.pcieSpeedOverride) - pcie_table->pcie_gen[i] = - data->registry_data.pcieSpeedOverride; - else - pcie_table->pcie_gen[i] = - bios_pcie_table->entries[i].gen_speed; - - if (data->registry_data.pcieLaneOverride) - pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( - data->registry_data.pcieLaneOverride); - else - pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( - bios_pcie_table->entries[i].lane_width); - if (data->registry_data.pcieClockOverride) - pcie_table->lclk[i] = - data->registry_data.pcieClockOverride; - else - pcie_table->lclk[i] = - bios_pcie_table->entries[i].pcie_sclk; - } - - pcie_table->count = NUM_LINK_LEVELS; - - return 0; -} - -/* - * This function is to initialize all DPM state tables - * for SMU based on the dependency table. - * Dynamic state patching function will then trim these - * state tables to the allowed range based - * on the power policy or external client requests, - * such as UVD request, etc. - */ -static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct vega10_single_dpm_table *dpm_table; - uint32_t i; - - struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table = - table_info->vdd_dep_on_socclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table = - table_info->vdd_dep_on_sclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = - table_info->vdd_dep_on_mclk; - struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table = - table_info->mm_dep_table; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table = - table_info->vdd_dep_on_dcefclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table = - table_info->vdd_dep_on_pixclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table = - table_info->vdd_dep_on_dispclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table = - table_info->vdd_dep_on_phyclk; - - PP_ASSERT_WITH_CODE(dep_soc_table, - "SOCCLK dependency table is missing. This table is mandatory", - return -EINVAL); - PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1, - "SOCCLK dependency table is empty. This table is mandatory", - return -EINVAL); - - PP_ASSERT_WITH_CODE(dep_gfx_table, - "GFXCLK dependency table is missing. This table is mandatory", - return -EINVAL); - PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1, - "GFXCLK dependency table is empty. This table is mandatory", - return -EINVAL); - - PP_ASSERT_WITH_CODE(dep_mclk_table, - "MCLK dependency table is missing. This table is mandatory", - return -EINVAL); - PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, - "MCLK dependency table has to have is missing. This table is mandatory", - return -EINVAL); - - /* Initialize Sclk DPM table based on allow Sclk values */ - dpm_table = &(data->dpm_table.soc_table); - vega10_setup_default_single_dpm_table(hwmgr, - dpm_table, - dep_soc_table); - - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - dpm_table = &(data->dpm_table.gfx_table); - vega10_setup_default_single_dpm_table(hwmgr, - dpm_table, - dep_gfx_table); - if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) - hwmgr->platform_descriptor.overdriveLimit.engineClock = - dpm_table->dpm_levels[dpm_table->count-1].value; - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - /* Initialize Mclk DPM table based on allow Mclk values */ - data->dpm_table.mem_table.count = 0; - dpm_table = &(data->dpm_table.mem_table); - vega10_setup_default_single_dpm_table(hwmgr, - dpm_table, - dep_mclk_table); - if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) - hwmgr->platform_descriptor.overdriveLimit.memoryClock = - dpm_table->dpm_levels[dpm_table->count-1].value; - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - data->dpm_table.eclk_table.count = 0; - dpm_table = &(data->dpm_table.eclk_table); - for (i = 0; i < dep_mm_table->count; i++) { - if (i == 0 || dpm_table->dpm_levels - [dpm_table->count - 1].value <= - dep_mm_table->entries[i].eclk) { - dpm_table->dpm_levels[dpm_table->count].value = - dep_mm_table->entries[i].eclk; - dpm_table->dpm_levels[dpm_table->count].enabled = - (i == 0) ? true : false; - dpm_table->count++; - } - } - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - data->dpm_table.vclk_table.count = 0; - data->dpm_table.dclk_table.count = 0; - dpm_table = &(data->dpm_table.vclk_table); - for (i = 0; i < dep_mm_table->count; i++) { - if (i == 0 || dpm_table->dpm_levels - [dpm_table->count - 1].value <= - dep_mm_table->entries[i].vclk) { - dpm_table->dpm_levels[dpm_table->count].value = - dep_mm_table->entries[i].vclk; - dpm_table->dpm_levels[dpm_table->count].enabled = - (i == 0) ? true : false; - dpm_table->count++; - } - } - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - dpm_table = &(data->dpm_table.dclk_table); - for (i = 0; i < dep_mm_table->count; i++) { - if (i == 0 || dpm_table->dpm_levels - [dpm_table->count - 1].value <= - dep_mm_table->entries[i].dclk) { - dpm_table->dpm_levels[dpm_table->count].value = - dep_mm_table->entries[i].dclk; - dpm_table->dpm_levels[dpm_table->count].enabled = - (i == 0) ? true : false; - dpm_table->count++; - } - } - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - /* Assume there is no headless Vega10 for now */ - dpm_table = &(data->dpm_table.dcef_table); - vega10_setup_default_single_dpm_table(hwmgr, - dpm_table, - dep_dcef_table); - - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - dpm_table = &(data->dpm_table.pixel_table); - vega10_setup_default_single_dpm_table(hwmgr, - dpm_table, - dep_pix_table); - - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - dpm_table = &(data->dpm_table.display_table); - vega10_setup_default_single_dpm_table(hwmgr, - dpm_table, - dep_disp_table); - - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - dpm_table = &(data->dpm_table.phy_table); - vega10_setup_default_single_dpm_table(hwmgr, - dpm_table, - dep_phy_table); - - vega10_init_dpm_state(&(dpm_table->dpm_state)); - - vega10_setup_default_pcie_table(hwmgr); - - /* Zero out the saved copy of the CUSTOM profile - * This will be checked when trying to set the profile - * and will require that new values be passed in - */ - data->custom_profile_mode[0] = 0; - data->custom_profile_mode[1] = 0; - data->custom_profile_mode[2] = 0; - data->custom_profile_mode[3] = 0; - - /* save a copy of the default DPM table */ - memcpy(&(data->golden_dpm_table), &(data->dpm_table), - sizeof(struct vega10_dpm_table)); - - return 0; -} - -/* - * @fn vega10_populate_ulv_state - * @brief Function to provide parameters for Utral Low Voltage state to SMC. - * - * @param hwmgr - the address of the hardware manager. - * @return Always 0. - */ -static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - - data->smc_state_table.pp_table.UlvOffsetVid = - (uint8_t)table_info->us_ulv_voltage_offset; - - data->smc_state_table.pp_table.UlvSmnclkDid = - (uint8_t)(table_info->us_ulv_smnclk_did); - data->smc_state_table.pp_table.UlvMp1clkDid = - (uint8_t)(table_info->us_ulv_mp1clk_did); - data->smc_state_table.pp_table.UlvGfxclkBypass = - (uint8_t)(table_info->us_ulv_gfxclk_bypass); - data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = - (uint8_t)(data->vddc_voltage_table.psi0_enable); - data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = - (uint8_t)(data->vddc_voltage_table.psi1_enable); - - return 0; -} - -static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, - uint32_t lclock, uint8_t *curr_lclk_did) -{ - struct pp_atomfwctrl_clock_dividers_soc15 dividers; - - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( - hwmgr, - COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, - lclock, ÷rs), - "Failed to get LCLK clock settings from VBIOS!", - return -1); - - *curr_lclk_did = dividers.ulDid; - - return 0; -} - -static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) -{ - int result = -1; - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct vega10_pcie_table *pcie_table = - &(data->dpm_table.pcie_table); - uint32_t i, j; - - for (i = 0; i < pcie_table->count; i++) { - pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i]; - pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; - - result = vega10_populate_single_lclk_level(hwmgr, - pcie_table->lclk[i], &(pp_table->LclkDid[i])); - if (result) { - pr_info("Populate LClock Level %d Failed!\n", i); - return result; - } - } - - j = i - 1; - while (i < NUM_LINK_LEVELS) { - pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j]; - pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; - - result = vega10_populate_single_lclk_level(hwmgr, - pcie_table->lclk[j], &(pp_table->LclkDid[i])); - if (result) { - pr_info("Populate LClock Level %d Failed!\n", i); - return result; - } - i++; - } - - return result; -} - -/** -* Populates single SMC GFXSCLK structure using the provided engine clock -* -* @param hwmgr the address of the hardware manager -* @param gfx_clock the GFX clock to use to populate the structure. -* @param current_gfxclk_level location in PPTable for the SMC GFXCLK structure. -*/ - -static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, - uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, - uint32_t *acg_freq) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk; - struct vega10_hwmgr *data = hwmgr->backend; - struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t gfx_max_clock = - hwmgr->platform_descriptor.overdriveLimit.engineClock; - uint32_t i = 0; - - if (hwmgr->od_enabled) - dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) - &(data->odn_dpm_table.vdd_dep_on_sclk); - else - dep_on_sclk = table_info->vdd_dep_on_sclk; - - PP_ASSERT_WITH_CODE(dep_on_sclk, - "Invalid SOC_VDD-GFX_CLK Dependency Table!", - return -EINVAL); - - if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) - gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock; - else { - for (i = 0; i < dep_on_sclk->count; i++) { - if (dep_on_sclk->entries[i].clk == gfx_clock) - break; - } - PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, - "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", - return -EINVAL); - } - - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, - COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK, - gfx_clock, ÷rs), - "Failed to get GFX Clock settings from VBIOS!", - return -EINVAL); - - /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */ - current_gfxclk_level->FbMult = - cpu_to_le32(dividers.ulPll_fb_mult); - /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ - current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; - current_gfxclk_level->SsFbMult = - cpu_to_le32(dividers.ulPll_ss_fbsmult); - current_gfxclk_level->SsSlewFrac = - cpu_to_le16(dividers.usPll_ss_slew_frac); - current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); - - *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */ - - return 0; -} - -/** - * @brief Populates single SMC SOCCLK structure using the provided clock. - * - * @param hwmgr - the address of the hardware manager. - * @param soc_clock - the SOC clock to use to populate the structure. - * @param current_socclk_level - location in PPTable for the SMC SOCCLK structure. - * @return 0 on success.. - */ -static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr, - uint32_t soc_clock, uint8_t *current_soc_did, - uint8_t *current_vol_index) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc; - struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t i; - - if (hwmgr->od_enabled) { - dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *) - &data->odn_dpm_table.vdd_dep_on_socclk; - for (i = 0; i < dep_on_soc->count; i++) { - if (dep_on_soc->entries[i].clk >= soc_clock) - break; - } - } else { - dep_on_soc = table_info->vdd_dep_on_socclk; - for (i = 0; i < dep_on_soc->count; i++) { - if (dep_on_soc->entries[i].clk == soc_clock) - break; - } - } - - PP_ASSERT_WITH_CODE(dep_on_soc->count > i, - "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table", - return -EINVAL); - - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, - COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, - soc_clock, ÷rs), - "Failed to get SOC Clock settings from VBIOS!", - return -EINVAL); - - *current_soc_did = (uint8_t)dividers.ulDid; - *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd); - return 0; -} - -/** -* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states -* -* @param hwmgr the address of the hardware manager -*/ -static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); - int result = 0; - uint32_t i, j; - - for (i = 0; i < dpm_table->count; i++) { - result = vega10_populate_single_gfx_level(hwmgr, - dpm_table->dpm_levels[i].value, - &(pp_table->GfxclkLevel[i]), - &(pp_table->AcgFreqTable[i])); - if (result) - return result; - } - - j = i - 1; - while (i < NUM_GFXCLK_DPM_LEVELS) { - result = vega10_populate_single_gfx_level(hwmgr, - dpm_table->dpm_levels[j].value, - &(pp_table->GfxclkLevel[i]), - &(pp_table->AcgFreqTable[i])); - if (result) - return result; - i++; - } - - pp_table->GfxclkSlewRate = - cpu_to_le16(table_info->us_gfxclk_slew_rate); - - dpm_table = &(data->dpm_table.soc_table); - for (i = 0; i < dpm_table->count; i++) { - result = vega10_populate_single_soc_level(hwmgr, - dpm_table->dpm_levels[i].value, - &(pp_table->SocclkDid[i]), - &(pp_table->SocDpmVoltageIndex[i])); - if (result) - return result; - } - - j = i - 1; - while (i < NUM_SOCCLK_DPM_LEVELS) { - result = vega10_populate_single_soc_level(hwmgr, - dpm_table->dpm_levels[j].value, - &(pp_table->SocclkDid[i]), - &(pp_table->SocDpmVoltageIndex[i])); - if (result) - return result; - i++; - } - - return result; -} - -static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct phm_ppt_v2_information *table_info = hwmgr->pptable; - struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; - - uint8_t soc_vid = 0; - uint32_t i, max_vddc_level; - - if (hwmgr->od_enabled) - vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table; - else - vddc_lookup_table = table_info->vddc_lookup_table; - - max_vddc_level = vddc_lookup_table->count; - for (i = 0; i < max_vddc_level; i++) { - soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd); - pp_table->SocVid[i] = soc_vid; - } - while (i < MAX_REGULAR_DPM_NUMBER) { - pp_table->SocVid[i] = soc_vid; - i++; - } -} - -/** - * @brief Populates single SMC GFXCLK structure using the provided clock. - * - * @param hwmgr - the address of the hardware manager. - * @param mem_clock - the memory clock to use to populate the structure. - * @return 0 on success.. - */ -static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, - uint32_t mem_clock, uint8_t *current_mem_vid, - PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk; - struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t mem_max_clock = - hwmgr->platform_descriptor.overdriveLimit.memoryClock; - uint32_t i = 0; - - if (hwmgr->od_enabled) - dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) - &data->odn_dpm_table.vdd_dep_on_mclk; - else - dep_on_mclk = table_info->vdd_dep_on_mclk; - - PP_ASSERT_WITH_CODE(dep_on_mclk, - "Invalid SOC_VDD-UCLK Dependency Table!", - return -EINVAL); - - if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { - mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock; - } else { - for (i = 0; i < dep_on_mclk->count; i++) { - if (dep_on_mclk->entries[i].clk == mem_clock) - break; - } - PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, - "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", - return -EINVAL); - } - - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( - hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs), - "Failed to get UCLK settings from VBIOS!", - return -1); - - *current_mem_vid = - (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd)); - *current_mem_soc_vind = - (uint8_t)(dep_on_mclk->entries[i].vddInd); - current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult); - current_memclk_level->Did = (uint8_t)(dividers.ulDid); - - PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1, - "Invalid Divider ID!", - return -EINVAL); - - return 0; -} - -/** - * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states. - * - * @param pHwMgr - the address of the hardware manager. - * @return PP_Result_OK on success. - */ -static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct vega10_single_dpm_table *dpm_table = - &(data->dpm_table.mem_table); - int result = 0; - uint32_t i, j; - - for (i = 0; i < dpm_table->count; i++) { - result = vega10_populate_single_memory_level(hwmgr, - dpm_table->dpm_levels[i].value, - &(pp_table->MemVid[i]), - &(pp_table->UclkLevel[i]), - &(pp_table->MemSocVoltageIndex[i])); - if (result) - return result; - } - - j = i - 1; - while (i < NUM_UCLK_DPM_LEVELS) { - result = vega10_populate_single_memory_level(hwmgr, - dpm_table->dpm_levels[j].value, - &(pp_table->MemVid[i]), - &(pp_table->UclkLevel[i]), - &(pp_table->MemSocVoltageIndex[i])); - if (result) - return result; - i++; - } - - pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels); - pp_table->MemoryChannelWidth = - (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH * - channel_number[data->mem_channels]); - - pp_table->LowestUclkReservedForUlv = - (uint8_t)(data->lowest_uclk_reserved_for_ulv); - - return result; -} - -static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr, - DSPCLK_e disp_clock) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *) - (hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; - uint32_t i; - uint16_t clk = 0, vddc = 0; - uint8_t vid = 0; - - switch (disp_clock) { - case DSPCLK_DCEFCLK: - dep_table = table_info->vdd_dep_on_dcefclk; - break; - case DSPCLK_DISPCLK: - dep_table = table_info->vdd_dep_on_dispclk; - break; - case DSPCLK_PIXCLK: - dep_table = table_info->vdd_dep_on_pixclk; - break; - case DSPCLK_PHYCLK: - dep_table = table_info->vdd_dep_on_phyclk; - break; - default: - return -1; - } - - PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS, - "Number Of Entries Exceeded maximum!", - return -1); - - for (i = 0; i < dep_table->count; i++) { - clk = (uint16_t)(dep_table->entries[i].clk / 100); - vddc = table_info->vddc_lookup_table-> - entries[dep_table->entries[i].vddInd].us_vdd; - vid = (uint8_t)convert_to_vid(vddc); - pp_table->DisplayClockTable[disp_clock][i].Freq = - cpu_to_le16(clk); - pp_table->DisplayClockTable[disp_clock][i].Vid = - cpu_to_le16(vid); - } - - while (i < NUM_DSPCLK_LEVELS) { - pp_table->DisplayClockTable[disp_clock][i].Freq = - cpu_to_le16(clk); - pp_table->DisplayClockTable[disp_clock][i].Vid = - cpu_to_le16(vid); - i++; - } - - return 0; -} - -static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr) -{ - uint32_t i; - - for (i = 0; i < DSPCLK_COUNT; i++) { - PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i), - "Failed to populate Clock in DisplayClockTable!", - return -1); - } - - return 0; -} - -static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, - uint32_t eclock, uint8_t *current_eclk_did, - uint8_t *current_soc_vol) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = - table_info->mm_dep_table; - struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t i; - - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, - COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, - eclock, ÷rs), - "Failed to get ECLK clock settings from VBIOS!", - return -1); - - *current_eclk_did = (uint8_t)dividers.ulDid; - - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].eclk == eclock) - *current_soc_vol = dep_table->entries[i].vddcInd; - } - - return 0; -} - -static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); - int result = -EINVAL; - uint32_t i, j; - - for (i = 0; i < dpm_table->count; i++) { - result = vega10_populate_single_eclock_level(hwmgr, - dpm_table->dpm_levels[i].value, - &(pp_table->EclkDid[i]), - &(pp_table->VceDpmVoltageIndex[i])); - if (result) - return result; - } - - j = i - 1; - while (i < NUM_VCE_DPM_LEVELS) { - result = vega10_populate_single_eclock_level(hwmgr, - dpm_table->dpm_levels[j].value, - &(pp_table->EclkDid[i]), - &(pp_table->VceDpmVoltageIndex[i])); - if (result) - return result; - i++; - } - - return result; -} - -static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr, - uint32_t vclock, uint8_t *current_vclk_did) -{ - struct pp_atomfwctrl_clock_dividers_soc15 dividers; - - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, - COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, - vclock, ÷rs), - "Failed to get VCLK clock settings from VBIOS!", - return -EINVAL); - - *current_vclk_did = (uint8_t)dividers.ulDid; - - return 0; -} - -static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, - uint32_t dclock, uint8_t *current_dclk_did) -{ - struct pp_atomfwctrl_clock_dividers_soc15 dividers; - - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, - COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, - dclock, ÷rs), - "Failed to get DCLK clock settings from VBIOS!", - return -EINVAL); - - *current_dclk_did = (uint8_t)dividers.ulDid; - - return 0; -} - -static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct vega10_single_dpm_table *vclk_dpm_table = - &(data->dpm_table.vclk_table); - struct vega10_single_dpm_table *dclk_dpm_table = - &(data->dpm_table.dclk_table); - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = - table_info->mm_dep_table; - int result = -EINVAL; - uint32_t i, j; - - for (i = 0; i < vclk_dpm_table->count; i++) { - result = vega10_populate_single_vclock_level(hwmgr, - vclk_dpm_table->dpm_levels[i].value, - &(pp_table->VclkDid[i])); - if (result) - return result; - } - - j = i - 1; - while (i < NUM_UVD_DPM_LEVELS) { - result = vega10_populate_single_vclock_level(hwmgr, - vclk_dpm_table->dpm_levels[j].value, - &(pp_table->VclkDid[i])); - if (result) - return result; - i++; - } - - for (i = 0; i < dclk_dpm_table->count; i++) { - result = vega10_populate_single_dclock_level(hwmgr, - dclk_dpm_table->dpm_levels[i].value, - &(pp_table->DclkDid[i])); - if (result) - return result; - } - - j = i - 1; - while (i < NUM_UVD_DPM_LEVELS) { - result = vega10_populate_single_dclock_level(hwmgr, - dclk_dpm_table->dpm_levels[j].value, - &(pp_table->DclkDid[i])); - if (result) - return result; - i++; - } - - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].vclk == - vclk_dpm_table->dpm_levels[i].value && - dep_table->entries[i].dclk == - dclk_dpm_table->dpm_levels[i].value) - pp_table->UvdDpmVoltageIndex[i] = - dep_table->entries[i].vddcInd; - else - return -1; - } - - j = i - 1; - while (i < NUM_UVD_DPM_LEVELS) { - pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd; - i++; - } - - return 0; -} - -static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = - table_info->vdd_dep_on_sclk; - uint32_t i; - - for (i = 0; i < dep_table->count; i++) { - pp_table->CksEnable[i] = dep_table->entries[i].cks_enable; - pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset - * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); - } - - return 0; -} - -static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = - table_info->vdd_dep_on_sclk; - struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; - int result = 0; - uint32_t i; - - pp_table->MinVoltageVid = (uint8_t)0xff; - pp_table->MaxVoltageVid = (uint8_t)0; - - if (data->smu_features[GNLD_AVFS].supported) { - result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); - if (!result) { - pp_table->MinVoltageVid = (uint8_t) - convert_to_vid((uint16_t)(avfs_params.ulMinVddc)); - pp_table->MaxVoltageVid = (uint8_t) - convert_to_vid((uint16_t)(avfs_params.ulMaxVddc)); - - pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0); - pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1); - pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2); - pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); - pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean); - pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); - pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor); - - pp_table->BtcGbVdroopTableCksOff.a0 = - cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0); - pp_table->BtcGbVdroopTableCksOff.a0_shift = 20; - pp_table->BtcGbVdroopTableCksOff.a1 = - cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1); - pp_table->BtcGbVdroopTableCksOff.a1_shift = 20; - pp_table->BtcGbVdroopTableCksOff.a2 = - cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2); - pp_table->BtcGbVdroopTableCksOff.a2_shift = 20; - - pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson; - pp_table->BtcGbVdroopTableCksOn.a0 = - cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0); - pp_table->BtcGbVdroopTableCksOn.a0_shift = 20; - pp_table->BtcGbVdroopTableCksOn.a1 = - cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1); - pp_table->BtcGbVdroopTableCksOn.a1_shift = 20; - pp_table->BtcGbVdroopTableCksOn.a2 = - cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2); - pp_table->BtcGbVdroopTableCksOn.a2_shift = 20; - - pp_table->AvfsGbCksOn.m1 = - cpu_to_le32(avfs_params.ulGbFuseTableCksonM1); - pp_table->AvfsGbCksOn.m2 = - cpu_to_le32(avfs_params.ulGbFuseTableCksonM2); - pp_table->AvfsGbCksOn.b = - cpu_to_le32(avfs_params.ulGbFuseTableCksonB); - pp_table->AvfsGbCksOn.m1_shift = 24; - pp_table->AvfsGbCksOn.m2_shift = 12; - pp_table->AvfsGbCksOn.b_shift = 0; - - pp_table->OverrideAvfsGbCksOn = - avfs_params.ucEnableGbFuseTableCkson; - pp_table->AvfsGbCksOff.m1 = - cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1); - pp_table->AvfsGbCksOff.m2 = - cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2); - pp_table->AvfsGbCksOff.b = - cpu_to_le32(avfs_params.ulGbFuseTableCksoffB); - pp_table->AvfsGbCksOff.m1_shift = 24; - pp_table->AvfsGbCksOff.m2_shift = 12; - pp_table->AvfsGbCksOff.b_shift = 0; - - for (i = 0; i < dep_table->count; i++) - pp_table->StaticVoltageOffsetVid[i] = - convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset)); - - if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->disp_clk_quad_eqn_a) && - (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->disp_clk_quad_eqn_b)) { - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = - (int32_t)data->disp_clk_quad_eqn_a; - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = - (int32_t)data->disp_clk_quad_eqn_b; - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = - (int32_t)data->disp_clk_quad_eqn_c; - } else { - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = - (int32_t)avfs_params.ulDispclk2GfxclkM1; - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = - (int32_t)avfs_params.ulDispclk2GfxclkM2; - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = - (int32_t)avfs_params.ulDispclk2GfxclkB; - } - - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24; - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12; - pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12; - - if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->dcef_clk_quad_eqn_a) && - (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->dcef_clk_quad_eqn_b)) { - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = - (int32_t)data->dcef_clk_quad_eqn_a; - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = - (int32_t)data->dcef_clk_quad_eqn_b; - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = - (int32_t)data->dcef_clk_quad_eqn_c; - } else { - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = - (int32_t)avfs_params.ulDcefclk2GfxclkM1; - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = - (int32_t)avfs_params.ulDcefclk2GfxclkM2; - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = - (int32_t)avfs_params.ulDcefclk2GfxclkB; - } - - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24; - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12; - pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12; - - if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->pixel_clk_quad_eqn_a) && - (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->pixel_clk_quad_eqn_b)) { - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = - (int32_t)data->pixel_clk_quad_eqn_a; - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = - (int32_t)data->pixel_clk_quad_eqn_b; - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = - (int32_t)data->pixel_clk_quad_eqn_c; - } else { - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = - (int32_t)avfs_params.ulPixelclk2GfxclkM1; - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = - (int32_t)avfs_params.ulPixelclk2GfxclkM2; - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = - (int32_t)avfs_params.ulPixelclk2GfxclkB; - } - - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24; - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12; - pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12; - if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->phy_clk_quad_eqn_a) && - (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != - data->phy_clk_quad_eqn_b)) { - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = - (int32_t)data->phy_clk_quad_eqn_a; - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = - (int32_t)data->phy_clk_quad_eqn_b; - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = - (int32_t)data->phy_clk_quad_eqn_c; - } else { - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = - (int32_t)avfs_params.ulPhyclk2GfxclkM1; - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = - (int32_t)avfs_params.ulPhyclk2GfxclkM2; - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = - (int32_t)avfs_params.ulPhyclk2GfxclkB; - } - - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24; - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12; - pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12; - - pp_table->AcgBtcGbVdroopTable.a0 = avfs_params.ulAcgGbVdroopTableA0; - pp_table->AcgBtcGbVdroopTable.a0_shift = 20; - pp_table->AcgBtcGbVdroopTable.a1 = avfs_params.ulAcgGbVdroopTableA1; - pp_table->AcgBtcGbVdroopTable.a1_shift = 20; - pp_table->AcgBtcGbVdroopTable.a2 = avfs_params.ulAcgGbVdroopTableA2; - pp_table->AcgBtcGbVdroopTable.a2_shift = 20; - - pp_table->AcgAvfsGb.m1 = avfs_params.ulAcgGbFuseTableM1; - pp_table->AcgAvfsGb.m2 = avfs_params.ulAcgGbFuseTableM2; - pp_table->AcgAvfsGb.b = avfs_params.ulAcgGbFuseTableB; - pp_table->AcgAvfsGb.m1_shift = 24; - pp_table->AcgAvfsGb.m2_shift = 12; - pp_table->AcgAvfsGb.b_shift = 0; - - } else { - data->smu_features[GNLD_AVFS].supported = false; - } - } - - return 0; -} - -static int vega10_acg_enable(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t agc_btc_response; - - if (data->smu_features[GNLD_ACG].supported) { - if (0 == vega10_enable_smc_features(hwmgr, true, - data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) - data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL); - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response); - - if (1 == agc_btc_response) { - if (1 == data->acg_loop_state) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL); - else if (2 == data->acg_loop_state) - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL); - if (0 == vega10_enable_smc_features(hwmgr, true, - data->smu_features[GNLD_ACG].smu_feature_bitmap)) - data->smu_features[GNLD_ACG].enabled = true; - } else { - pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n"); - data->smu_features[GNLD_ACG].enabled = false; - } - } - - return 0; -} - -static int vega10_acg_disable(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_ACG].supported && - data->smu_features[GNLD_ACG].enabled) - if (!vega10_enable_smc_features(hwmgr, false, - data->smu_features[GNLD_ACG].smu_feature_bitmap)) - data->smu_features[GNLD_ACG].enabled = false; - - return 0; -} - -static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct pp_atomfwctrl_gpio_parameters gpio_params = {0}; - int result; - - result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); - if (!result) { - if (PP_CAP(PHM_PlatformCaps_RegulatorHot) && - data->registry_data.regulator_hot_gpio_support) { - pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; - pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; - pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio; - pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity; - } else { - pp_table->VR0HotGpio = 0; - pp_table->VR0HotPolarity = 0; - pp_table->VR1HotGpio = 0; - pp_table->VR1HotPolarity = 0; - } - - if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) && - data->registry_data.ac_dc_switch_gpio_support) { - pp_table->AcDcGpio = gpio_params.ucAcDcGpio; - pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; - } else { - pp_table->AcDcGpio = 0; - pp_table->AcDcPolarity = 0; - } - } - - return result; -} - -static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_AVFS].supported) { - /* Already enabled or disabled */ - if (!(enable ^ data->smu_features[GNLD_AVFS].enabled)) - return 0; - - if (enable) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, - data->smu_features[GNLD_AVFS].smu_feature_bitmap), - "[avfs_control] Attempt to Enable AVFS feature Failed!", - return -1); - data->smu_features[GNLD_AVFS].enabled = true; - } else { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, - data->smu_features[GNLD_AVFS].smu_feature_bitmap), - "[avfs_control] Attempt to Disable AVFS feature Failed!", - return -1); - data->smu_features[GNLD_AVFS].enabled = false; - } - } - - return 0; -} - -static int vega10_update_avfs(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { - vega10_avfs_enable(hwmgr, false); - } else if (data->need_update_dpm_table) { - vega10_avfs_enable(hwmgr, false); - vega10_avfs_enable(hwmgr, true); - } else { - vega10_avfs_enable(hwmgr, true); - } - - return 0; -} - -static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) -{ - int result = 0; - - uint64_t serial_number = 0; - uint32_t top32, bottom32; - struct phm_fuses_default fuse; - - struct vega10_hwmgr *data = hwmgr->backend; - AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); - - serial_number = ((uint64_t)bottom32 << 32) | top32; - - if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) { - avfs_fuse_table->VFT0_b = fuse.VFT0_b; - avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; - avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; - avfs_fuse_table->VFT1_b = fuse.VFT1_b; - avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; - avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; - avfs_fuse_table->VFT2_b = fuse.VFT2_b; - avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; - avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; - result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table, - AVFSFUSETABLE, false); - PP_ASSERT_WITH_CODE(!result, - "Failed to upload FuseOVerride!", - ); - } - - return result; -} - -static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); - struct phm_ppt_v2_information *table_info = hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; - struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; - uint32_t i; - - dep_table = table_info->vdd_dep_on_mclk; - odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk); - - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; - return; - } - } - - dep_table = table_info->vdd_dep_on_sclk; - odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk); - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; - return; - } - } -} - -/** -* Initializes the SMC table and uploads it -* -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data (PowerState) -* @return always 0 -*/ -static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) -{ - int result; - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct pp_atomfwctrl_voltage_table voltage_table; - struct pp_atomfwctrl_bios_boot_up_values boot_up_values; - struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); - - result = vega10_setup_default_dpm_tables(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to setup default DPM tables!", - return result); - - if (!hwmgr->not_vf) - return 0; - - /* initialize ODN table */ - if (hwmgr->od_enabled) { - if (odn_table->max_vddc) { - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; - vega10_check_dpm_table_updated(hwmgr); - } else { - vega10_odn_initial_default_setting(hwmgr); - } - } - - pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, - VOLTAGE_OBJ_SVID2, &voltage_table); - pp_table->MaxVidStep = voltage_table.max_vid_step; - - pp_table->GfxDpmVoltageMode = - (uint8_t)(table_info->uc_gfx_dpm_voltage_mode); - pp_table->SocDpmVoltageMode = - (uint8_t)(table_info->uc_soc_dpm_voltage_mode); - pp_table->UclkDpmVoltageMode = - (uint8_t)(table_info->uc_uclk_dpm_voltage_mode); - pp_table->UvdDpmVoltageMode = - (uint8_t)(table_info->uc_uvd_dpm_voltage_mode); - pp_table->VceDpmVoltageMode = - (uint8_t)(table_info->uc_vce_dpm_voltage_mode); - pp_table->Mp0DpmVoltageMode = - (uint8_t)(table_info->uc_mp0_dpm_voltage_mode); - - pp_table->DisplayDpmVoltageMode = - (uint8_t)(table_info->uc_dcef_dpm_voltage_mode); - - data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable; - data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable; - - if (data->registry_data.ulv_support && - table_info->us_ulv_voltage_offset) { - result = vega10_populate_ulv_state(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize ULV state!", - return result); - } - - result = vega10_populate_smc_link_levels(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize Link Level!", - return result); - - result = vega10_populate_all_graphic_levels(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize Graphics Level!", - return result); - - result = vega10_populate_all_memory_levels(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize Memory Level!", - return result); - - vega10_populate_vddc_soc_levels(hwmgr); - - result = vega10_populate_all_display_clock_levels(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize Display Level!", - return result); - - result = vega10_populate_smc_vce_levels(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize VCE Level!", - return result); - - result = vega10_populate_smc_uvd_levels(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize UVD Level!", - return result); - - if (data->registry_data.clock_stretcher_support) { - result = vega10_populate_clock_stretcher_table(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to populate Clock Stretcher Table!", - return result); - } - - result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); - if (!result) { - data->vbios_boot_state.vddc = boot_up_values.usVddc; - data->vbios_boot_state.vddci = boot_up_values.usVddci; - data->vbios_boot_state.mvddc = boot_up_values.usMvddc; - data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; - data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; - pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, - SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk); - - pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, - SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk); - - data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; - data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; - if (0 != boot_up_values.usVddc) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFloorSocVoltage, - (boot_up_values.usVddc * 4), - NULL); - data->vbios_boot_state.bsoc_vddc_lock = true; - } else { - data->vbios_boot_state.bsoc_vddc_lock = false; - } - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetMinDeepSleepDcefclk, - (uint32_t)(data->vbios_boot_state.dcef_clock / 100), - NULL); - } - - result = vega10_populate_avfs_parameters(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize AVFS Parameters!", - return result); - - result = vega10_populate_gpio_parameters(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to initialize GPIO Parameters!", - return result); - - pp_table->GfxclkAverageAlpha = (uint8_t) - (data->gfxclk_average_alpha); - pp_table->SocclkAverageAlpha = (uint8_t) - (data->socclk_average_alpha); - pp_table->UclkAverageAlpha = (uint8_t) - (data->uclk_average_alpha); - pp_table->GfxActivityAverageAlpha = (uint8_t) - (data->gfx_activity_average_alpha); - - vega10_populate_and_upload_avfs_fuse_override(hwmgr); - - result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); - - PP_ASSERT_WITH_CODE(!result, - "Failed to upload PPtable!", return result); - - result = vega10_avfs_enable(hwmgr, true); - PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", - return result); - vega10_acg_enable(hwmgr); - - return 0; -} - -static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_THERMAL].supported) { - if (data->smu_features[GNLD_THERMAL].enabled) - pr_info("THERMAL Feature Already enabled!"); - - PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr, - true, - data->smu_features[GNLD_THERMAL].smu_feature_bitmap), - "Enable THERMAL Feature Failed!", - return -1); - data->smu_features[GNLD_THERMAL].enabled = true; - } - - return 0; -} - -static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_THERMAL].supported) { - if (!data->smu_features[GNLD_THERMAL].enabled) - pr_info("THERMAL Feature Already disabled!"); - - PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr, - false, - data->smu_features[GNLD_THERMAL].smu_feature_bitmap), - "disable THERMAL Feature Failed!", - return -1); - data->smu_features[GNLD_THERMAL].enabled = false; - } - - return 0; -} - -static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { - if (data->smu_features[GNLD_VR0HOT].supported) { - PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr, - true, - data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), - "Attempt to Enable VR0 Hot feature Failed!", - return -1); - data->smu_features[GNLD_VR0HOT].enabled = true; - } else { - if (data->smu_features[GNLD_VR1HOT].supported) { - PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr, - true, - data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), - "Attempt to Enable VR0 Hot feature Failed!", - return -1); - data->smu_features[GNLD_VR1HOT].enabled = true; - } - } - } - return 0; -} - -static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->registry_data.ulv_support) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_ULV].smu_feature_bitmap), - "Enable ULV Feature Failed!", - return -1); - data->smu_features[GNLD_ULV].enabled = true; - } - - return 0; -} - -static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->registry_data.ulv_support) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_ULV].smu_feature_bitmap), - "disable ULV Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_ULV].enabled = false; - } - - return 0; -} - -static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_DS_GFXCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), - "Attempt to Enable DS_GFXCLK Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_GFXCLK].enabled = true; - } - - if (data->smu_features[GNLD_DS_SOCCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), - "Attempt to Enable DS_SOCCLK Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_SOCCLK].enabled = true; - } - - if (data->smu_features[GNLD_DS_LCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), - "Attempt to Enable DS_LCLK Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_LCLK].enabled = true; - } - - if (data->smu_features[GNLD_DS_DCEFCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), - "Attempt to Enable DS_DCEFCLK Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_DCEFCLK].enabled = true; - } - - return 0; -} - -static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_DS_GFXCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), - "Attempt to disable DS_GFXCLK Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_GFXCLK].enabled = false; - } - - if (data->smu_features[GNLD_DS_SOCCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), - "Attempt to disable DS_ Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_SOCCLK].enabled = false; - } - - if (data->smu_features[GNLD_DS_LCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), - "Attempt to disable DS_LCLK Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_LCLK].enabled = false; - } - - if (data->smu_features[GNLD_DS_DCEFCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), - "Attempt to disable DS_DCEFCLK Feature Failed!", - return -EINVAL); - data->smu_features[GNLD_DS_DCEFCLK].enabled = false; - } - - return 0; -} - -static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t i, feature_mask = 0; - - if (!hwmgr->not_vf) - return 0; - - if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), - "Attempt to disable LED DPM feature failed!", return -EINVAL); - data->smu_features[GNLD_LED_DISPLAY].enabled = false; - } - - for (i = 0; i < GNLD_DPM_MAX; i++) { - if (data->smu_features[i].smu_feature_bitmap & bitmap) { - if (data->smu_features[i].supported) { - if (data->smu_features[i].enabled) { - feature_mask |= data->smu_features[i]. - smu_feature_bitmap; - data->smu_features[i].enabled = false; - } - } - } - } - - vega10_enable_smc_features(hwmgr, false, feature_mask); - - return 0; -} - -/** - * @brief Tell SMC to enabled the supported DPMs. - * - * @param hwmgr - the address of the powerplay hardware manager. - * @Param bitmap - bitmap for the features to enabled. - * @return 0 on at least one DPM is successfully enabled. - */ -static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t i, feature_mask = 0; - - for (i = 0; i < GNLD_DPM_MAX; i++) { - if (data->smu_features[i].smu_feature_bitmap & bitmap) { - if (data->smu_features[i].supported) { - if (!data->smu_features[i].enabled) { - feature_mask |= data->smu_features[i]. - smu_feature_bitmap; - data->smu_features[i].enabled = true; - } - } - } - } - - if (vega10_enable_smc_features(hwmgr, - true, feature_mask)) { - for (i = 0; i < GNLD_DPM_MAX; i++) { - if (data->smu_features[i].smu_feature_bitmap & - feature_mask) - data->smu_features[i].enabled = false; - } - } - - if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), - "Attempt to Enable LED DPM feature Failed!", return -EINVAL); - data->smu_features[GNLD_LED_DISPLAY].enabled = true; - } - - if (data->vbios_boot_state.bsoc_vddc_lock) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFloorSocVoltage, 0, - NULL); - data->vbios_boot_state.bsoc_vddc_lock = false; - } - - if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { - if (data->smu_features[GNLD_ACDC].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), - "Attempt to Enable DS_GFXCLK Feature Failed!", - return -1); - data->smu_features[GNLD_ACDC].enabled = true; - } - } - - return 0; -} - -static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_PCC_LIMIT].supported) { - if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled) - pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled"); - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap), - "Attempt to Enable PCC Limit feature Failed!", - return -EINVAL); - data->smu_features[GNLD_PCC_LIMIT].enabled = enable; - } - - return 0; -} - -static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - int tmp_result, result = 0; - - if (hwmgr->not_vf) { - vega10_enable_disable_PCC_limit_feature(hwmgr, true); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_ConfigureTelemetry, data->config_telemetry, - NULL); - - tmp_result = vega10_construct_voltage_tables(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to construct voltage tables!", - result = tmp_result); - } - - if (hwmgr->not_vf || hwmgr->pp_one_vf) { - tmp_result = vega10_init_smc_table(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to initialize SMC table!", - result = tmp_result); - } - - if (hwmgr->not_vf) { - if (PP_CAP(PHM_PlatformCaps_ThermalController)) { - tmp_result = vega10_enable_thermal_protection(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable thermal protection!", - result = tmp_result); - } - - tmp_result = vega10_enable_vrhot_feature(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable VR hot feature!", - result = tmp_result); - - tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable deep sleep master switch!", - result = tmp_result); - } - - if (hwmgr->not_vf) { - tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to start DPM!", result = tmp_result); - } - - if (hwmgr->not_vf) { - /* enable didt, do not abort if failed didt */ - tmp_result = vega10_enable_didt_config(hwmgr); - PP_ASSERT(!tmp_result, - "Failed to enable didt config!"); - } - - tmp_result = vega10_enable_power_containment(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable power containment!", - result = tmp_result); - - if (hwmgr->not_vf) { - tmp_result = vega10_power_control_set_level(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to power control set level!", - result = tmp_result); - - tmp_result = vega10_enable_ulv(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable ULV!", - result = tmp_result); - } - - return result; -} - -static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr) -{ - return sizeof(struct vega10_power_state); -} - -static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, - void *state, struct pp_power_state *power_state, - void *pp_table, uint32_t classification_flag) -{ - ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2; - struct vega10_power_state *vega10_power_state = - cast_phw_vega10_power_state(&(power_state->hardware)); - struct vega10_performance_level *performance_level; - ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state; - ATOM_Vega10_POWERPLAYTABLE *powerplay_table = - (ATOM_Vega10_POWERPLAYTABLE *)pp_table; - ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table = - (ATOM_Vega10_SOCCLK_Dependency_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset)); - ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = - (ATOM_Vega10_GFXCLK_Dependency_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); - ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table = - (ATOM_Vega10_MCLK_Dependency_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); - - - /* The following fields are not initialized here: - * id orderedList allStatesList - */ - power_state->classification.ui_label = - (le16_to_cpu(state_entry->usClassification) & - ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> - ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; - power_state->classification.flags = classification_flag; - /* NOTE: There is a classification2 flag in BIOS - * that is not being used right now - */ - power_state->classification.temporary_state = false; - power_state->classification.to_be_deleted = false; - - power_state->validation.disallowOnDC = - ((le32_to_cpu(state_entry->ulCapsAndSettings) & - ATOM_Vega10_DISALLOW_ON_DC) != 0); - - power_state->display.disableFrameModulation = false; - power_state->display.limitRefreshrate = false; - power_state->display.enableVariBright = - ((le32_to_cpu(state_entry->ulCapsAndSettings) & - ATOM_Vega10_ENABLE_VARIBRIGHT) != 0); - - power_state->validation.supportedPowerLevels = 0; - power_state->uvd_clocks.VCLK = 0; - power_state->uvd_clocks.DCLK = 0; - power_state->temperatures.min = 0; - power_state->temperatures.max = 0; - - performance_level = &(vega10_power_state->performance_levels - [vega10_power_state->performance_level_count++]); - - PP_ASSERT_WITH_CODE( - (vega10_power_state->performance_level_count < - NUM_GFXCLK_DPM_LEVELS), - "Performance levels exceeds SMC limit!", - return -1); - - PP_ASSERT_WITH_CODE( - (vega10_power_state->performance_level_count <= - hwmgr->platform_descriptor. - hardwareActivityPerformanceLevels), - "Performance levels exceeds Driver limit!", - return -1); - - /* Performance levels are arranged from low to high. */ - performance_level->soc_clock = socclk_dep_table->entries - [state_entry->ucSocClockIndexLow].ulClk; - performance_level->gfx_clock = gfxclk_dep_table->entries - [state_entry->ucGfxClockIndexLow].ulClk; - performance_level->mem_clock = mclk_dep_table->entries - [state_entry->ucMemClockIndexLow].ulMemClk; - - performance_level = &(vega10_power_state->performance_levels - [vega10_power_state->performance_level_count++]); - performance_level->soc_clock = socclk_dep_table->entries - [state_entry->ucSocClockIndexHigh].ulClk; - if (gfxclk_dep_table->ucRevId == 0) { - /* under vega10 pp one vf mode, the gfx clk dpm need be lower - * to level-4 due to the limited 110w-power - */ - if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) - performance_level->gfx_clock = - gfxclk_dep_table->entries[4].ulClk; - else - performance_level->gfx_clock = gfxclk_dep_table->entries - [state_entry->ucGfxClockIndexHigh].ulClk; - } else if (gfxclk_dep_table->ucRevId == 1) { - patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; - if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) - performance_level->gfx_clock = patom_record_V2[4].ulClk; - else - performance_level->gfx_clock = - patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk; - } - - performance_level->mem_clock = mclk_dep_table->entries - [state_entry->ucMemClockIndexHigh].ulMemClk; - return 0; -} - -static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr, - unsigned long entry_index, struct pp_power_state *state) -{ - int result; - struct vega10_power_state *ps; - - state->hardware.magic = PhwVega10_Magic; - - ps = cast_phw_vega10_power_state(&state->hardware); - - result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state, - vega10_get_pp_table_entry_callback_func); - - /* - * This is the earliest time we have all the dependency table - * and the VBIOS boot state - */ - /* set DC compatible flag if this state supports DC */ - if (!state->validation.disallowOnDC) - ps->dc_compatible = true; - - ps->uvd_clks.vclk = state->uvd_clocks.VCLK; - ps->uvd_clks.dclk = state->uvd_clocks.DCLK; - - return 0; -} - -static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps) -{ - return 0; -} - -static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, - struct pp_power_state *request_ps, - const struct pp_power_state *current_ps) -{ - struct amdgpu_device *adev = hwmgr->adev; - struct vega10_power_state *vega10_ps = - cast_phw_vega10_power_state(&request_ps->hardware); - uint32_t sclk; - uint32_t mclk; - struct PP_Clocks minimum_clocks = {0}; - bool disable_mclk_switching; - bool disable_mclk_switching_for_frame_lock; - bool disable_mclk_switching_for_vr; - bool force_mclk_high; - const struct phm_clock_and_voltage_limits *max_limits; - uint32_t i; - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - int32_t count; - uint32_t stable_pstate_sclk_dpm_percentage; - uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; - uint32_t latency; - - data->battery_state = (PP_StateUILabel_Battery == - request_ps->classification.ui_label); - - if (vega10_ps->performance_level_count != 2) - pr_info("VI should always have 2 performance levels"); - - max_limits = adev->pm.ac_power ? - &(hwmgr->dyn_state.max_clock_voltage_on_ac) : - &(hwmgr->dyn_state.max_clock_voltage_on_dc); - - /* Cap clock DPM tables at DC MAX if it is in DC. */ - if (!adev->pm.ac_power) { - for (i = 0; i < vega10_ps->performance_level_count; i++) { - if (vega10_ps->performance_levels[i].mem_clock > - max_limits->mclk) - vega10_ps->performance_levels[i].mem_clock = - max_limits->mclk; - if (vega10_ps->performance_levels[i].gfx_clock > - max_limits->sclk) - vega10_ps->performance_levels[i].gfx_clock = - max_limits->sclk; - } - } - - /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ - minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; - minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; - - if (PP_CAP(PHM_PlatformCaps_StablePState)) { - stable_pstate_sclk_dpm_percentage = - data->registry_data.stable_pstate_sclk_dpm_percentage; - PP_ASSERT_WITH_CODE( - data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && - data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, - "percent sclk value must range from 1% to 100%, setting default value", - stable_pstate_sclk_dpm_percentage = 75); - - max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); - stable_pstate_sclk = (max_limits->sclk * - stable_pstate_sclk_dpm_percentage) / 100; - - for (count = table_info->vdd_dep_on_sclk->count - 1; - count >= 0; count--) { - if (stable_pstate_sclk >= - table_info->vdd_dep_on_sclk->entries[count].clk) { - stable_pstate_sclk = - table_info->vdd_dep_on_sclk->entries[count].clk; - break; - } - } - - if (count < 0) - stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; - - stable_pstate_mclk = max_limits->mclk; - - minimum_clocks.engineClock = stable_pstate_sclk; - minimum_clocks.memoryClock = stable_pstate_mclk; - } - - disable_mclk_switching_for_frame_lock = - PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); - disable_mclk_switching_for_vr = - PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); - force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); - - if (hwmgr->display_config->num_display == 0) - disable_mclk_switching = false; - else - disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && - !hwmgr->display_config->multi_monitor_in_sync) || - disable_mclk_switching_for_frame_lock || - disable_mclk_switching_for_vr || - force_mclk_high; - - sclk = vega10_ps->performance_levels[0].gfx_clock; - mclk = vega10_ps->performance_levels[0].mem_clock; - - if (sclk < minimum_clocks.engineClock) - sclk = (minimum_clocks.engineClock > max_limits->sclk) ? - max_limits->sclk : minimum_clocks.engineClock; - - if (mclk < minimum_clocks.memoryClock) - mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? - max_limits->mclk : minimum_clocks.memoryClock; - - vega10_ps->performance_levels[0].gfx_clock = sclk; - vega10_ps->performance_levels[0].mem_clock = mclk; - - if (vega10_ps->performance_levels[1].gfx_clock < - vega10_ps->performance_levels[0].gfx_clock) - vega10_ps->performance_levels[0].gfx_clock = - vega10_ps->performance_levels[1].gfx_clock; - - if (disable_mclk_switching) { - /* Set Mclk the max of level 0 and level 1 */ - if (mclk < vega10_ps->performance_levels[1].mem_clock) - mclk = vega10_ps->performance_levels[1].mem_clock; - - /* Find the lowest MCLK frequency that is within - * the tolerable latency defined in DAL - */ - latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; - for (i = 0; i < data->mclk_latency_table.count; i++) { - if ((data->mclk_latency_table.entries[i].latency <= latency) && - (data->mclk_latency_table.entries[i].frequency >= - vega10_ps->performance_levels[0].mem_clock) && - (data->mclk_latency_table.entries[i].frequency <= - vega10_ps->performance_levels[1].mem_clock)) - mclk = data->mclk_latency_table.entries[i].frequency; - } - vega10_ps->performance_levels[0].mem_clock = mclk; - } else { - if (vega10_ps->performance_levels[1].mem_clock < - vega10_ps->performance_levels[0].mem_clock) - vega10_ps->performance_levels[0].mem_clock = - vega10_ps->performance_levels[1].mem_clock; - } - - if (PP_CAP(PHM_PlatformCaps_StablePState)) { - for (i = 0; i < vega10_ps->performance_level_count; i++) { - vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; - vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk; - } - } - - return 0; -} - -static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) -{ - struct vega10_hwmgr *data = hwmgr->backend; - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - const struct vega10_power_state *vega10_ps = - cast_const_phw_vega10_power_state(states->pnew_state); - struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); - uint32_t sclk = vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].gfx_clock; - struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); - uint32_t mclk = vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].mem_clock; - uint32_t i; - - for (i = 0; i < sclk_table->count; i++) { - if (sclk == sclk_table->dpm_levels[i].value) - break; - } - - if (i >= sclk_table->count) { - if (sclk > sclk_table->dpm_levels[i-1].value) { - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; - sclk_table->dpm_levels[i-1].value = sclk; - } - } - - for (i = 0; i < mclk_table->count; i++) { - if (mclk == mclk_table->dpm_levels[i].value) - break; - } - - if (i >= mclk_table->count) { - if (mclk > mclk_table->dpm_levels[i-1].value) { - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; - mclk_table->dpm_levels[i-1].value = mclk; - } - } - - if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) - data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; - - return 0; -} - -static int vega10_populate_and_upload_sclk_mclk_dpm_levels( - struct pp_hwmgr *hwmgr, const void *input) -{ - int result = 0; - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_dpm_table *dpm_table = &data->dpm_table; - struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table; - struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk; - int count; - - if (!data->need_update_dpm_table) - return 0; - - if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { - for (count = 0; count < dpm_table->gfx_table.count; count++) - dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; - } - - odn_clk_table = &odn_table->vdd_dep_on_mclk; - if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { - for (count = 0; count < dpm_table->mem_table.count; count++) - dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; - } - - if (data->need_update_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { - result = vega10_populate_all_graphic_levels(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", - return result); - } - - if (data->need_update_dpm_table & - (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { - result = vega10_populate_all_memory_levels(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", - return result); - } - - vega10_populate_vddc_soc_levels(hwmgr); - - return result; -} - -static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, - struct vega10_single_dpm_table *dpm_table, - uint32_t low_limit, uint32_t high_limit) -{ - uint32_t i; - - for (i = 0; i < dpm_table->count; i++) { - if ((dpm_table->dpm_levels[i].value < low_limit) || - (dpm_table->dpm_levels[i].value > high_limit)) - dpm_table->dpm_levels[i].enabled = false; - else - dpm_table->dpm_levels[i].enabled = true; - } - return 0; -} - -static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, - struct vega10_single_dpm_table *dpm_table, - uint32_t low_limit, uint32_t high_limit, - uint32_t disable_dpm_mask) -{ - uint32_t i; - - for (i = 0; i < dpm_table->count; i++) { - if ((dpm_table->dpm_levels[i].value < low_limit) || - (dpm_table->dpm_levels[i].value > high_limit)) - dpm_table->dpm_levels[i].enabled = false; - else if (!((1 << i) & disable_dpm_mask)) - dpm_table->dpm_levels[i].enabled = false; - else - dpm_table->dpm_levels[i].enabled = true; - } - return 0; -} - -static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr, - const struct vega10_power_state *vega10_ps) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t high_limit_count; - - PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1), - "power state did not have any performance level", - return -1); - - high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1; - - vega10_trim_single_dpm_states(hwmgr, - &(data->dpm_table.soc_table), - vega10_ps->performance_levels[0].soc_clock, - vega10_ps->performance_levels[high_limit_count].soc_clock); - - vega10_trim_single_dpm_states_with_mask(hwmgr, - &(data->dpm_table.gfx_table), - vega10_ps->performance_levels[0].gfx_clock, - vega10_ps->performance_levels[high_limit_count].gfx_clock, - data->disable_dpm_mask); - - vega10_trim_single_dpm_states(hwmgr, - &(data->dpm_table.mem_table), - vega10_ps->performance_levels[0].mem_clock, - vega10_ps->performance_levels[high_limit_count].mem_clock); - - return 0; -} - -static uint32_t vega10_find_lowest_dpm_level( - struct vega10_single_dpm_table *table) -{ - uint32_t i; - - for (i = 0; i < table->count; i++) { - if (table->dpm_levels[i].enabled) - break; - } - - return i; -} - -static uint32_t vega10_find_highest_dpm_level( - struct vega10_single_dpm_table *table) -{ - uint32_t i = 0; - - if (table->count <= MAX_REGULAR_DPM_NUMBER) { - for (i = table->count; i > 0; i--) { - if (table->dpm_levels[i - 1].enabled) - return i - 1; - } - } else { - pr_info("DPM Table Has Too Many Entries!"); - return MAX_REGULAR_DPM_NUMBER - 1; - } - - return i; -} - -static void vega10_apply_dal_minimum_voltage_request( - struct pp_hwmgr *hwmgr) -{ - return; -} - -static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - - vdd_dep_table_on_mclk = table_info->vdd_dep_on_mclk; - - return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; -} - -static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t socclk_idx; - - vega10_apply_dal_minimum_voltage_request(hwmgr); - - if (!data->registry_data.sclk_dpm_key_disabled) { - if (data->smc_state_table.gfx_boot_level != - data->dpm_table.gfx_table.dpm_state.soft_min_level) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMinGfxclkByIndex, - data->smc_state_table.gfx_boot_level, - NULL); - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->smc_state_table.gfx_boot_level; - } - } - - if (!data->registry_data.mclk_dpm_key_disabled) { - if (data->smc_state_table.mem_boot_level != - data->dpm_table.mem_table.dpm_state.soft_min_level) { - if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) - && hwmgr->not_vf) { - socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMinSocclkByIndex, - socclk_idx, - NULL); - } else { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMinUclkByIndex, - data->smc_state_table.mem_boot_level, - NULL); - } - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->smc_state_table.mem_boot_level; - } - } - - if (!hwmgr->not_vf) - return 0; - - if (!data->registry_data.socclk_dpm_key_disabled) { - if (data->smc_state_table.soc_boot_level != - data->dpm_table.soc_table.dpm_state.soft_min_level) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMinSocclkByIndex, - data->smc_state_table.soc_boot_level, - NULL); - data->dpm_table.soc_table.dpm_state.soft_min_level = - data->smc_state_table.soc_boot_level; - } - } - - return 0; -} - -static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - vega10_apply_dal_minimum_voltage_request(hwmgr); - - if (!data->registry_data.sclk_dpm_key_disabled) { - if (data->smc_state_table.gfx_max_level != - data->dpm_table.gfx_table.dpm_state.soft_max_level) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxclkByIndex, - data->smc_state_table.gfx_max_level, - NULL); - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->smc_state_table.gfx_max_level; - } - } - - if (!data->registry_data.mclk_dpm_key_disabled) { - if (data->smc_state_table.mem_max_level != - data->dpm_table.mem_table.dpm_state.soft_max_level) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxUclkByIndex, - data->smc_state_table.mem_max_level, - NULL); - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->smc_state_table.mem_max_level; - } - } - - if (!hwmgr->not_vf) - return 0; - - if (!data->registry_data.socclk_dpm_key_disabled) { - if (data->smc_state_table.soc_max_level != - data->dpm_table.soc_table.dpm_state.soft_max_level) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxSocclkByIndex, - data->smc_state_table.soc_max_level, - NULL); - data->dpm_table.soc_table.dpm_state.soft_max_level = - data->smc_state_table.soc_max_level; - } - } - - return 0; -} - -static int vega10_generate_dpm_level_enable_mask( - struct pp_hwmgr *hwmgr, const void *input) -{ - struct vega10_hwmgr *data = hwmgr->backend; - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - const struct vega10_power_state *vega10_ps = - cast_const_phw_vega10_power_state(states->pnew_state); - int i; - - PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), - "Attempt to Trim DPM States Failed!", - return -1); - - data->smc_state_table.gfx_boot_level = - vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); - data->smc_state_table.gfx_max_level = - vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); - data->smc_state_table.mem_boot_level = - vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); - data->smc_state_table.mem_max_level = - vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); - data->smc_state_table.soc_boot_level = - vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table)); - data->smc_state_table.soc_max_level = - vega10_find_highest_dpm_level(&(data->dpm_table.soc_table)); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), - "Attempt to upload DPM Bootup Levels Failed!", - return -1); - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), - "Attempt to upload DPM Max Levels Failed!", - return -1); - for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++) - data->dpm_table.gfx_table.dpm_levels[i].enabled = true; - - - for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++) - data->dpm_table.mem_table.dpm_levels[i].enabled = true; - - for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++) - data->dpm_table.soc_table.dpm_levels[i].enabled = true; - - return 0; -} - -int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_DPM_VCE].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - enable, - data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), - "Attempt to Enable/Disable DPM VCE Failed!", - return -1); - data->smu_features[GNLD_DPM_VCE].enabled = enable; - } - - return 0; -} - -static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t low_sclk_interrupt_threshold = 0; - - if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && - (data->low_sclk_interrupt_threshold != 0)) { - low_sclk_interrupt_threshold = - data->low_sclk_interrupt_threshold; - - data->smc_state_table.pp_table.LowGfxclkInterruptThreshold = - cpu_to_le32(low_sclk_interrupt_threshold); - - /* This message will also enable SmcToHost Interrupt */ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetLowGfxclkInterruptThreshold, - (uint32_t)low_sclk_interrupt_threshold, - NULL); - } - - return 0; -} - -static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, - const void *input) -{ - int tmp_result, result = 0; - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - - tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to find DPM states clocks in DPM table!", - result = tmp_result); - - tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to populate and upload SCLK MCLK DPM levels!", - result = tmp_result); - - tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to generate DPM level enabled mask!", - result = tmp_result); - - tmp_result = vega10_update_sclk_threshold(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to update SCLK threshold!", - result = tmp_result); - - result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); - PP_ASSERT_WITH_CODE(!result, - "Failed to upload PPtable!", return result); - - /* - * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. - * That effectively disables AVFS feature. - */ - if(hwmgr->hardcode_pp_table != NULL) - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; - - vega10_update_avfs(hwmgr); - - /* - * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC. - * That will help to keep AVFS disabled. - */ - data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; - - return 0; -} - -static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct pp_power_state *ps; - struct vega10_power_state *vega10_ps; - - if (hwmgr == NULL) - return -EINVAL; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - vega10_ps = cast_phw_vega10_power_state(&ps->hardware); - - if (low) - return vega10_ps->performance_levels[0].gfx_clock; - else - return vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].gfx_clock; -} - -static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct pp_power_state *ps; - struct vega10_power_state *vega10_ps; - - if (hwmgr == NULL) - return -EINVAL; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - vega10_ps = cast_phw_vega10_power_state(&ps->hardware); - - if (low) - return vega10_ps->performance_levels[0].mem_clock; - else - return vega10_ps->performance_levels - [vega10_ps->performance_level_count-1].mem_clock; -} - -static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, - uint32_t *query) -{ - uint32_t value; - - if (!query) - return -EINVAL; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); - - /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */ - *query = value << 8; - - return 0; -} - -static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, - void *value, int *size) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t sclk_mhz, mclk_idx, activity_percent = 0; - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_dpm_table *dpm_table = &data->dpm_table; - int ret = 0; - uint32_t val_vid; - - switch (idx) { - case AMDGPU_PP_SENSOR_GFX_SCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz); - *((uint32_t *)value) = sclk_mhz * 100; - break; - case AMDGPU_PP_SENSOR_GFX_MCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx); - if (mclk_idx < dpm_table->mem_table.count) { - *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; - *size = 4; - } else { - ret = -EINVAL; - } - break; - case AMDGPU_PP_SENSOR_GPU_LOAD: - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0, - &activity_percent); - *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_TEMP: - *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); - *size = 4; - break; - case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value); - *((uint32_t *)value) = *((uint32_t *)value) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - *size = 4; - break; - case AMDGPU_PP_SENSOR_MEM_TEMP: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value); - *((uint32_t *)value) = *((uint32_t *)value) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - *size = 4; - break; - case AMDGPU_PP_SENSOR_UVD_POWER: - *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; - *size = 4; - break; - case AMDGPU_PP_SENSOR_VCE_POWER: - *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_POWER: - ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value); - break; - case AMDGPU_PP_SENSOR_VDDGFX: - val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & - SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >> - SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT; - *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid); - return 0; - case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: - ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value); - if (!ret) - *size = 8; - break; - default: - ret = -EINVAL; - break; - } - - return ret; -} - -static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, - bool has_disp) -{ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetUclkFastSwitch, - has_disp ? 1 : 0, - NULL); -} - -static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, - struct pp_display_clock_request *clock_req) -{ - int result = 0; - enum amd_pp_clock_type clk_type = clock_req->clock_type; - uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; - DSPCLK_e clk_select = 0; - uint32_t clk_request = 0; - - switch (clk_type) { - case amd_pp_dcef_clock: - clk_select = DSPCLK_DCEFCLK; - break; - case amd_pp_disp_clock: - clk_select = DSPCLK_DISPCLK; - break; - case amd_pp_pixel_clock: - clk_select = DSPCLK_PIXCLK; - break; - case amd_pp_phy_clock: - clk_select = DSPCLK_PHYCLK; - break; - default: - pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); - result = -1; - break; - } - - if (!result) { - clk_request = (clk_freq << 16) | clk_select; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_RequestDisplayClockByFreq, - clk_request, - NULL); - } - - return result; -} - -static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, - uint32_t frequency) -{ - uint8_t count; - uint8_t i; - - if (mclk_table == NULL || mclk_table->count == 0) - return 0; - - count = (uint8_t)(mclk_table->count); - - for(i = 0; i < count; i++) { - if(mclk_table->entries[i].clk >= frequency) - return i; - } - - return i-1; -} - -static int vega10_notify_smc_display_config_after_ps_adjustment( - struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_single_dpm_table *dpm_table = - &data->dpm_table.dcef_table; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; - uint32_t idx; - struct PP_Clocks min_clocks = {0}; - uint32_t i; - struct pp_display_clock_request clock_req; - - if ((hwmgr->display_config->num_display > 1) && - !hwmgr->display_config->multi_monitor_in_sync && - !hwmgr->display_config->nb_pstate_switch_disable) - vega10_notify_smc_display_change(hwmgr, false); - else - vega10_notify_smc_display_change(hwmgr, true); - - min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; - min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; - min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; - - for (i = 0; i < dpm_table->count; i++) { - if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) - break; - } - - if (i < dpm_table->count) { - clock_req.clock_type = amd_pp_dcef_clock; - clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; - if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { - smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, - min_clocks.dcefClockInSR / 100, - NULL); - } else { - pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); - } - } else { - pr_debug("Cannot find requested DCEFCLK!"); - } - - if (min_clocks.memoryClock != 0) { - idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx, - NULL); - data->dpm_table.mem_table.dpm_state.soft_min_level= idx; - } - - return 0; -} - -static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - data->smc_state_table.gfx_boot_level = - data->smc_state_table.gfx_max_level = - vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); - data->smc_state_table.mem_boot_level = - data->smc_state_table.mem_max_level = - vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), - "Failed to upload boot level to highest!", - return -1); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), - "Failed to upload dpm max level to highest!", - return -1); - - return 0; -} - -static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - data->smc_state_table.gfx_boot_level = - data->smc_state_table.gfx_max_level = - vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); - data->smc_state_table.mem_boot_level = - data->smc_state_table.mem_max_level = - vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), - "Failed to upload boot level to highest!", - return -1); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), - "Failed to upload dpm max level to highest!", - return -1); - - return 0; - -} - -static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - data->smc_state_table.gfx_boot_level = - vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); - data->smc_state_table.gfx_max_level = - vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); - data->smc_state_table.mem_boot_level = - vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); - data->smc_state_table.mem_max_level = - vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), - "Failed to upload DPM Bootup Levels!", - return -1); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), - "Failed to upload DPM Max Levels!", - return -1); - return 0; -} - -static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, - uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - - if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && - table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL && - table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { - *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; - *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; - *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; - hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; - hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; - } - - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { - *sclk_mask = 0; - } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { - *mclk_mask = 0; - } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - /* under vega10 pp one vf mode, the gfx clk dpm need be lower - * to level-4 due to the limited power - */ - if (hwmgr->pp_one_vf) - *sclk_mask = 4; - else - *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; - *soc_mask = table_info->vdd_dep_on_socclk->count - 1; - *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; - } - - return 0; -} - -static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - if (!hwmgr->not_vf) - return; - - switch (mode) { - case AMD_FAN_CTRL_NONE: - vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100); - break; - case AMD_FAN_CTRL_MANUAL: - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega10_fan_ctrl_stop_smc_fan_control(hwmgr); - break; - case AMD_FAN_CTRL_AUTO: - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega10_fan_ctrl_start_smc_fan_control(hwmgr); - break; - default: - break; - } -} - -static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - switch (type) { - case PP_SCLK: - data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; - data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), - "Failed to upload boot level to lowest!", - return -EINVAL); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), - "Failed to upload dpm max level to highest!", - return -EINVAL); - break; - - case PP_MCLK: - data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; - data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), - "Failed to upload boot level to lowest!", - return -EINVAL); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), - "Failed to upload dpm max level to highest!", - return -EINVAL); - - break; - - case PP_SOCCLK: - data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; - data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), - "Failed to upload boot level to lowest!", - return -EINVAL); - - PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), - "Failed to upload dpm max level to highest!", - return -EINVAL); - - break; - - case PP_DCEFCLK: - pr_info("Setting DCEFCLK min/max dpm level is not supported!\n"); - break; - - case PP_PCIE: - default: - break; - } - - return 0; -} - -static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, - enum amd_dpm_forced_level level) -{ - int ret = 0; - uint32_t sclk_mask = 0; - uint32_t mclk_mask = 0; - uint32_t soc_mask = 0; - - if (hwmgr->pstate_sclk == 0) - vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); - - switch (level) { - case AMD_DPM_FORCED_LEVEL_HIGH: - ret = vega10_force_dpm_highest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_LOW: - ret = vega10_force_dpm_lowest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_AUTO: - ret = vega10_unforce_dpm_levels(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: - ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); - if (ret) - return ret; - vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); - vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); - break; - case AMD_DPM_FORCED_LEVEL_MANUAL: - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: - default: - break; - } - - if (!hwmgr->not_vf) - return ret; - - if (!ret) { - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); - else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); - } - - return ret; -} - -static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) - return AMD_FAN_CTRL_MANUAL; - else - return AMD_FAN_CTRL_AUTO; -} - -static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr, - struct amd_pp_simple_clock_info *info) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_clock_and_voltage_limits *max_limits = - &table_info->max_clock_voltage_on_ac; - - info->engine_max_clock = max_limits->sclk; - info->memory_max_clock = max_limits->mclk; - - return 0; -} - -static void vega10_get_sclks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = - table_info->vdd_dep_on_sclk; - uint32_t i; - - clocks->num_levels = 0; - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].clk) { - clocks->data[clocks->num_levels].clocks_in_khz = - dep_table->entries[i].clk * 10; - clocks->num_levels++; - } - } - -} - -static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = - table_info->vdd_dep_on_mclk; - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t j = 0; - uint32_t i; - - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].clk) { - - clocks->data[j].clocks_in_khz = - dep_table->entries[i].clk * 10; - data->mclk_latency_table.entries[j].frequency = - dep_table->entries[i].clk; - clocks->data[j].latency_in_us = - data->mclk_latency_table.entries[j].latency = 25; - j++; - } - } - clocks->num_levels = data->mclk_latency_table.count = j; -} - -static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = - table_info->vdd_dep_on_dcefclk; - uint32_t i; - - for (i = 0; i < dep_table->count; i++) { - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; - clocks->data[i].latency_in_us = 0; - clocks->num_levels++; - } -} - -static void vega10_get_socclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = - table_info->vdd_dep_on_socclk; - uint32_t i; - - for (i = 0; i < dep_table->count; i++) { - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; - clocks->data[i].latency_in_us = 0; - clocks->num_levels++; - } -} - -static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks) -{ - switch (type) { - case amd_pp_sys_clock: - vega10_get_sclks(hwmgr, clocks); - break; - case amd_pp_mem_clock: - vega10_get_memclocks(hwmgr, clocks); - break; - case amd_pp_dcef_clock: - vega10_get_dcefclocks(hwmgr, clocks); - break; - case amd_pp_soc_clock: - vega10_get_socclocks(hwmgr, clocks); - break; - default: - return -1; - } - - return 0; -} - -static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks) -{ - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; - uint32_t i; - - switch (type) { - case amd_pp_mem_clock: - dep_table = table_info->vdd_dep_on_mclk; - break; - case amd_pp_dcef_clock: - dep_table = table_info->vdd_dep_on_dcefclk; - break; - case amd_pp_disp_clock: - dep_table = table_info->vdd_dep_on_dispclk; - break; - case amd_pp_pixel_clock: - dep_table = table_info->vdd_dep_on_pixclk; - break; - case amd_pp_phy_clock: - dep_table = table_info->vdd_dep_on_phyclk; - break; - default: - return -1; - } - - for (i = 0; i < dep_table->count; i++) { - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; - clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table-> - entries[dep_table->entries[i].vddInd].us_vdd); - clocks->num_levels++; - } - - if (i < dep_table->count) - return -1; - - return 0; -} - -static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, - void *clock_range) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; - Watermarks_t *table = &(data->smc_state_table.water_marks_table); - - if (!data->registry_data.disable_water_mark) { - smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); - data->water_marks_bitmap = WaterMarksExist; - } - - return 0; -} - -static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) -{ - static const char *ppfeature_name[] = { - "DPM_PREFETCHER", - "GFXCLK_DPM", - "UCLK_DPM", - "SOCCLK_DPM", - "UVD_DPM", - "VCE_DPM", - "ULV", - "MP0CLK_DPM", - "LINK_DPM", - "DCEFCLK_DPM", - "AVFS", - "GFXCLK_DS", - "SOCCLK_DS", - "LCLK_DS", - "PPT", - "TDC", - "THERMAL", - "GFX_PER_CU_CG", - "RM", - "DCEFCLK_DS", - "ACDC", - "VR0HOT", - "VR1HOT", - "FW_CTF", - "LED_DISPLAY", - "FAN_CONTROL", - "FAST_PPT", - "DIDT", - "ACG", - "PCC_LIMIT"}; - static const char *output_title[] = { - "FEATURES", - "BITMASK", - "ENABLEMENT"}; - uint64_t features_enabled; - int i; - int ret = 0; - int size = 0; - - ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); - PP_ASSERT_WITH_CODE(!ret, - "[EnableAllSmuFeatures] Failed to get enabled smc features!", - return ret); - - size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); - size += sprintf(buf + size, "%-19s %-22s %s\n", - output_title[0], - output_title[1], - output_title[2]); - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", - ppfeature_name[i], - 1ULL << i, - (features_enabled & (1ULL << i)) ? "Y" : "N"); - } - - return size; -} - -static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) -{ - uint64_t features_enabled; - uint64_t features_to_enable; - uint64_t features_to_disable; - int ret = 0; - - if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) - return -EINVAL; - - ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); - if (ret) - return ret; - - features_to_disable = - features_enabled & ~new_ppfeature_masks; - features_to_enable = - ~features_enabled & new_ppfeature_masks; - - pr_debug("features_to_disable 0x%llx\n", features_to_disable); - pr_debug("features_to_enable 0x%llx\n", features_to_enable); - - if (features_to_disable) { - ret = vega10_enable_smc_features(hwmgr, false, features_to_disable); - if (ret) - return ret; - } - - if (features_to_enable) { - ret = vega10_enable_smc_features(hwmgr, true, features_to_enable); - if (ret) - return ret; - } - - return 0; -} - -static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); - struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); - struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); - struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); - struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); - struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; - - int i, now, size = 0, count = 0; - - switch (type) { - case PP_SCLK: - if (data->registry_data.sclk_dpm_key_disabled) - break; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); - - if (hwmgr->pp_one_vf && - (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) - count = 5; - else - count = sclk_table->count; - for (i = 0; i < count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, sclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_MCLK: - if (data->registry_data.mclk_dpm_key_disabled) - break; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); - - for (i = 0; i < mclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, mclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_SOCCLK: - if (data->registry_data.socclk_dpm_key_disabled) - break; - - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); - - for (i = 0; i < soc_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, soc_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_DCEFCLK: - if (data->registry_data.dcefclk_dpm_key_disabled) - break; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now); - - for (i = 0; i < dcef_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, dcef_table->dpm_levels[i].value / 100, - (dcef_table->dpm_levels[i].value / 100 == now) ? - "*" : ""); - break; - case PP_PCIE: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex, &now); - - for (i = 0; i < pcie_table->count; i++) - size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" : - (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" : - (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "", - (i == now) ? "*" : ""); - break; - case OD_SCLK: - if (hwmgr->od_enabled) { - size = sprintf(buf, "%s:\n", "OD_SCLK"); - podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; - for (i = 0; i < podn_vdd_dep->count; i++) - size += sprintf(buf + size, "%d: %10uMhz %10umV\n", - i, podn_vdd_dep->entries[i].clk / 100, - podn_vdd_dep->entries[i].vddc); - } - break; - case OD_MCLK: - if (hwmgr->od_enabled) { - size = sprintf(buf, "%s:\n", "OD_MCLK"); - podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; - for (i = 0; i < podn_vdd_dep->count; i++) - size += sprintf(buf + size, "%d: %10uMhz %10umV\n", - i, podn_vdd_dep->entries[i].clk/100, - podn_vdd_dep->entries[i].vddc); - } - break; - case OD_RANGE: - if (hwmgr->od_enabled) { - size = sprintf(buf, "%s:\n", "OD_RANGE"); - size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.engineClock/100); - size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.mem_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); - size += sprintf(buf + size, "VDDC: %7umV %11umV\n", - data->odn_dpm_table.min_vddc, - data->odn_dpm_table.max_vddc); - } - break; - default: - break; - } - return size; -} - -static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); - int result = 0; - - if ((data->water_marks_bitmap & WaterMarksExist) && - !(data->water_marks_bitmap & WaterMarksLoaded)) { - result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); - PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); - data->water_marks_bitmap |= WaterMarksLoaded; - } - - if (data->water_marks_bitmap & WaterMarksLoaded) { - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, - NULL); - } - - return result; -} - -static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_DPM_UVD].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - enable, - data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), - "Attempt to Enable/Disable DPM UVD Failed!", - return -1); - data->smu_features[GNLD_DPM_UVD].enabled = enable; - } - return 0; -} - -static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - data->vce_power_gated = bgate; - vega10_enable_disable_vce_dpm(hwmgr, !bgate); -} - -static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - data->uvd_power_gated = bgate; - vega10_enable_disable_uvd_dpm(hwmgr, !bgate); -} - -static inline bool vega10_are_power_levels_equal( - const struct vega10_performance_level *pl1, - const struct vega10_performance_level *pl2) -{ - return ((pl1->soc_clock == pl2->soc_clock) && - (pl1->gfx_clock == pl2->gfx_clock) && - (pl1->mem_clock == pl2->mem_clock)); -} - -static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, - const struct pp_hw_power_state *pstate1, - const struct pp_hw_power_state *pstate2, bool *equal) -{ - const struct vega10_power_state *psa; - const struct vega10_power_state *psb; - int i; - - if (pstate1 == NULL || pstate2 == NULL || equal == NULL) - return -EINVAL; - - psa = cast_const_phw_vega10_power_state(pstate1); - psb = cast_const_phw_vega10_power_state(pstate2); - /* If the two states don't even have the same number of performance levels they cannot be the same state. */ - if (psa->performance_level_count != psb->performance_level_count) { - *equal = false; - return 0; - } - - for (i = 0; i < psa->performance_level_count; i++) { - if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { - /* If we have found even one performance level pair that is different the states are different. */ - *equal = false; - return 0; - } - } - - /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ - *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); - *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); - *equal &= (psa->sclk_threshold == psb->sclk_threshold); - - return 0; -} - -static bool -vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - bool is_update_required = false; - - if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) - is_update_required = true; - - if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { - if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) - is_update_required = true; - } - - return is_update_required; -} - -static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - - if (!hwmgr->not_vf) - return 0; - - if (PP_CAP(PHM_PlatformCaps_ThermalController)) - vega10_disable_thermal_protection(hwmgr); - - tmp_result = vega10_disable_power_containment(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable power containment!", result = tmp_result); - - tmp_result = vega10_disable_didt_config(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable didt config!", result = tmp_result); - - tmp_result = vega10_avfs_enable(hwmgr, false); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable AVFS!", result = tmp_result); - - tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to stop DPM!", result = tmp_result); - - tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable deep sleep!", result = tmp_result); - - tmp_result = vega10_disable_ulv(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable ulv!", result = tmp_result); - - tmp_result = vega10_acg_disable(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable acg!", result = tmp_result); - - vega10_enable_disable_PCC_limit_feature(hwmgr, false); - return result; -} - -static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - int result; - - result = vega10_disable_dpm_tasks(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "[disable_dpm_tasks] Failed to disable DPM!", - ); - data->water_marks_bitmap &= ~(WaterMarksLoaded); - - return result; -} - -static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); - struct vega10_single_dpm_table *golden_sclk_table = - &(data->golden_dpm_table.gfx_table); - int value = sclk_table->dpm_levels[sclk_table->count - 1].value; - int golden_value = golden_sclk_table->dpm_levels - [golden_sclk_table->count - 1].value; - - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_single_dpm_table *golden_sclk_table = - &(data->golden_dpm_table.gfx_table); - struct pp_power_state *ps; - struct vega10_power_state *vega10_ps; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - vega10_ps = cast_phw_vega10_power_state(&ps->hardware); - - vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].gfx_clock = - golden_sclk_table->dpm_levels - [golden_sclk_table->count - 1].value * - value / 100 + - golden_sclk_table->dpm_levels - [golden_sclk_table->count - 1].value; - - if (vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].gfx_clock > - hwmgr->platform_descriptor.overdriveLimit.engineClock) { - vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].gfx_clock = - hwmgr->platform_descriptor.overdriveLimit.engineClock; - pr_warn("max sclk supported by vbios is %d\n", - hwmgr->platform_descriptor.overdriveLimit.engineClock); - } - return 0; -} - -static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); - struct vega10_single_dpm_table *golden_mclk_table = - &(data->golden_dpm_table.mem_table); - int value = mclk_table->dpm_levels[mclk_table->count - 1].value; - int golden_value = golden_mclk_table->dpm_levels - [golden_mclk_table->count - 1].value; - - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_single_dpm_table *golden_mclk_table = - &(data->golden_dpm_table.mem_table); - struct pp_power_state *ps; - struct vega10_power_state *vega10_ps; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - vega10_ps = cast_phw_vega10_power_state(&ps->hardware); - - vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].mem_clock = - golden_mclk_table->dpm_levels - [golden_mclk_table->count - 1].value * - value / 100 + - golden_mclk_table->dpm_levels - [golden_mclk_table->count - 1].value; - - if (vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].mem_clock > - hwmgr->platform_descriptor.overdriveLimit.memoryClock) { - vega10_ps->performance_levels - [vega10_ps->performance_level_count - 1].mem_clock = - hwmgr->platform_descriptor.overdriveLimit.memoryClock; - pr_warn("max mclk supported by vbios is %d\n", - hwmgr->platform_descriptor.overdriveLimit.memoryClock); - } - - return 0; -} - -static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, - uint32_t virtual_addr_low, - uint32_t virtual_addr_hi, - uint32_t mc_addr_low, - uint32_t mc_addr_hi, - uint32_t size) -{ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSystemVirtualDramAddrHigh, - virtual_addr_hi, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSystemVirtualDramAddrLow, - virtual_addr_low, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramAddrHigh, - mc_addr_hi, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramAddrLow, - mc_addr_low, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramSize, - size, - NULL); - return 0; -} - -static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *thermal_data) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - - memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); - - thermal_data->max = pp_table->TedgeLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->mem_crit_max = pp_table->ThbmLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return 0; -} - -static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t i, size = 0; - static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,}, - {70, 60, 1, 3,}, - {90, 60, 0, 0,}, - {70, 60, 0, 0,}, - {70, 90, 0, 0,}, - {30, 60, 0, 6,}, - }; - static const char *profile_name[7] = {"BOOTUP_DEFAULT", - "3D_FULL_SCREEN", - "POWER_SAVING", - "VIDEO", - "VR", - "COMPUTE", - "CUSTOM"}; - static const char *title[6] = {"NUM", - "MODE_NAME", - "BUSY_SET_POINT", - "FPS", - "USE_RLC_BUSY", - "MIN_ACTIVE_LEVEL"}; - - if (!buf) - return -EINVAL; - - size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0], - title[1], title[2], title[3], title[4], title[5]); - - for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++) - size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", - i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", - profile_mode_setting[i][0], profile_mode_setting[i][1], - profile_mode_setting[i][2], profile_mode_setting[i][3]); - size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", i, - profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", - data->custom_profile_mode[0], data->custom_profile_mode[1], - data->custom_profile_mode[2], data->custom_profile_mode[3]); - return size; -} - -static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint8_t busy_set_point; - uint8_t FPS; - uint8_t use_rlc_busy; - uint8_t min_active_level; - uint32_t power_profile_mode = input[size]; - - if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { - if (size != 0 && size != 4) - return -EINVAL; - - /* If size = 0 and the CUSTOM profile has been set already - * then just apply the profile. The copy stored in the hwmgr - * is zeroed out on init - */ - if (size == 0) { - if (data->custom_profile_mode[0] != 0) - goto out; - else - return -EINVAL; - } - - data->custom_profile_mode[0] = busy_set_point = input[0]; - data->custom_profile_mode[1] = FPS = input[1]; - data->custom_profile_mode[2] = use_rlc_busy = input[2]; - data->custom_profile_mode[3] = min_active_level = input[3]; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetCustomGfxDpmParameters, - busy_set_point | FPS<<8 | - use_rlc_busy << 16 | min_active_level<<24, - NULL); - } - -out: - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, - 1 << power_profile_mode, - NULL); - hwmgr->power_profile_mode = power_profile_mode; - - return 0; -} - - -static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, - enum PP_OD_DPM_TABLE_COMMAND type, - uint32_t clk, - uint32_t voltage) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); - struct vega10_single_dpm_table *golden_table; - - if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) { - pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc); - return false; - } - - if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { - golden_table = &(data->golden_dpm_table.gfx_table); - if (golden_table->dpm_levels[0].value > clk || - hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { - pr_info("OD engine clock is out of range [%d - %d] MHz\n", - golden_table->dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.engineClock/100); - return false; - } - } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { - golden_table = &(data->golden_dpm_table.mem_table); - if (golden_table->dpm_levels[0].value > clk || - hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { - pr_info("OD memory clock is out of range [%d - %d] MHz\n", - golden_table->dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); - return false; - } - } else { - return false; - } - - return true; -} - -static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct pp_power_state *ps = hwmgr->request_ps; - struct vega10_power_state *vega10_ps; - struct vega10_single_dpm_table *gfx_dpm_table = - &data->dpm_table.gfx_table; - struct vega10_single_dpm_table *soc_dpm_table = - &data->dpm_table.soc_table; - struct vega10_single_dpm_table *mem_dpm_table = - &data->dpm_table.mem_table; - int max_level; - - if (!ps) - return; - - vega10_ps = cast_phw_vega10_power_state(&ps->hardware); - max_level = vega10_ps->performance_level_count - 1; - - if (vega10_ps->performance_levels[max_level].gfx_clock != - gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) - vega10_ps->performance_levels[max_level].gfx_clock = - gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; - - if (vega10_ps->performance_levels[max_level].soc_clock != - soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) - vega10_ps->performance_levels[max_level].soc_clock = - soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; - - if (vega10_ps->performance_levels[max_level].mem_clock != - mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) - vega10_ps->performance_levels[max_level].mem_clock = - mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; - - if (!hwmgr->ps) - return; - - ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1)); - vega10_ps = cast_phw_vega10_power_state(&ps->hardware); - max_level = vega10_ps->performance_level_count - 1; - - if (vega10_ps->performance_levels[max_level].gfx_clock != - gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) - vega10_ps->performance_levels[max_level].gfx_clock = - gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; - - if (vega10_ps->performance_levels[max_level].soc_clock != - soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) - vega10_ps->performance_levels[max_level].soc_clock = - soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; - - if (vega10_ps->performance_levels[max_level].mem_clock != - mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) - vega10_ps->performance_levels[max_level].mem_clock = - mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; -} - -static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr, - enum PP_OD_DPM_TABLE_COMMAND type) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk; - struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; - - struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk = - &data->odn_dpm_table.vdd_dep_on_socclk; - struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table; - - struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep; - uint8_t i, j; - - if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { - podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; - for (i = 0; i < podn_vdd_dep->count; i++) - od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc; - } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { - podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; - for (i = 0; i < dpm_table->count; i++) { - for (j = 0; j < od_vddc_lookup_table->count; j++) { - if (od_vddc_lookup_table->entries[j].us_vdd > - podn_vdd_dep->entries[i].vddc) - break; - } - if (j == od_vddc_lookup_table->count) { - j = od_vddc_lookup_table->count - 1; - od_vddc_lookup_table->entries[j].us_vdd = - podn_vdd_dep->entries[i].vddc; - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; - } - podn_vdd_dep->entries[i].vddInd = j; - } - dpm_table = &data->dpm_table.soc_table; - for (i = 0; i < dep_table->count; i++) { - if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd && - dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) { - data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; - for (; (i < dep_table->count) && - (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) { - podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk; - dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk; - } - break; - } else { - dpm_table->dpm_levels[i].value = dep_table->entries[i].clk; - podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc; - podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd; - podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk; - } - } - if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk < - podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) { - data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; - podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = - podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; - dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = - podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; - } - if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd < - podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) { - data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; - podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = - podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd; - } - } - vega10_odn_update_power_state(hwmgr); -} - -static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, - enum PP_OD_DPM_TABLE_COMMAND type, - long *input, uint32_t size) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table; - struct vega10_single_dpm_table *dpm_table; - - uint32_t input_clk; - uint32_t input_vol; - uint32_t input_level; - uint32_t i; - - PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", - return -EINVAL); - - if (!hwmgr->od_enabled) { - pr_info("OverDrive feature not enabled\n"); - return -EINVAL; - } - - if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { - dpm_table = &data->dpm_table.gfx_table; - podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk; - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; - } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { - dpm_table = &data->dpm_table.mem_table; - podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk; - data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; - } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { - memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table)); - vega10_odn_initial_default_setting(hwmgr); - vega10_odn_update_power_state(hwmgr); - /* force to update all clock tables */ - data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK | - DPMTABLE_UPDATE_MCLK | - DPMTABLE_UPDATE_SOCCLK; - return 0; - } else if (PP_OD_COMMIT_DPM_TABLE == type) { - vega10_check_dpm_table_updated(hwmgr); - return 0; - } else { - return -EINVAL; - } - - for (i = 0; i < size; i += 3) { - if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) { - pr_info("invalid clock voltage input\n"); - return 0; - } - input_level = input[i]; - input_clk = input[i+1] * 100; - input_vol = input[i+2]; - - if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { - dpm_table->dpm_levels[input_level].value = input_clk; - podn_vdd_dep_table->entries[input_level].clk = input_clk; - podn_vdd_dep_table->entries[input_level].vddc = input_vol; - } else { - return -EINVAL; - } - } - vega10_odn_update_soc_table(hwmgr, type); - return 0; -} - -static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr, - enum pp_mp1_state mp1_state) -{ - uint16_t msg; - int ret; - - switch (mp1_state) { - case PP_MP1_STATE_UNLOAD: - msg = PPSMC_MSG_PrepareMp1ForUnload; - break; - case PP_MP1_STATE_SHUTDOWN: - case PP_MP1_STATE_RESET: - case PP_MP1_STATE_NONE: - default: - return 0; - } - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, - "[PrepareMp1] Failed!", - return ret); - - return 0; -} - -static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, - PHM_PerformanceLevelDesignation designation, uint32_t index, - PHM_PerformanceLevel *level) -{ - const struct vega10_power_state *ps; - uint32_t i; - - if (level == NULL || hwmgr == NULL || state == NULL) - return -EINVAL; - - ps = cast_const_phw_vega10_power_state(state); - - i = index > ps->performance_level_count - 1 ? - ps->performance_level_count - 1 : index; - - level->coreClock = ps->performance_levels[i].gfx_clock; - level->memory_clock = ps->performance_levels[i].mem_clock; - - return 0; -} - -static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable) -{ - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t feature_mask = 0; - - if (disable) { - feature_mask |= data->smu_features[GNLD_ULV].enabled ? - data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; - feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ? - data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; - feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ? - data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; - feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ? - data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; - feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ? - data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; - } else { - feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ? - data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; - feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ? - data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; - feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ? - data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; - feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ? - data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; - feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ? - data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; - } - - if (feature_mask) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - !disable, feature_mask), - "enable/disable power features for compute performance Failed!", - return -EINVAL); - - if (disable) { - data->smu_features[GNLD_ULV].enabled = false; - data->smu_features[GNLD_DS_GFXCLK].enabled = false; - data->smu_features[GNLD_DS_SOCCLK].enabled = false; - data->smu_features[GNLD_DS_LCLK].enabled = false; - data->smu_features[GNLD_DS_DCEFCLK].enabled = false; - } else { - data->smu_features[GNLD_ULV].enabled = true; - data->smu_features[GNLD_DS_GFXCLK].enabled = true; - data->smu_features[GNLD_DS_SOCCLK].enabled = true; - data->smu_features[GNLD_DS_LCLK].enabled = true; - data->smu_features[GNLD_DS_DCEFCLK].enabled = true; - } - - return 0; - -} - -static const struct pp_hwmgr_func vega10_hwmgr_funcs = { - .backend_init = vega10_hwmgr_backend_init, - .backend_fini = vega10_hwmgr_backend_fini, - .asic_setup = vega10_setup_asic_task, - .dynamic_state_management_enable = vega10_enable_dpm_tasks, - .dynamic_state_management_disable = vega10_disable_dpm_tasks, - .get_num_of_pp_table_entries = - vega10_get_number_of_powerplay_table_entries, - .get_power_state_size = vega10_get_power_state_size, - .get_pp_table_entry = vega10_get_pp_table_entry, - .patch_boot_state = vega10_patch_boot_state, - .apply_state_adjust_rules = vega10_apply_state_adjust_rules, - .power_state_set = vega10_set_power_state_tasks, - .get_sclk = vega10_dpm_get_sclk, - .get_mclk = vega10_dpm_get_mclk, - .notify_smc_display_config_after_ps_adjustment = - vega10_notify_smc_display_config_after_ps_adjustment, - .force_dpm_level = vega10_dpm_force_dpm_level, - .stop_thermal_controller = vega10_thermal_stop_thermal_controller, - .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info, - .get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent, - .set_fan_speed_percent = vega10_fan_ctrl_set_fan_speed_percent, - .reset_fan_speed_to_default = - vega10_fan_ctrl_reset_fan_speed_to_default, - .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm, - .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm, - .uninitialize_thermal_controller = - vega10_thermal_ctrl_uninitialize_thermal_controller, - .set_fan_control_mode = vega10_set_fan_control_mode, - .get_fan_control_mode = vega10_get_fan_control_mode, - .read_sensor = vega10_read_sensor, - .get_dal_power_level = vega10_get_dal_power_level, - .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency, - .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage, - .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges, - .display_clock_voltage_request = vega10_display_clock_voltage_request, - .force_clock_level = vega10_force_clock_level, - .print_clock_levels = vega10_print_clock_levels, - .display_config_changed = vega10_display_configuration_changed_task, - .powergate_uvd = vega10_power_gate_uvd, - .powergate_vce = vega10_power_gate_vce, - .check_states_equal = vega10_check_states_equal, - .check_smc_update_required_for_display_configuration = - vega10_check_smc_update_required_for_display_configuration, - .power_off_asic = vega10_power_off_asic, - .disable_smc_firmware_ctf = vega10_thermal_disable_alert, - .get_sclk_od = vega10_get_sclk_od, - .set_sclk_od = vega10_set_sclk_od, - .get_mclk_od = vega10_get_mclk_od, - .set_mclk_od = vega10_set_mclk_od, - .avfs_control = vega10_avfs_enable, - .notify_cac_buffer_info = vega10_notify_cac_buffer_info, - .get_thermal_temperature_range = vega10_get_thermal_temperature_range, - .register_irq_handlers = smu9_register_irq_handlers, - .start_thermal_controller = vega10_start_thermal_controller, - .get_power_profile_mode = vega10_get_power_profile_mode, - .set_power_profile_mode = vega10_set_power_profile_mode, - .set_power_limit = vega10_set_power_limit, - .odn_edit_dpm_table = vega10_odn_edit_dpm_table, - .get_performance_level = vega10_get_performance_level, - .get_asic_baco_capability = smu9_baco_get_capability, - .get_asic_baco_state = smu9_baco_get_state, - .set_asic_baco_state = vega10_baco_set_state, - .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost, - .get_ppfeature_status = vega10_get_ppfeature_status, - .set_ppfeature_status = vega10_set_ppfeature_status, - .set_mp1_state = vega10_set_mp1_state, - .disable_power_features_for_compute_performance = - vega10_disable_power_features_for_compute_performance, -}; - -int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - hwmgr->hwmgr_func = &vega10_hwmgr_funcs; - hwmgr->pptable_func = &vega10_pptable_funcs; - if (amdgpu_passthrough(adev)) - return vega10_baco_set_cap(hwmgr); - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h deleted file mode 100644 index f752b4ad0c8a..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _VEGA10_HWMGR_H_ -#define _VEGA10_HWMGR_H_ - -#include "hwmgr.h" -#include "smu9_driver_if.h" -#include "ppatomctrl.h" -#include "ppatomfwctrl.h" -#include "vega10_ppsmc.h" -#include "vega10_powertune.h" - -#define VEGA10_MAX_HARDWARE_POWERLEVELS 2 - -#define WaterMarksExist 1 -#define WaterMarksLoaded 2 - -enum { - GNLD_DPM_PREFETCHER = 0, - GNLD_DPM_GFXCLK, - GNLD_DPM_UCLK, - GNLD_DPM_SOCCLK, - GNLD_DPM_UVD, - GNLD_DPM_VCE, - GNLD_ULV, - GNLD_DPM_MP0CLK, - GNLD_DPM_LINK, - GNLD_DPM_DCEFCLK, - GNLD_AVFS, - GNLD_DS_GFXCLK, - GNLD_DS_SOCCLK, - GNLD_DS_LCLK, - GNLD_PPT, - GNLD_TDC, - GNLD_THERMAL, - GNLD_GFX_PER_CU_CG, - GNLD_RM, - GNLD_DS_DCEFCLK, - GNLD_ACDC, - GNLD_VR0HOT, - GNLD_VR1HOT, - GNLD_FW_CTF, - GNLD_LED_DISPLAY, - GNLD_FAN_CONTROL, - GNLD_FEATURE_FAST_PPT_BIT, - GNLD_DIDT, - GNLD_ACG, - GNLD_PCC_LIMIT, - GNLD_FEATURES_MAX -}; - -#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) - -#define SMC_DPM_FEATURES 0x30F - -struct smu_features { - bool supported; - bool enabled; - uint32_t smu_feature_id; - uint32_t smu_feature_bitmap; -}; - -struct vega10_performance_level { - uint32_t soc_clock; - uint32_t gfx_clock; - uint32_t mem_clock; -}; - -struct vega10_bacos { - uint32_t baco_flags; - /* struct vega10_performance_level performance_level; */ -}; - -struct vega10_uvd_clocks { - uint32_t vclk; - uint32_t dclk; -}; - -struct vega10_vce_clocks { - uint32_t evclk; - uint32_t ecclk; -}; - -struct vega10_power_state { - uint32_t magic; - struct vega10_uvd_clocks uvd_clks; - struct vega10_vce_clocks vce_clks; - uint16_t performance_level_count; - bool dc_compatible; - uint32_t sclk_threshold; - struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS]; -}; - -struct vega10_dpm_level { - bool enabled; - uint32_t value; - uint32_t param1; -}; - -#define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5 -#define MAX_REGULAR_DPM_NUMBER 8 -#define MAX_PCIE_CONF 2 -#define VEGA10_MINIMUM_ENGINE_CLOCK 2500 - -struct vega10_dpm_state { - uint32_t soft_min_level; - uint32_t soft_max_level; - uint32_t hard_min_level; - uint32_t hard_max_level; -}; - -struct vega10_single_dpm_table { - uint32_t count; - struct vega10_dpm_state dpm_state; - struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega10_pcie_table { - uint16_t count; - uint8_t pcie_gen[MAX_PCIE_CONF]; - uint8_t pcie_lane[MAX_PCIE_CONF]; - uint32_t lclk[MAX_PCIE_CONF]; -}; - -struct vega10_dpm_table { - struct vega10_single_dpm_table soc_table; - struct vega10_single_dpm_table gfx_table; - struct vega10_single_dpm_table mem_table; - struct vega10_single_dpm_table eclk_table; - struct vega10_single_dpm_table vclk_table; - struct vega10_single_dpm_table dclk_table; - struct vega10_single_dpm_table dcef_table; - struct vega10_single_dpm_table pixel_table; - struct vega10_single_dpm_table display_table; - struct vega10_single_dpm_table phy_table; - struct vega10_pcie_table pcie_table; -}; - -#define VEGA10_MAX_LEAKAGE_COUNT 8 -struct vega10_leakage_voltage { - uint16_t count; - uint16_t leakage_id[VEGA10_MAX_LEAKAGE_COUNT]; - uint16_t actual_voltage[VEGA10_MAX_LEAKAGE_COUNT]; -}; - -struct vega10_display_timing { - uint32_t min_clock_in_sr; - uint32_t num_existing_displays; -}; - -struct vega10_dpmlevel_enable_mask { - uint32_t uvd_dpm_enable_mask; - uint32_t vce_dpm_enable_mask; - uint32_t acp_dpm_enable_mask; - uint32_t samu_dpm_enable_mask; - uint32_t sclk_dpm_enable_mask; - uint32_t mclk_dpm_enable_mask; -}; - -struct vega10_vbios_boot_state { - bool bsoc_vddc_lock; - uint16_t vddc; - uint16_t vddci; - uint16_t mvddc; - uint16_t vdd_gfx; - uint32_t gfx_clock; - uint32_t mem_clock; - uint32_t soc_clock; - uint32_t dcef_clock; -}; - -struct vega10_smc_state_table { - uint32_t soc_boot_level; - uint32_t gfx_boot_level; - uint32_t dcef_boot_level; - uint32_t mem_boot_level; - uint32_t uvd_boot_level; - uint32_t vce_boot_level; - uint32_t gfx_max_level; - uint32_t mem_max_level; - uint32_t soc_max_level; - uint8_t vr_hot_gpio; - uint8_t ac_dc_gpio; - uint8_t therm_out_gpio; - uint8_t therm_out_polarity; - uint8_t therm_out_mode; - PPTable_t pp_table; - Watermarks_t water_marks_table; - AvfsTable_t avfs_table; - AvfsFuseOverride_t avfs_fuse_override_table; -}; - -struct vega10_mclk_latency_entries { - uint32_t frequency; - uint32_t latency; -}; - -struct vega10_mclk_latency_table { - uint32_t count; - struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega10_registry_data { - uint8_t ac_dc_switch_gpio_support; - uint8_t avfs_support; - uint8_t cac_support; - uint8_t clock_stretcher_support; - uint8_t db_ramping_support; - uint8_t didt_mode; - uint8_t didt_support; - uint8_t edc_didt_support; - uint8_t dynamic_state_patching_support; - uint8_t enable_pkg_pwr_tracking_feature; - uint8_t enable_tdc_limit_feature; - uint32_t fast_watermark_threshold; - uint8_t force_dpm_high; - uint8_t fuzzy_fan_control_support; - uint8_t long_idle_baco_support; - uint8_t mclk_dpm_key_disabled; - uint8_t od_state_in_dc_support; - uint8_t pcieLaneOverride; - uint8_t pcieSpeedOverride; - uint32_t pcieClockOverride; - uint8_t pcie_dpm_key_disabled; - uint8_t dcefclk_dpm_key_disabled; - uint8_t power_containment_support; - uint8_t ppt_support; - uint8_t prefetcher_dpm_key_disabled; - uint8_t quick_transition_support; - uint8_t regulator_hot_gpio_support; - uint8_t sclk_deep_sleep_support; - uint8_t sclk_dpm_key_disabled; - uint8_t sclk_from_vbios; - uint8_t sclk_throttle_low_notification; - uint8_t show_baco_dbg_info; - uint8_t skip_baco_hardware; - uint8_t socclk_dpm_key_disabled; - uint8_t spll_shutdown_support; - uint8_t sq_ramping_support; - uint32_t stable_pstate_sclk_dpm_percentage; - uint8_t tcp_ramping_support; - uint8_t tdc_support; - uint8_t td_ramping_support; - uint8_t dbr_ramping_support; - uint8_t gc_didt_support; - uint8_t psm_didt_support; - uint8_t thermal_out_gpio_support; - uint8_t thermal_support; - uint8_t fw_ctf_enabled; - uint8_t fan_control_support; - uint8_t ulps_support; - uint8_t ulv_support; - uint32_t vddc_vddci_delta; - uint8_t odn_feature_enable; - uint8_t disable_water_mark; - uint8_t zrpm_stop_temp; - uint8_t zrpm_start_temp; - uint8_t led_dpm_enabled; - uint8_t vr0hot_enabled; - uint8_t vr1hot_enabled; -}; - -struct vega10_odn_clock_voltage_dependency_table { - uint32_t count; - struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega10_odn_vddc_lookup_table { - uint32_t count; - struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega10_odn_dpm_table { - struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_sclk; - struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_mclk; - struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_socclk; - struct vega10_odn_vddc_lookup_table vddc_lookup_table; - uint32_t max_vddc; - uint32_t min_vddc; -}; - -struct vega10_odn_fan_table { - uint32_t target_fan_speed; - uint32_t target_temperature; - uint32_t min_performance_clock; - uint32_t min_fan_limit; -}; - -struct vega10_hwmgr { - struct vega10_dpm_table dpm_table; - struct vega10_dpm_table golden_dpm_table; - struct vega10_registry_data registry_data; - struct vega10_vbios_boot_state vbios_boot_state; - struct vega10_mclk_latency_table mclk_latency_table; - - struct vega10_leakage_voltage vddc_leakage; - - uint32_t vddc_control; - struct pp_atomfwctrl_voltage_table vddc_voltage_table; - uint32_t mvdd_control; - struct pp_atomfwctrl_voltage_table mvdd_voltage_table; - uint32_t vddci_control; - struct pp_atomfwctrl_voltage_table vddci_voltage_table; - - uint32_t active_auto_throttle_sources; - uint32_t water_marks_bitmap; - struct vega10_bacos bacos; - - struct vega10_odn_dpm_table odn_dpm_table; - struct vega10_odn_fan_table odn_fan_table; - - /* ---- General data ---- */ - uint8_t need_update_dpm_table; - - bool cac_enabled; - bool battery_state; - bool is_tlu_enabled; - - uint32_t low_sclk_interrupt_threshold; - - uint32_t total_active_cus; - - struct vega10_display_timing display_timing; - - /* ---- Vega10 Dyn Register Settings ---- */ - - uint32_t debug_settings; - uint32_t lowest_uclk_reserved_for_ulv; - uint32_t gfxclk_average_alpha; - uint32_t socclk_average_alpha; - uint32_t uclk_average_alpha; - uint32_t gfx_activity_average_alpha; - uint32_t display_voltage_mode; - uint32_t dcef_clk_quad_eqn_a; - uint32_t dcef_clk_quad_eqn_b; - uint32_t dcef_clk_quad_eqn_c; - uint32_t disp_clk_quad_eqn_a; - uint32_t disp_clk_quad_eqn_b; - uint32_t disp_clk_quad_eqn_c; - uint32_t pixel_clk_quad_eqn_a; - uint32_t pixel_clk_quad_eqn_b; - uint32_t pixel_clk_quad_eqn_c; - uint32_t phy_clk_quad_eqn_a; - uint32_t phy_clk_quad_eqn_b; - uint32_t phy_clk_quad_eqn_c; - - /* ---- Thermal Temperature Setting ---- */ - struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; - - /* ---- Power Gating States ---- */ - bool uvd_power_gated; - bool vce_power_gated; - bool need_long_memory_training; - - /* Internal settings to apply the application power optimization parameters */ - uint32_t disable_dpm_mask; - - /* ---- SMU9 ---- */ - struct smu_features smu_features[GNLD_FEATURES_MAX]; - struct vega10_smc_state_table smc_state_table; - - uint32_t config_telemetry; - uint32_t acg_loop_state; - uint32_t mem_channels; - uint8_t custom_profile_mode[4]; -}; - -#define VEGA10_DPM2_NEAR_TDP_DEC 10 -#define VEGA10_DPM2_ABOVE_SAFE_INC 5 -#define VEGA10_DPM2_BELOW_SAFE_INC 20 - -#define VEGA10_DPM2_LTA_WINDOW_SIZE 7 - -#define VEGA10_DPM2_LTS_TRUNCATE 0 - -#define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT 80 - -#define VEGA10_DPM2_MAXPS_PERCENT_M 90 -#define VEGA10_DPM2_MAXPS_PERCENT_H 90 - -#define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN 50 - -#define VEGA10_DPM2_SQ_RAMP_MAX_POWER 0x3FFF -#define VEGA10_DPM2_SQ_RAMP_MIN_POWER 0x12 -#define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 -#define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E -#define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF - -#define VEGA10_VOLTAGE_CONTROL_NONE 0x0 -#define VEGA10_VOLTAGE_CONTROL_BY_GPIO 0x1 -#define VEGA10_VOLTAGE_CONTROL_BY_SVID2 0x2 -#define VEGA10_VOLTAGE_CONTROL_MERGED 0x3 -/* To convert to Q8.8 format for firmware */ -#define VEGA10_Q88_FORMAT_CONVERSION_UNIT 256 - -#define VEGA10_UNUSED_GPIO_PIN 0x7F - -#define VEGA10_THERM_OUT_MODE_DISABLE 0x0 -#define VEGA10_THERM_OUT_MODE_THERM_ONLY 0x1 -#define VEGA10_THERM_OUT_MODE_THERM_VRHOT 0x2 - -#define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT 0xffffffff -#define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT 0xffffffff - -#define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ - -#define VEGA10_UMD_PSTATE_GFXCLK_LEVEL 0x3 -#define VEGA10_UMD_PSTATE_SOCCLK_LEVEL 0x3 -#define VEGA10_UMD_PSTATE_MCLK_LEVEL 0x2 - -extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); -extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); -extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr); -extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); -extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display); -int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input); -int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); -int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); -int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate); -int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); - -#endif /* _VEGA10_HWMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h deleted file mode 100644 index faf7ac044348..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA10_INC_H -#define VEGA10_INC_H - -#include "asic_reg/thm/thm_9_0_default.h" -#include "asic_reg/thm/thm_9_0_offset.h" -#include "asic_reg/thm/thm_9_0_sh_mask.h" - -#include "asic_reg/mp/mp_9_0_offset.h" -#include "asic_reg/mp/mp_9_0_sh_mask.h" - -#include "asic_reg/gc/gc_9_0_default.h" -#include "asic_reg/gc/gc_9_0_offset.h" -#include "asic_reg/gc/gc_9_0_sh_mask.h" - -#include "asic_reg/nbio/nbio_6_1_default.h" -#include "asic_reg/nbio/nbio_6_1_offset.h" -#include "asic_reg/nbio/nbio_6_1_sh_mask.h" - - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c deleted file mode 100644 index 9757d47dd6b8..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +++ /dev/null @@ -1,1392 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "hwmgr.h" -#include "vega10_hwmgr.h" -#include "vega10_smumgr.h" -#include "vega10_powertune.h" -#include "vega10_ppsmc.h" -#include "vega10_inc.h" -#include "pp_debug.h" -#include "soc15_common.h" - -static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ */ - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 }, - { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 }, - - /* DIDT_TD */ - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde }, - { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde }, - - /* DIDT_TCP */ - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, - { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, - - /* DIDT_DB */ - { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, - { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /*DIDT_SQ_CTRL3 */ - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, - - /*DIDT_TCP_CTRL3 */ - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, - - /*DIDT_TD_CTRL3 */ - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, - - /*DIDT_DB_CTRL3 */ - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ */ - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, - { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 }, - - /* DIDT_TD */ - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, - { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, - - /* DIDT_TCP */ - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, - { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, - - /* DIDT_DB */ - { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, - { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, - { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ */ - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff }, - /* DIDT_TD */ - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff }, - /* DIDT_TCP */ - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff }, - /* DIDT_DB */ - { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MIN_POWER_MASK, DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MAX_POWER_MASK, DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff }, - - { 0xFFFFFFFF } /* End of list */ -}; - - -static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ */ - { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B363B1A }, - { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, 0x270B2432 }, - { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000018 }, - - /* DIDT_TD */ - { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B1D220F }, - { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00007558 }, - { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 }, - - /* DIDT_TCP */ - { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, 0, 0x5ACE160D }, - { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 }, - - /* DIDT_DB */ - { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, 0x0E152A0F }, - { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, 0x09061813 }, - { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000013 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ */ - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, - /* DIDT_TD */ - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, - /* DIDT_TCP */ - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, - { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, - /* DIDT_DB */ - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, - { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - - -static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ */ - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, - { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, - - /* DIDT_TD */ - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, - { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, - - /* DIDT_TCP */ - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, - - /* DIDT_DB */ - { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, - { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, - { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, - { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* DIDT_SQ_STALL_PATTERN_1_2 */ - { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, - { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, - - /* DIDT_SQ_STALL_PATTERN_3_4 */ - { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, - { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, - - /* DIDT_SQ_STALL_PATTERN_5_6 */ - { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, - { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, - - /* DIDT_SQ_STALL_PATTERN_7 */ - { ixDIDT_SQ_STALL_PATTERN_7, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, - - /* DIDT_TCP_STALL_PATTERN_1_2 */ - { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, - { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, - - /* DIDT_TCP_STALL_PATTERN_3_4 */ - { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, - { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, - - /* DIDT_TCP_STALL_PATTERN_5_6 */ - { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, - { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, - - /* DIDT_TCP_STALL_PATTERN_7 */ - { ixDIDT_TCP_STALL_PATTERN_7, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, - - /* DIDT_TD_STALL_PATTERN_1_2 */ - { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, - { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, - - /* DIDT_TD_STALL_PATTERN_3_4 */ - { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, - { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, - - /* DIDT_TD_STALL_PATTERN_5_6 */ - { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, - { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, - - /* DIDT_TD_STALL_PATTERN_7 */ - { ixDIDT_TD_STALL_PATTERN_7, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, - - /* DIDT_DB_STALL_PATTERN_1_2 */ - { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, - { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, - - /* DIDT_DB_STALL_PATTERN_3_4 */ - { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, - { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, - - /* DIDT_DB_STALL_PATTERN_5_6 */ - { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, - { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, - - /* DIDT_DB_STALL_PATTERN_7 */ - { ixDIDT_DB_STALL_PATTERN_7, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ */ - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860021 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060021 }, - /* TD */ - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x028E0020 }, - /* TCP */ - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x001c0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x009c0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x011c0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x019c0020 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x021c0020 }, - /* DB */ - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00200008 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00820008 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01020008 }, - { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01820008 }, - - { 0xFFFFFFFF } /* End of list */ -}; - - -static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ */ - { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x000F0007 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x003F001F }, - { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x0000007F }, - /* TD */ - { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, - /* TCP */ - { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, - /* DB */ - { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ */ - { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, - /* TD */ - { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 }, - { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ */ - { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, - /* TD */ - { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, - /* TCP */ - { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, - { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, - /* DB */ - { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0x0000010E }, - { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, - { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, - { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ */ - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ */ - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ */ - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, - - /* TD */ - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 }, - { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 }, - { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 }, - { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 }, - { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, - { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, - { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 }, - { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { 0xFFFFFFFF } /* End of list */ -}; - - -static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ EDC STALL PATTERNs */ - { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, 0x1111 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, 0x1111 }, - - { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, 0x1515 }, - { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, 0x1515 }, - - { ixDIDT_SQ_EDC_STALL_PATTERN_7, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, 0x5555 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ EDC STALL DELAYs */ - { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 }, - - { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 }, - - { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 }, - - { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ EDC CTRL */ - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - /* SQ EDC CTRL */ - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 }, - { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 }, - { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 }, - { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 }, - { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, - { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[]= -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { 0x16A02, 0xFFFFFFFF, 0x0, 0x0000005F }, - { 0x16A05, 0xFFFFFFFF, 0x0, 0x00000001 }, - { 0x16A06, 0x00000001, 0x0, 0x02000000 }, - { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = -{ -/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - * Offset Mask Shift Value - * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ - { 0x16A05, 0xFFFFFFFF, 0x18, 0x00000001 }, - { 0x16A05, 0xFFFFFFFF, 0x8, 0x00000003 }, - { 0x16A05, 0xFFFFFFFF, 0xa, 0x00000006 }, - { 0x16A05, 0xFFFFFFFF, 0x7, 0x00000000 }, - { 0x16A06, 0xFFFFFFFF, 0x18, 0x00000001 }, - { 0x16A06, 0xFFFFFFFF, 0x19, 0x00000001 }, - { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 }, - - { 0xFFFFFFFF } /* End of list */ -}; - -static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type) -{ - uint32_t data; - - PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL); - - while (config_regs->offset != 0xFFFFFFFF) { - switch (reg_type) { - case VEGA10_CONFIGREG_DIDT: - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); - data &= ~config_regs->mask; - data |= ((config_regs->value << config_regs->shift) & config_regs->mask); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); - break; - case VEGA10_CONFIGREG_GCCAC: - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); - data &= ~config_regs->mask; - data |= ((config_regs->value << config_regs->shift) & config_regs->mask); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); - break; - case VEGA10_CONFIGREG_SECAC: - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset); - data &= ~config_regs->mask; - data |= ((config_regs->value << config_regs->shift) & config_regs->mask); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data); - break; - default: - return -EINVAL; - } - - config_regs++; - } - - return 0; -} - -static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs) -{ - uint32_t data; - - while (config_regs->offset != 0xFFFFFFFF) { - data = cgs_read_register(hwmgr->device, config_regs->offset); - data &= ~config_regs->mask; - data |= ((config_regs->value << config_regs->shift) & config_regs->mask); - cgs_write_register(hwmgr->device, config_regs->offset, data); - config_regs++; - } - - return 0; -} - -static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) -{ - uint32_t data; - uint32_t en = (enable ? 1 : 0); - uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; - - if (PP_CAP(PHM_PlatformCaps_SQRamping)) { - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_SQ_CTRL0, DIDT_CTRL_EN, en); - didt_block_info &= ~SQ_Enable_MASK; - didt_block_info |= en << SQ_Enable_SHIFT; - } - - if (PP_CAP(PHM_PlatformCaps_DBRamping)) { - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_DB_CTRL0, DIDT_CTRL_EN, en); - didt_block_info &= ~DB_Enable_MASK; - didt_block_info |= en << DB_Enable_SHIFT; - } - - if (PP_CAP(PHM_PlatformCaps_TDRamping)) { - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_TD_CTRL0, DIDT_CTRL_EN, en); - didt_block_info &= ~TD_Enable_MASK; - didt_block_info |= en << TD_Enable_SHIFT; - } - - if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_TCP_CTRL0, DIDT_CTRL_EN, en); - didt_block_info &= ~TCP_Enable_MASK; - didt_block_info |= en << TCP_Enable_SHIFT; - } - - if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { - CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, - DIDT_DBR_CTRL0, DIDT_CTRL_EN, en); - } - - if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) { - if (PP_CAP(PHM_PlatformCaps_SQRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); - data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en); - data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data); - } - - if (PP_CAP(PHM_PlatformCaps_DBRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); - data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en); - data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data); - } - - if (PP_CAP(PHM_PlatformCaps_TDRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); - data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en); - data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data); - } - - if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); - data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en); - data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data); - } - - if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); - data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en); - data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data); - } - } - - /* For Vega10, SMC does not support any mask yet. */ - if (enable) - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info, - NULL); - -} - -static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int result; - uint32_t num_se = 0, count, data; - - num_se = adev->gfx.config.max_shader_engines; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - mutex_lock(&adev->grbm_idx_mutex); - for (count = 0; count < num_se; count++) { - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); - - result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); - - if (0 != result) - break; - } - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); - mutex_unlock(&adev->grbm_idx_mutex); - - vega10_didt_set_mask(hwmgr, true); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - return 0; -} - -static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - vega10_didt_set_mask(hwmgr, false); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - return 0; -} - -static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int result; - uint32_t num_se = 0, count, data; - - num_se = adev->gfx.config.max_shader_engines; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - mutex_lock(&adev->grbm_idx_mutex); - for (count = 0; count < num_se; count++) { - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); - - result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); - if (0 != result) - break; - } - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); - mutex_unlock(&adev->grbm_idx_mutex); - - vega10_didt_set_mask(hwmgr, true); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10); - if (PP_CAP(PHM_PlatformCaps_GCEDC)) - vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10); - - if (PP_CAP(PHM_PlatformCaps_PSM)) - vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); - - return 0; -} - -static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t data; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - vega10_didt_set_mask(hwmgr, false); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - if (PP_CAP(PHM_PlatformCaps_GCEDC)) { - data = 0x00000000; - cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data); - } - - if (PP_CAP(PHM_PlatformCaps_PSM)) - vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); - - return 0; -} - -static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int result; - uint32_t num_se = 0, count, data; - - num_se = adev->gfx.config.max_shader_engines; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - mutex_lock(&adev->grbm_idx_mutex); - for (count = 0; count < num_se; count++) { - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); - result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); - - if (0 != result) - break; - } - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); - mutex_unlock(&adev->grbm_idx_mutex); - - vega10_didt_set_mask(hwmgr, true); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - return 0; -} - -static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - vega10_didt_set_mask(hwmgr, false); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - return 0; -} - -static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int result = 0; - uint32_t num_se = 0; - uint32_t count, data; - - num_se = adev->gfx.config.max_shader_engines; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); - - mutex_lock(&adev->grbm_idx_mutex); - for (count = 0; count < num_se; count++) { - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); - result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); - - if (0 != result) - break; - } - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); - mutex_unlock(&adev->grbm_idx_mutex); - - vega10_didt_set_mask(hwmgr, true); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10); - - if (PP_CAP(PHM_PlatformCaps_GCEDC)) { - vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10); - vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10); - } - - if (PP_CAP(PHM_PlatformCaps_PSM)) - vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); - - return 0; -} - -static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t data; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - vega10_didt_set_mask(hwmgr, false); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - if (PP_CAP(PHM_PlatformCaps_GCEDC)) { - data = 0x00000000; - cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data); - } - - if (PP_CAP(PHM_PlatformCaps_PSM)) - vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); - - return 0; -} - -static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int result; - - amdgpu_gfx_rlc_enter_safe_mode(adev); - - mutex_lock(&adev->grbm_idx_mutex); - WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); - mutex_unlock(&adev->grbm_idx_mutex); - - result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); - result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT); - if (0 != result) - return result; - - vega10_didt_set_mask(hwmgr, false); - - amdgpu_gfx_rlc_exit_safe_mode(adev); - - return 0; -} - -static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) -{ - int result; - - result = vega10_disable_se_edc_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result); - - return 0; -} - -int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) -{ - int result = 0; - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_DIDT].supported) { - if (data->smu_features[GNLD_DIDT].enabled) - PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n"); - - switch (data->registry_data.didt_mode) { - case 0: - result = vega10_enable_cac_driving_se_didt_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result); - break; - case 2: - result = vega10_enable_psm_gc_didt_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result); - break; - case 3: - result = vega10_enable_se_edc_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result); - break; - case 1: - case 4: - case 5: - result = vega10_enable_psm_gc_edc_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result); - break; - case 6: - result = vega10_enable_se_edc_force_stall_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result); - break; - default: - result = -EINVAL; - break; - } - - if (0 == result) { - result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap); - PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result); - data->smu_features[GNLD_DIDT].enabled = true; - } - } - - return result; -} - -int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) -{ - int result = 0; - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_DIDT].supported) { - if (!data->smu_features[GNLD_DIDT].enabled) - PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n"); - - switch (data->registry_data.didt_mode) { - case 0: - result = vega10_disable_cac_driving_se_didt_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result); - break; - case 2: - result = vega10_disable_psm_gc_didt_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result); - break; - case 3: - result = vega10_disable_se_edc_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result); - break; - case 1: - case 4: - case 5: - result = vega10_disable_psm_gc_edc_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result); - break; - case 6: - result = vega10_disable_se_edc_force_stall_config(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result); - break; - default: - result = -EINVAL; - break; - } - - if (0 == result) { - result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap); - PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result); - data->smu_features[GNLD_DIDT].enabled = false; - } - } - - return result; -} - -void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_tdp_table *tdp_table = table_info->tdp_table; - PPTable_t *table = &(data->smc_state_table.pp_table); - - table->SocketPowerLimit = cpu_to_le16( - tdp_table->usMaximumPowerDeliveryLimit); - table->TdcLimit = cpu_to_le16(tdp_table->usTDC); - table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit); - table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge); - table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot); - table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM); - table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc); - table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd); - table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1); - table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2); - table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx); - table->LoadLineResistance = - hwmgr->platform_descriptor.LoadLineSlope * 256; - table->FitLimit = 0; /* Not used for Vega10 */ - - table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address; - table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address; - table->Vr_I2C_address = tdp_table->ucVr_I2C_address; - table->Plx_I2C_address = tdp_table->ucPlx_I2C_address; - - table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line; - table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA; - - table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line; - table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA; - - table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line; - table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA; -} - -int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->registry_data.enable_pkg_pwr_tracking_feature) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetPptLimit, n, - NULL); - - return 0; -} - -int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_tdp_table *tdp_table = table_info->tdp_table; - int result = 0; - - hwmgr->default_power_limit = hwmgr->power_limit = - (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit); - - if (!hwmgr->not_vf) - return 0; - - if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { - if (data->smu_features[GNLD_PPT].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_PPT].smu_feature_bitmap), - "Attempt to enable PPT feature Failed!", - data->smu_features[GNLD_PPT].supported = false); - - if (data->smu_features[GNLD_TDC].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, data->smu_features[GNLD_TDC].smu_feature_bitmap), - "Attempt to enable PPT feature Failed!", - data->smu_features[GNLD_TDC].supported = false); - - result = vega10_set_power_limit(hwmgr, hwmgr->power_limit); - PP_ASSERT_WITH_CODE(!result, - "Failed to set Default Power Limit in SMC!", - return result); - } - - return result; -} - -int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { - if (data->smu_features[GNLD_PPT].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_PPT].smu_feature_bitmap), - "Attempt to disable PPT feature Failed!", - data->smu_features[GNLD_PPT].supported = false); - - if (data->smu_features[GNLD_TDC].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, data->smu_features[GNLD_TDC].smu_feature_bitmap), - "Attempt to disable PPT feature Failed!", - data->smu_features[GNLD_TDC].supported = false); - } - - return 0; -} - -static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, - uint32_t adjust_percent) -{ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_OverDriveSetPercentage, adjust_percent, - NULL); -} - -int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) -{ - int adjust_percent; - - if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { - adjust_percent = - hwmgr->platform_descriptor.TDPAdjustmentPolarity ? - hwmgr->platform_descriptor.TDPAdjustment : - (-1 * hwmgr->platform_descriptor.TDPAdjustment); - vega10_set_overdrive_target_percentage(hwmgr, - (uint32_t)adjust_percent); - } - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h deleted file mode 100644 index b95771ab89cd..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _VEGA10_POWERTUNE_H_ -#define _VEGA10_POWERTUNE_H_ - -enum vega10_pt_config_reg_type { - VEGA10_CONFIGREG_MMR = 0, - VEGA10_CONFIGREG_SMC_IND, - VEGA10_CONFIGREG_DIDT_IND, - VEGA10_CONFIGREG_CACHE, - VEGA10_CONFIGREG_MAX -}; - -enum vega10_didt_config_reg_type { - VEGA10_CONFIGREG_DIDT = 0, - VEGA10_CONFIGREG_GCCAC, - VEGA10_CONFIGREG_SECAC -}; - -/* PowerContainment Features */ -#define POWERCONTAINMENT_FEATURE_DTE 0x00000001 -#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 -#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 - -struct vega10_pt_config_reg { - uint32_t offset; - uint32_t mask; - uint32_t shift; - uint32_t value; - enum vega10_pt_config_reg_type type; -}; - -struct vega10_didt_config_reg { - uint32_t offset; - uint32_t mask; - uint32_t shift; - uint32_t value; -}; - -struct vega10_pt_defaults { - uint8_t SviLoadLineEn; - uint8_t SviLoadLineVddC; - uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; - uint8_t TDC_MAWt; - uint8_t TdcWaterfallCtl; - uint8_t DTEAmbientTempBase; -}; - -void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr); -int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr); -int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr); -int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr); -int vega10_enable_power_containment(struct pp_hwmgr *hwmgr); -int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); -int vega10_power_control_set_level(struct pp_hwmgr *hwmgr); -int vega10_disable_power_containment(struct pp_hwmgr *hwmgr); - -int vega10_enable_didt_config(struct pp_hwmgr *hwmgr); -int vega10_disable_didt_config(struct pp_hwmgr *hwmgr); - -#endif /* _VEGA10_POWERTUNE_H_ */ - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h deleted file mode 100644 index c934e9612c1b..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _VEGA10_PPTABLE_H_ -#define _VEGA10_PPTABLE_H_ - -#pragma pack(push, 1) - -#define ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f -#define ATOM_VEGA10_PP_FANPARAMETERS_NOFAN 0x80 - -#define ATOM_VEGA10_PP_THERMALCONTROLLER_NONE 0 -#define ATOM_VEGA10_PP_THERMALCONTROLLER_LM96163 17 -#define ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 24 - -#define ATOM_VEGA10_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 -#define ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D - -#define ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY 0x1 -#define ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 -#define ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC 0x4 -#define ATOM_VEGA10_PP_PLATFORM_CAP_BACO 0x8 -#define ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x10 - - -/* ATOM_PPLIB_NONCLOCK_INFO::usClassification */ -#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 -#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 -#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 -#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 -#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 -#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 -/* 2, 4, 6, 7 are reserved */ - -#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 -#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 -#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 -#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 -#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 -#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 - -/* ATOM_PPLIB_NONCLOCK_INFO::usClassification2 */ -#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 - -#define ATOM_Vega10_DISALLOW_ON_DC 0x00004000 -#define ATOM_Vega10_ENABLE_VARIBRIGHT 0x00008000 - -#define ATOM_Vega10_TABLE_REVISION_VEGA10 8 - -#define ATOM_Vega10_VoltageMode_AVFS_Interpolate 0 -#define ATOM_Vega10_VoltageMode_AVFS_WorstCase 1 -#define ATOM_Vega10_VoltageMode_Static 2 - -typedef struct _ATOM_Vega10_POWERPLAYTABLE { - struct atom_common_table_header sHeader; - UCHAR ucTableRevision; - USHORT usTableSize; /* the size of header structure */ - ULONG ulGoldenPPID; /* PPGen use only */ - ULONG ulGoldenRevision; /* PPGen use only */ - USHORT usFormatID; /* PPGen use only */ - ULONG ulPlatformCaps; /* See ATOM_Vega10_CAPS_* */ - ULONG ulMaxODEngineClock; /* For Overdrive. */ - ULONG ulMaxODMemoryClock; /* For Overdrive. */ - USHORT usPowerControlLimit; - USHORT usUlvVoltageOffset; /* in mv units */ - USHORT usUlvSmnclkDid; - USHORT usUlvMp1clkDid; - USHORT usUlvGfxclkBypass; - USHORT usGfxclkSlewRate; - UCHAR ucGfxVoltageMode; - UCHAR ucSocVoltageMode; - UCHAR ucUclkVoltageMode; - UCHAR ucUvdVoltageMode; - UCHAR ucVceVoltageMode; - UCHAR ucMp0VoltageMode; - UCHAR ucDcefVoltageMode; - USHORT usStateArrayOffset; /* points to ATOM_Vega10_State_Array */ - USHORT usFanTableOffset; /* points to ATOM_Vega10_Fan_Table */ - USHORT usThermalControllerOffset; /* points to ATOM_Vega10_Thermal_Controller */ - USHORT usSocclkDependencyTableOffset; /* points to ATOM_Vega10_SOCCLK_Dependency_Table */ - USHORT usMclkDependencyTableOffset; /* points to ATOM_Vega10_MCLK_Dependency_Table */ - USHORT usGfxclkDependencyTableOffset; /* points to ATOM_Vega10_GFXCLK_Dependency_Table */ - USHORT usDcefclkDependencyTableOffset; /* points to ATOM_Vega10_DCEFCLK_Dependency_Table */ - USHORT usVddcLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */ - USHORT usVddmemLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */ - USHORT usMMDependencyTableOffset; /* points to ATOM_Vega10_MM_Dependency_Table */ - USHORT usVCEStateTableOffset; /* points to ATOM_Vega10_VCE_State_Table */ - USHORT usReserve; /* No PPM Support for Vega10 */ - USHORT usPowerTuneTableOffset; /* points to ATOM_Vega10_PowerTune_Table */ - USHORT usHardLimitTableOffset; /* points to ATOM_Vega10_Hard_Limit_Table */ - USHORT usVddciLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */ - USHORT usPCIETableOffset; /* points to ATOM_Vega10_PCIE_Table */ - USHORT usPixclkDependencyTableOffset; /* points to ATOM_Vega10_PIXCLK_Dependency_Table */ - USHORT usDispClkDependencyTableOffset; /* points to ATOM_Vega10_DISPCLK_Dependency_Table */ - USHORT usPhyClkDependencyTableOffset; /* points to ATOM_Vega10_PHYCLK_Dependency_Table */ -} ATOM_Vega10_POWERPLAYTABLE; - -typedef struct _ATOM_Vega10_State { - UCHAR ucSocClockIndexHigh; - UCHAR ucSocClockIndexLow; - UCHAR ucGfxClockIndexHigh; - UCHAR ucGfxClockIndexLow; - UCHAR ucMemClockIndexHigh; - UCHAR ucMemClockIndexLow; - USHORT usClassification; - ULONG ulCapsAndSettings; - USHORT usClassification2; -} ATOM_Vega10_State; - -typedef struct _ATOM_Vega10_State_Array { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_State states[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_State_Array; - -typedef struct _ATOM_Vega10_CLK_Dependency_Record { - ULONG ulClk; /* Frequency of Clock */ - UCHAR ucVddInd; /* Base voltage */ -} ATOM_Vega10_CLK_Dependency_Record; - -typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record { - ULONG ulClk; /* Clock Frequency */ - UCHAR ucVddInd; /* SOC_VDD index */ - USHORT usCKSVOffsetandDisable; /* Bits 0~30: Voltage offset for CKS, Bit 31: Disable/enable for the GFXCLK level. */ - USHORT usAVFSOffset; /* AVFS Voltage offset */ -} ATOM_Vega10_GFXCLK_Dependency_Record; - -typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record_V2 { - ULONG ulClk; - UCHAR ucVddInd; - USHORT usCKSVOffsetandDisable; - USHORT usAVFSOffset; - UCHAR ucACGEnable; - UCHAR ucReserved[3]; -} ATOM_Vega10_GFXCLK_Dependency_Record_V2; - -typedef struct _ATOM_Vega10_MCLK_Dependency_Record { - ULONG ulMemClk; /* Clock Frequency */ - UCHAR ucVddInd; /* SOC_VDD index */ - UCHAR ucVddMemInd; /* MEM_VDD - only non zero for MCLK record */ - UCHAR ucVddciInd; /* VDDCI = only non zero for MCLK record */ -} ATOM_Vega10_MCLK_Dependency_Record; - -typedef struct _ATOM_Vega10_GFXCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_GFXCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_GFXCLK_Dependency_Table; - -typedef struct _ATOM_Vega10_MCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_MCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_MCLK_Dependency_Table; - -typedef struct _ATOM_Vega10_SOCCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_SOCCLK_Dependency_Table; - -typedef struct _ATOM_Vega10_DCEFCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_DCEFCLK_Dependency_Table; - -typedef struct _ATOM_Vega10_PIXCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_PIXCLK_Dependency_Table; - -typedef struct _ATOM_Vega10_DISPCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries.*/ - ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_DISPCLK_Dependency_Table; - -typedef struct _ATOM_Vega10_PHYCLK_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_PHYCLK_Dependency_Table; - -typedef struct _ATOM_Vega10_MM_Dependency_Record { - UCHAR ucVddcInd; /* SOC_VDD voltage */ - ULONG ulDClk; /* UVD D-clock */ - ULONG ulVClk; /* UVD V-clock */ - ULONG ulEClk; /* VCE clock */ - ULONG ulPSPClk; /* PSP clock */ -} ATOM_Vega10_MM_Dependency_Record; - -typedef struct _ATOM_Vega10_MM_Dependency_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries */ - ATOM_Vega10_MM_Dependency_Record entries[1]; /* Dynamically allocate entries */ -} ATOM_Vega10_MM_Dependency_Table; - -typedef struct _ATOM_Vega10_PCIE_Record { - ULONG ulLCLK; /* LClock */ - UCHAR ucPCIEGenSpeed; /* PCIE Speed */ - UCHAR ucPCIELaneWidth; /* PCIE Lane Width */ -} ATOM_Vega10_PCIE_Record; - -typedef struct _ATOM_Vega10_PCIE_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries */ - ATOM_Vega10_PCIE_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Vega10_PCIE_Table; - -typedef struct _ATOM_Vega10_Voltage_Lookup_Record { - USHORT usVdd; /* Base voltage */ -} ATOM_Vega10_Voltage_Lookup_Record; - -typedef struct _ATOM_Vega10_Voltage_Lookup_Table { - UCHAR ucRevId; - UCHAR ucNumEntries; /* Number of entries */ - ATOM_Vega10_Voltage_Lookup_Record entries[1]; /* Dynamically allocate entries */ -} ATOM_Vega10_Voltage_Lookup_Table; - -typedef struct _ATOM_Vega10_Fan_Table { - UCHAR ucRevId; /* Change this if the table format changes or version changes so that the other fields are not the same. */ - USHORT usFanOutputSensitivity; /* Sensitivity of fan reaction to temepature changes. */ - USHORT usFanRPMMax; /* The default value in RPM. */ - USHORT usThrottlingRPM; - USHORT usFanAcousticLimit; /* Minimum Fan Controller Frequency Acoustic Limit. */ - USHORT usTargetTemperature; /* The default ideal temperature in Celcius. */ - USHORT usMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. */ - USHORT usTargetGfxClk; /* The ideal Fan Controller GFXCLK Frequency Acoustic Limit. */ - USHORT usFanGainEdge; - USHORT usFanGainHotspot; - USHORT usFanGainLiquid; - USHORT usFanGainVrVddc; - USHORT usFanGainVrMvdd; - USHORT usFanGainPlx; - USHORT usFanGainHbm; - UCHAR ucEnableZeroRPM; - USHORT usFanStopTemperature; - USHORT usFanStartTemperature; -} ATOM_Vega10_Fan_Table; - -typedef struct _ATOM_Vega10_Fan_Table_V2 { - UCHAR ucRevId; - USHORT usFanOutputSensitivity; - USHORT usFanAcousticLimitRpm; - USHORT usThrottlingRPM; - USHORT usTargetTemperature; - USHORT usMinimumPWMLimit; - USHORT usTargetGfxClk; - USHORT usFanGainEdge; - USHORT usFanGainHotspot; - USHORT usFanGainLiquid; - USHORT usFanGainVrVddc; - USHORT usFanGainVrMvdd; - USHORT usFanGainPlx; - USHORT usFanGainHbm; - UCHAR ucEnableZeroRPM; - USHORT usFanStopTemperature; - USHORT usFanStartTemperature; - UCHAR ucFanParameters; - UCHAR ucFanMinRPM; - UCHAR ucFanMaxRPM; -} ATOM_Vega10_Fan_Table_V2; - -typedef struct _ATOM_Vega10_Fan_Table_V3 { - UCHAR ucRevId; - USHORT usFanOutputSensitivity; - USHORT usFanAcousticLimitRpm; - USHORT usThrottlingRPM; - USHORT usTargetTemperature; - USHORT usMinimumPWMLimit; - USHORT usTargetGfxClk; - USHORT usFanGainEdge; - USHORT usFanGainHotspot; - USHORT usFanGainLiquid; - USHORT usFanGainVrVddc; - USHORT usFanGainVrMvdd; - USHORT usFanGainPlx; - USHORT usFanGainHbm; - UCHAR ucEnableZeroRPM; - USHORT usFanStopTemperature; - USHORT usFanStartTemperature; - UCHAR ucFanParameters; - UCHAR ucFanMinRPM; - UCHAR ucFanMaxRPM; - USHORT usMGpuThrottlingRPM; -} ATOM_Vega10_Fan_Table_V3; - -typedef struct _ATOM_Vega10_Thermal_Controller { - UCHAR ucRevId; - UCHAR ucType; /* one of ATOM_VEGA10_PP_THERMALCONTROLLER_*/ - UCHAR ucI2cLine; /* as interpreted by DAL I2C */ - UCHAR ucI2cAddress; - UCHAR ucFanParameters; /* Fan Control Parameters. */ - UCHAR ucFanMinRPM; /* Fan Minimum RPM (hundreds) -- for display purposes only.*/ - UCHAR ucFanMaxRPM; /* Fan Maximum RPM (hundreds) -- for display purposes only.*/ - UCHAR ucFlags; /* to be defined */ -} ATOM_Vega10_Thermal_Controller; - -typedef struct _ATOM_Vega10_VCE_State_Record -{ - UCHAR ucVCEClockIndex; /*index into usVCEDependencyTableOffset of 'ATOM_Vega10_MM_Dependency_Table' type */ - UCHAR ucFlag; /* 2 bits indicates memory p-states */ - UCHAR ucSCLKIndex; /* index into ATOM_Vega10_SCLK_Dependency_Table */ - UCHAR ucMCLKIndex; /* index into ATOM_Vega10_MCLK_Dependency_Table */ -} ATOM_Vega10_VCE_State_Record; - -typedef struct _ATOM_Vega10_VCE_State_Table -{ - UCHAR ucRevId; - UCHAR ucNumEntries; - ATOM_Vega10_VCE_State_Record entries[1]; -} ATOM_Vega10_VCE_State_Table; - -typedef struct _ATOM_Vega10_PowerTune_Table { - UCHAR ucRevId; - USHORT usSocketPowerLimit; - USHORT usBatteryPowerLimit; - USHORT usSmallPowerLimit; - USHORT usTdcLimit; - USHORT usEdcLimit; - USHORT usSoftwareShutdownTemp; - USHORT usTemperatureLimitHotSpot; - USHORT usTemperatureLimitLiquid1; - USHORT usTemperatureLimitLiquid2; - USHORT usTemperatureLimitHBM; - USHORT usTemperatureLimitVrSoc; - USHORT usTemperatureLimitVrMem; - USHORT usTemperatureLimitPlx; - USHORT usLoadLineResistance; - UCHAR ucLiquid1_I2C_address; - UCHAR ucLiquid2_I2C_address; - UCHAR ucVr_I2C_address; - UCHAR ucPlx_I2C_address; - UCHAR ucLiquid_I2C_LineSCL; - UCHAR ucLiquid_I2C_LineSDA; - UCHAR ucVr_I2C_LineSCL; - UCHAR ucVr_I2C_LineSDA; - UCHAR ucPlx_I2C_LineSCL; - UCHAR ucPlx_I2C_LineSDA; - USHORT usTemperatureLimitTedge; -} ATOM_Vega10_PowerTune_Table; - -typedef struct _ATOM_Vega10_PowerTune_Table_V2 -{ - UCHAR ucRevId; - USHORT usSocketPowerLimit; - USHORT usBatteryPowerLimit; - USHORT usSmallPowerLimit; - USHORT usTdcLimit; - USHORT usEdcLimit; - USHORT usSoftwareShutdownTemp; - USHORT usTemperatureLimitHotSpot; - USHORT usTemperatureLimitLiquid1; - USHORT usTemperatureLimitLiquid2; - USHORT usTemperatureLimitHBM; - USHORT usTemperatureLimitVrSoc; - USHORT usTemperatureLimitVrMem; - USHORT usTemperatureLimitPlx; - USHORT usLoadLineResistance; - UCHAR ucLiquid1_I2C_address; - UCHAR ucLiquid2_I2C_address; - UCHAR ucLiquid_I2C_Line; - UCHAR ucVr_I2C_address; - UCHAR ucVr_I2C_Line; - UCHAR ucPlx_I2C_address; - UCHAR ucPlx_I2C_Line; - USHORT usTemperatureLimitTedge; -} ATOM_Vega10_PowerTune_Table_V2; - -typedef struct _ATOM_Vega10_PowerTune_Table_V3 -{ - UCHAR ucRevId; - USHORT usSocketPowerLimit; - USHORT usBatteryPowerLimit; - USHORT usSmallPowerLimit; - USHORT usTdcLimit; - USHORT usEdcLimit; - USHORT usSoftwareShutdownTemp; - USHORT usTemperatureLimitHotSpot; - USHORT usTemperatureLimitLiquid1; - USHORT usTemperatureLimitLiquid2; - USHORT usTemperatureLimitHBM; - USHORT usTemperatureLimitVrSoc; - USHORT usTemperatureLimitVrMem; - USHORT usTemperatureLimitPlx; - USHORT usLoadLineResistance; - UCHAR ucLiquid1_I2C_address; - UCHAR ucLiquid2_I2C_address; - UCHAR ucLiquid_I2C_Line; - UCHAR ucVr_I2C_address; - UCHAR ucVr_I2C_Line; - UCHAR ucPlx_I2C_address; - UCHAR ucPlx_I2C_Line; - USHORT usTemperatureLimitTedge; - USHORT usBoostStartTemperature; - USHORT usBoostStopTemperature; - ULONG ulBoostClock; - ULONG Reserved[2]; -} ATOM_Vega10_PowerTune_Table_V3; - -typedef struct _ATOM_Vega10_Hard_Limit_Record { - ULONG ulSOCCLKLimit; - ULONG ulGFXCLKLimit; - ULONG ulMCLKLimit; - USHORT usVddcLimit; - USHORT usVddciLimit; - USHORT usVddMemLimit; -} ATOM_Vega10_Hard_Limit_Record; - -typedef struct _ATOM_Vega10_Hard_Limit_Table -{ - UCHAR ucRevId; - UCHAR ucNumEntries; - ATOM_Vega10_Hard_Limit_Record entries[1]; -} ATOM_Vega10_Hard_Limit_Table; - -typedef struct _Vega10_PPTable_Generic_SubTable_Header -{ - UCHAR ucRevId; -} Vega10_PPTable_Generic_SubTable_Header; - -#pragma pack(pop) - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c deleted file mode 100644 index f29af5ca0aa0..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c +++ /dev/null @@ -1,1398 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include <linux/module.h> -#include <linux/pci.h> -#include <linux/slab.h> -#include <linux/fb.h> - -#include "vega10_processpptables.h" -#include "ppatomfwctrl.h" -#include "atomfirmware.h" -#include "pp_debug.h" -#include "cgs_common.h" -#include "vega10_pptable.h" - -#define NUM_DSPCLK_LEVELS 8 -#define VEGA10_ENGINECLOCK_HARDMAX 198000 - -static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, - enum phm_platform_caps cap) -{ - if (enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); - else - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); -} - -static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) -{ - int index = GetIndexIntoMasterDataTable(powerplayinfo); - - u16 size; - u8 frev, crev; - const void *table_address = hwmgr->soft_pp_table; - - if (!table_address) { - table_address = (ATOM_Vega10_POWERPLAYTABLE *) - smu_atom_get_data_table(hwmgr->adev, index, - &size, &frev, &crev); - - hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ - hwmgr->soft_pp_table_size = size; - } - - return table_address; -} - -static int check_powerplay_tables( - struct pp_hwmgr *hwmgr, - const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) -{ - const ATOM_Vega10_State_Array *state_arrays; - - state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usStateArrayOffset)); - - PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= - ATOM_Vega10_TABLE_REVISION_VEGA10), - "Unsupported PPTable format!", return -1); - PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset, - "State table is not set!", return -1); - PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, - "Invalid PowerPlay Table!", return -1); - PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, - "Invalid PowerPlay Table!", return -1); - - return 0; -} - -static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) -{ - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY), - PHM_PlatformCaps_PowerPlaySupport); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), - PHM_PlatformCaps_BiosPowerSourceControl); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC), - PHM_PlatformCaps_AutomaticDCTransition); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_BACO), - PHM_PlatformCaps_BACO); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL), - PHM_PlatformCaps_CombinePCCWithThermalSignal); - - return 0; -} - -static int init_thermal_controller( - struct pp_hwmgr *hwmgr, - const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) -{ - const ATOM_Vega10_Thermal_Controller *thermal_controller; - const Vega10_PPTable_Generic_SubTable_Header *header; - const ATOM_Vega10_Fan_Table *fan_table_v1; - const ATOM_Vega10_Fan_Table_V2 *fan_table_v2; - const ATOM_Vega10_Fan_Table_V3 *fan_table_v3; - - thermal_controller = (ATOM_Vega10_Thermal_Controller *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usThermalControllerOffset)); - - PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0), - "Thermal controller table not set!", return -EINVAL); - - hwmgr->thermal_controller.ucType = thermal_controller->ucType; - hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine; - hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress; - - hwmgr->thermal_controller.fanInfo.bNoFan = - (0 != (thermal_controller->ucFanParameters & - ATOM_VEGA10_PP_FANPARAMETERS_NOFAN)); - - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = - thermal_controller->ucFanParameters & - ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; - - hwmgr->thermal_controller.fanInfo.ulMinRPM = - thermal_controller->ucFanMinRPM * 100UL; - hwmgr->thermal_controller.fanInfo.ulMaxRPM = - thermal_controller->ucFanMaxRPM * 100UL; - - hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay - = 100000; - - set_hw_cap( - hwmgr, - ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, - PHM_PlatformCaps_ThermalController); - - if (!powerplay_table->usFanTableOffset) - return 0; - - header = (const Vega10_PPTable_Generic_SubTable_Header *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usFanTableOffset)); - - if (header->ucRevId == 10) { - fan_table_v1 = (ATOM_Vega10_Fan_Table *)header; - - PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8), - "Invalid Input Fan Table!", return -EINVAL); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl); - - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = - le16_to_cpu(fan_table_v1->usFanOutputSensitivity); - hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = - le16_to_cpu(fan_table_v1->usFanRPMMax); - hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = - le16_to_cpu(fan_table_v1->usThrottlingRPM); - hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit = - le16_to_cpu(fan_table_v1->usFanAcousticLimit); - hwmgr->thermal_controller.advanceFanControlParameters.usTMax = - le16_to_cpu(fan_table_v1->usTargetTemperature); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = - le16_to_cpu(fan_table_v1->usMinimumPWMLimit); - hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk = - le16_to_cpu(fan_table_v1->usTargetGfxClk); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge = - le16_to_cpu(fan_table_v1->usFanGainEdge); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot = - le16_to_cpu(fan_table_v1->usFanGainHotspot); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid = - le16_to_cpu(fan_table_v1->usFanGainLiquid); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc = - le16_to_cpu(fan_table_v1->usFanGainVrVddc); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd = - le16_to_cpu(fan_table_v1->usFanGainVrMvdd); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx = - le16_to_cpu(fan_table_v1->usFanGainPlx); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm = - le16_to_cpu(fan_table_v1->usFanGainHbm); - - hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM = - fan_table_v1->ucEnableZeroRPM; - hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature = - le16_to_cpu(fan_table_v1->usFanStopTemperature); - hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature = - le16_to_cpu(fan_table_v1->usFanStartTemperature); - } else if (header->ucRevId == 0xb) { - fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header; - - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = - fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; - hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL; - hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl); - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = - le16_to_cpu(fan_table_v2->usFanOutputSensitivity); - hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = - fan_table_v2->ucFanMaxRPM * 100UL; - hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = - le16_to_cpu(fan_table_v2->usThrottlingRPM); - hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit = - le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm); - hwmgr->thermal_controller.advanceFanControlParameters.usTMax = - le16_to_cpu(fan_table_v2->usTargetTemperature); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = - le16_to_cpu(fan_table_v2->usMinimumPWMLimit); - hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk = - le16_to_cpu(fan_table_v2->usTargetGfxClk); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge = - le16_to_cpu(fan_table_v2->usFanGainEdge); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot = - le16_to_cpu(fan_table_v2->usFanGainHotspot); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid = - le16_to_cpu(fan_table_v2->usFanGainLiquid); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc = - le16_to_cpu(fan_table_v2->usFanGainVrVddc); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd = - le16_to_cpu(fan_table_v2->usFanGainVrMvdd); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx = - le16_to_cpu(fan_table_v2->usFanGainPlx); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm = - le16_to_cpu(fan_table_v2->usFanGainHbm); - - hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM = - fan_table_v2->ucEnableZeroRPM; - hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature = - le16_to_cpu(fan_table_v2->usFanStopTemperature); - hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature = - le16_to_cpu(fan_table_v2->usFanStartTemperature); - } else if (header->ucRevId > 0xb) { - fan_table_v3 = (ATOM_Vega10_Fan_Table_V3 *)header; - - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = - fan_table_v3->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; - hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v3->ucFanMinRPM * 100UL; - hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v3->ucFanMaxRPM * 100UL; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl); - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = - le16_to_cpu(fan_table_v3->usFanOutputSensitivity); - hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = - fan_table_v3->ucFanMaxRPM * 100UL; - hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = - le16_to_cpu(fan_table_v3->usThrottlingRPM); - hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit = - le16_to_cpu(fan_table_v3->usFanAcousticLimitRpm); - hwmgr->thermal_controller.advanceFanControlParameters.usTMax = - le16_to_cpu(fan_table_v3->usTargetTemperature); - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = - le16_to_cpu(fan_table_v3->usMinimumPWMLimit); - hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk = - le16_to_cpu(fan_table_v3->usTargetGfxClk); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge = - le16_to_cpu(fan_table_v3->usFanGainEdge); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot = - le16_to_cpu(fan_table_v3->usFanGainHotspot); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid = - le16_to_cpu(fan_table_v3->usFanGainLiquid); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc = - le16_to_cpu(fan_table_v3->usFanGainVrVddc); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd = - le16_to_cpu(fan_table_v3->usFanGainVrMvdd); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx = - le16_to_cpu(fan_table_v3->usFanGainPlx); - hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm = - le16_to_cpu(fan_table_v3->usFanGainHbm); - - hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM = - fan_table_v3->ucEnableZeroRPM; - hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature = - le16_to_cpu(fan_table_v3->usFanStopTemperature); - hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature = - le16_to_cpu(fan_table_v3->usFanStartTemperature); - hwmgr->thermal_controller.advanceFanControlParameters.usMGpuThrottlingRPMLimit = - le16_to_cpu(fan_table_v3->usMGpuThrottlingRPM); - } - - return 0; -} - -static int init_over_drive_limits( - struct pp_hwmgr *hwmgr, - const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) -{ - const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = - (const ATOM_Vega10_GFXCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); - bool is_acg_enabled = false; - ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2; - - if (gfxclk_dep_table->ucRevId == 1) { - patom_record_v2 = - (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; - is_acg_enabled = - (bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable; - } - - if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX && - !is_acg_enabled) - hwmgr->platform_descriptor.overdriveLimit.engineClock = - VEGA10_ENGINECLOCK_HARDMAX; - else - hwmgr->platform_descriptor.overdriveLimit.engineClock = - le32_to_cpu(powerplay_table->ulMaxODEngineClock); - hwmgr->platform_descriptor.overdriveLimit.memoryClock = - le32_to_cpu(powerplay_table->ulMaxODMemoryClock); - - hwmgr->platform_descriptor.minOverdriveVDDC = 0; - hwmgr->platform_descriptor.maxOverdriveVDDC = 0; - hwmgr->platform_descriptor.overdriveVDDCStep = 0; - - return 0; -} - -static int get_mm_clock_voltage_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table, - const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table) -{ - uint32_t table_size, i; - const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record; - phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table; - - PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) * - mm_dependency_table->ucNumEntries; - mm_table = kzalloc(table_size, GFP_KERNEL); - - if (!mm_table) - return -ENOMEM; - - mm_table->count = mm_dependency_table->ucNumEntries; - - for (i = 0; i < mm_dependency_table->ucNumEntries; i++) { - mm_dependency_record = &mm_dependency_table->entries[i]; - mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd; - mm_table->entries[i].samclock = - le32_to_cpu(mm_dependency_record->ulPSPClk); - mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk); - mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk); - mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk); - } - - *vega10_mm_table = mm_table; - - return 0; -} - -static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda) -{ - switch(line){ - case Vega10_I2CLineID_DDC1: - *scl = Vega10_I2C_DDC1CLK; - *sda = Vega10_I2C_DDC1DATA; - break; - case Vega10_I2CLineID_DDC2: - *scl = Vega10_I2C_DDC2CLK; - *sda = Vega10_I2C_DDC2DATA; - break; - case Vega10_I2CLineID_DDC3: - *scl = Vega10_I2C_DDC3CLK; - *sda = Vega10_I2C_DDC3DATA; - break; - case Vega10_I2CLineID_DDC4: - *scl = Vega10_I2C_DDC4CLK; - *sda = Vega10_I2C_DDC4DATA; - break; - case Vega10_I2CLineID_DDC5: - *scl = Vega10_I2C_DDC5CLK; - *sda = Vega10_I2C_DDC5DATA; - break; - case Vega10_I2CLineID_DDC6: - *scl = Vega10_I2C_DDC6CLK; - *sda = Vega10_I2C_DDC6DATA; - break; - case Vega10_I2CLineID_SCLSDA: - *scl = Vega10_I2C_SCL; - *sda = Vega10_I2C_SDA; - break; - case Vega10_I2CLineID_DDCVGA: - *scl = Vega10_I2C_DDCVGACLK; - *sda = Vega10_I2C_DDCVGADATA; - break; - default: - *scl = 0; - *sda = 0; - break; - } -} - -static int get_tdp_table( - struct pp_hwmgr *hwmgr, - struct phm_tdp_table **info_tdp_table, - const Vega10_PPTable_Generic_SubTable_Header *table) -{ - uint32_t table_size; - struct phm_tdp_table *tdp_table; - uint8_t scl; - uint8_t sda; - const ATOM_Vega10_PowerTune_Table *power_tune_table; - const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2; - const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3; - - table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table); - - tdp_table = kzalloc(table_size, GFP_KERNEL); - - if (!tdp_table) - return -ENOMEM; - - if (table->ucRevId == 5) { - power_tune_table = (ATOM_Vega10_PowerTune_Table *)table; - tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit); - tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit); - tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit); - tdp_table->usSoftwareShutdownTemp = - le16_to_cpu(power_tune_table->usSoftwareShutdownTemp); - tdp_table->usTemperatureLimitTedge = - le16_to_cpu(power_tune_table->usTemperatureLimitTedge); - tdp_table->usTemperatureLimitHotspot = - le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot); - tdp_table->usTemperatureLimitLiquid1 = - le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1); - tdp_table->usTemperatureLimitLiquid2 = - le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2); - tdp_table->usTemperatureLimitHBM = - le16_to_cpu(power_tune_table->usTemperatureLimitHBM); - tdp_table->usTemperatureLimitVrVddc = - le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc); - tdp_table->usTemperatureLimitVrMvdd = - le16_to_cpu(power_tune_table->usTemperatureLimitVrMem); - tdp_table->usTemperatureLimitPlx = - le16_to_cpu(power_tune_table->usTemperatureLimitPlx); - tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address; - tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address; - tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL; - tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA; - tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address; - tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL; - tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA; - tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address; - tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL; - tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA; - hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance); - } else if (table->ucRevId == 6) { - power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table; - tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit); - tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit); - tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit); - tdp_table->usSoftwareShutdownTemp = - le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp); - tdp_table->usTemperatureLimitTedge = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge); - tdp_table->usTemperatureLimitHotspot = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot); - tdp_table->usTemperatureLimitLiquid1 = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1); - tdp_table->usTemperatureLimitLiquid2 = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2); - tdp_table->usTemperatureLimitHBM = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM); - tdp_table->usTemperatureLimitVrVddc = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc); - tdp_table->usTemperatureLimitVrMvdd = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem); - tdp_table->usTemperatureLimitPlx = - le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx); - tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address; - tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address; - - get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda); - - tdp_table->ucLiquid_I2C_Line = scl; - tdp_table->ucLiquid_I2C_LineSDA = sda; - - tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address; - - get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda); - - tdp_table->ucVr_I2C_Line = scl; - tdp_table->ucVr_I2C_LineSDA = sda; - tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address; - - get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda); - - tdp_table->ucPlx_I2C_Line = scl; - tdp_table->ucPlx_I2C_LineSDA = sda; - - hwmgr->platform_descriptor.LoadLineSlope = - le16_to_cpu(power_tune_table_v2->usLoadLineResistance); - } else { - power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table; - tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v3->usSocketPowerLimit); - tdp_table->usTDC = le16_to_cpu(power_tune_table_v3->usTdcLimit); - tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v3->usEdcLimit); - tdp_table->usSoftwareShutdownTemp = le16_to_cpu(power_tune_table_v3->usSoftwareShutdownTemp); - tdp_table->usTemperatureLimitTedge = le16_to_cpu(power_tune_table_v3->usTemperatureLimitTedge); - tdp_table->usTemperatureLimitHotspot = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHotSpot); - tdp_table->usTemperatureLimitLiquid1 = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid1); - tdp_table->usTemperatureLimitLiquid2 = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid2); - tdp_table->usTemperatureLimitHBM = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHBM); - tdp_table->usTemperatureLimitVrVddc = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrSoc); - tdp_table->usTemperatureLimitVrMvdd = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrMem); - tdp_table->usTemperatureLimitPlx = le16_to_cpu(power_tune_table_v3->usTemperatureLimitPlx); - tdp_table->ucLiquid1_I2C_address = power_tune_table_v3->ucLiquid1_I2C_address; - tdp_table->ucLiquid2_I2C_address = power_tune_table_v3->ucLiquid2_I2C_address; - tdp_table->usBoostStartTemperature = le16_to_cpu(power_tune_table_v3->usBoostStartTemperature); - tdp_table->usBoostStopTemperature = le16_to_cpu(power_tune_table_v3->usBoostStopTemperature); - tdp_table->ulBoostClock = le32_to_cpu(power_tune_table_v3->ulBoostClock); - - get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda); - - tdp_table->ucLiquid_I2C_Line = scl; - tdp_table->ucLiquid_I2C_LineSDA = sda; - - tdp_table->ucVr_I2C_address = power_tune_table_v3->ucVr_I2C_address; - - get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda); - - tdp_table->ucVr_I2C_Line = scl; - tdp_table->ucVr_I2C_LineSDA = sda; - - tdp_table->ucPlx_I2C_address = power_tune_table_v3->ucPlx_I2C_address; - - get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda); - - tdp_table->ucPlx_I2C_Line = scl; - tdp_table->ucPlx_I2C_LineSDA = sda; - - hwmgr->platform_descriptor.LoadLineSlope = - le16_to_cpu(power_tune_table_v3->usLoadLineResistance); - } - - *info_tdp_table = tdp_table; - - return 0; -} - -static int get_socclk_voltage_dependency_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table, - const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table) -{ - uint32_t table_size, i; - phm_ppt_v1_clock_voltage_dependency_table *clk_table; - - PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries, - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_clock_voltage_dependency_record) * - clk_dep_table->ucNumEntries; - - clk_table = kzalloc(table_size, GFP_KERNEL); - - if (!clk_table) - return -ENOMEM; - - clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; - - for (i = 0; i < clk_dep_table->ucNumEntries; i++) { - clk_table->entries[i].vddInd = - clk_dep_table->entries[i].ucVddInd; - clk_table->entries[i].clk = - le32_to_cpu(clk_dep_table->entries[i].ulClk); - } - - *pp_vega10_clk_dep_table = clk_table; - - return 0; -} - -static int get_mclk_voltage_dependency_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table, - const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table) -{ - uint32_t table_size, i; - phm_ppt_v1_clock_voltage_dependency_table *mclk_table; - - PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries, - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_clock_voltage_dependency_record) * - mclk_dep_table->ucNumEntries; - - mclk_table = kzalloc(table_size, GFP_KERNEL); - - if (!mclk_table) - return -ENOMEM; - - mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; - - for (i = 0; i < mclk_dep_table->ucNumEntries; i++) { - mclk_table->entries[i].vddInd = - mclk_dep_table->entries[i].ucVddInd; - mclk_table->entries[i].vddciInd = - mclk_dep_table->entries[i].ucVddciInd; - mclk_table->entries[i].mvddInd = - mclk_dep_table->entries[i].ucVddMemInd; - mclk_table->entries[i].clk = - le32_to_cpu(mclk_dep_table->entries[i].ulMemClk); - } - - *pp_vega10_mclk_dep_table = mclk_table; - - return 0; -} - -static int get_gfxclk_voltage_dependency_table( - struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_clock_voltage_dependency_table - **pp_vega10_clk_dep_table, - const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table) -{ - uint32_t table_size, i; - struct phm_ppt_v1_clock_voltage_dependency_table - *clk_table; - ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2; - - PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_clock_voltage_dependency_record) * - clk_dep_table->ucNumEntries; - - clk_table = kzalloc(table_size, GFP_KERNEL); - - if (!clk_table) - return -ENOMEM; - - clk_table->count = clk_dep_table->ucNumEntries; - - if (clk_dep_table->ucRevId == 0) { - for (i = 0; i < clk_table->count; i++) { - clk_table->entries[i].vddInd = - clk_dep_table->entries[i].ucVddInd; - clk_table->entries[i].clk = - le32_to_cpu(clk_dep_table->entries[i].ulClk); - clk_table->entries[i].cks_enable = - (((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000) - >> 15) == 0) ? 1 : 0; - clk_table->entries[i].cks_voffset = - le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F; - clk_table->entries[i].sclk_offset = - le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset); - } - } else if (clk_dep_table->ucRevId == 1) { - patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries; - for (i = 0; i < clk_table->count; i++) { - clk_table->entries[i].vddInd = - patom_record_v2->ucVddInd; - clk_table->entries[i].clk = - le32_to_cpu(patom_record_v2->ulClk); - clk_table->entries[i].cks_enable = - (((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000) - >> 15) == 0) ? 1 : 0; - clk_table->entries[i].cks_voffset = - le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F; - clk_table->entries[i].sclk_offset = - le16_to_cpu(patom_record_v2->usAVFSOffset); - patom_record_v2++; - } - } else { - kfree(clk_table); - PP_ASSERT_WITH_CODE(false, - "Unsupported GFXClockDependencyTable Revision!", - return -EINVAL); - } - - *pp_vega10_clk_dep_table = clk_table; - - return 0; -} - -static int get_pix_clk_voltage_dependency_table( - struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_clock_voltage_dependency_table - **pp_vega10_clk_dep_table, - const ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table) -{ - uint32_t table_size, i; - struct phm_ppt_v1_clock_voltage_dependency_table - *clk_table; - - PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_clock_voltage_dependency_record) * - clk_dep_table->ucNumEntries; - - clk_table = kzalloc(table_size, GFP_KERNEL); - - if (!clk_table) - return -ENOMEM; - - clk_table->count = clk_dep_table->ucNumEntries; - - for (i = 0; i < clk_table->count; i++) { - clk_table->entries[i].vddInd = - clk_dep_table->entries[i].ucVddInd; - clk_table->entries[i].clk = - le32_to_cpu(clk_dep_table->entries[i].ulClk); - } - - *pp_vega10_clk_dep_table = clk_table; - - return 0; -} - -static int get_dcefclk_voltage_dependency_table( - struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_clock_voltage_dependency_table - **pp_vega10_clk_dep_table, - const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table) -{ - uint32_t table_size, i; - uint8_t num_entries; - struct phm_ppt_v1_clock_voltage_dependency_table - *clk_table; - uint32_t dev_id; - uint32_t rev_id; - struct amdgpu_device *adev = hwmgr->adev; - - PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), - "Invalid PowerPlay Table!", return -1); - -/* - * workaround needed to add another DPM level for pioneer cards - * as VBIOS is locked down. - * This DPM level was added to support 3DPM monitors @ 4K120Hz - * - */ - dev_id = adev->pdev->device; - rev_id = adev->pdev->revision; - - if (dev_id == 0x6863 && rev_id == 0 && - clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000) - num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ? - NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1; - else - num_entries = clk_dep_table->ucNumEntries; - - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_clock_voltage_dependency_record) * - num_entries; - - clk_table = kzalloc(table_size, GFP_KERNEL); - - if (!clk_table) - return -ENOMEM; - - clk_table->count = (uint32_t)num_entries; - - for (i = 0; i < clk_dep_table->ucNumEntries; i++) { - clk_table->entries[i].vddInd = - clk_dep_table->entries[i].ucVddInd; - clk_table->entries[i].clk = - le32_to_cpu(clk_dep_table->entries[i].ulClk); - } - - if (i < num_entries) { - clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd; - clk_table->entries[i].clk = 90000; - } - - *pp_vega10_clk_dep_table = clk_table; - - return 0; -} - -static int get_pcie_table(struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_pcie_table **vega10_pcie_table, - const Vega10_PPTable_Generic_SubTable_Header *table) -{ - uint32_t table_size, i, pcie_count; - struct phm_ppt_v1_pcie_table *pcie_table; - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - const ATOM_Vega10_PCIE_Table *atom_pcie_table = - (ATOM_Vega10_PCIE_Table *)table; - - PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries, - "Invalid PowerPlay Table!", - return 0); - - table_size = sizeof(uint32_t) + - sizeof(struct phm_ppt_v1_pcie_record) * - atom_pcie_table->ucNumEntries; - - pcie_table = kzalloc(table_size, GFP_KERNEL); - - if (!pcie_table) - return -ENOMEM; - - pcie_count = table_info->vdd_dep_on_sclk->count; - if (atom_pcie_table->ucNumEntries <= pcie_count) - pcie_count = atom_pcie_table->ucNumEntries; - else - pr_info("Number of Pcie Entries exceed the number of" - " GFXCLK Dpm Levels!" - " Disregarding the excess entries...\n"); - - pcie_table->count = pcie_count; - - for (i = 0; i < pcie_count; i++) { - pcie_table->entries[i].gen_speed = - atom_pcie_table->entries[i].ucPCIEGenSpeed; - pcie_table->entries[i].lane_width = - atom_pcie_table->entries[i].ucPCIELaneWidth; - pcie_table->entries[i].pcie_sclk = - atom_pcie_table->entries[i].ulLCLK; - } - - *vega10_pcie_table = pcie_table; - - return 0; -} - -static int get_hard_limits( - struct pp_hwmgr *hwmgr, - struct phm_clock_and_voltage_limits *limits, - const ATOM_Vega10_Hard_Limit_Table *limit_table) -{ - PP_ASSERT_WITH_CODE(limit_table->ucNumEntries, - "Invalid PowerPlay Table!", return -1); - - /* currently we always take entries[0] parameters */ - limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit); - limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit); - limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit); - limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit); - limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit); - limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit); - - return 0; -} - -static int get_valid_clk( - struct pp_hwmgr *hwmgr, - struct phm_clock_array **clk_table, - const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table) -{ - uint32_t table_size, i; - struct phm_clock_array *table; - - PP_ASSERT_WITH_CODE(clk_volt_pp_table->count, - "Invalid PowerPlay Table!", return -1); - - table_size = sizeof(uint32_t) + - sizeof(uint32_t) * clk_volt_pp_table->count; - - table = kzalloc(table_size, GFP_KERNEL); - - if (!table) - return -ENOMEM; - - table->count = (uint32_t)clk_volt_pp_table->count; - - for (i = 0; i < table->count; i++) - table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk; - - *clk_table = table; - - return 0; -} - -static int init_powerplay_extended_tables( - struct pp_hwmgr *hwmgr, - const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) -{ - int result = 0; - struct phm_ppt_v2_information *pp_table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - - const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table = - (const ATOM_Vega10_MM_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usMMDependencyTableOffset)); - const Vega10_PPTable_Generic_SubTable_Header *power_tune_table = - (const Vega10_PPTable_Generic_SubTable_Header *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usPowerTuneTableOffset)); - const ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table = - (const ATOM_Vega10_SOCCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset)); - const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = - (const ATOM_Vega10_GFXCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); - const ATOM_Vega10_DCEFCLK_Dependency_Table *dcefclk_dep_table = - (const ATOM_Vega10_DCEFCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset)); - const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table = - (const ATOM_Vega10_MCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); - const ATOM_Vega10_Hard_Limit_Table *hard_limits = - (const ATOM_Vega10_Hard_Limit_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usHardLimitTableOffset)); - const Vega10_PPTable_Generic_SubTable_Header *pcie_table = - (const Vega10_PPTable_Generic_SubTable_Header *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usPCIETableOffset)); - const ATOM_Vega10_PIXCLK_Dependency_Table *pixclk_dep_table = - (const ATOM_Vega10_PIXCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset)); - const ATOM_Vega10_PHYCLK_Dependency_Table *phyclk_dep_table = - (const ATOM_Vega10_PHYCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset)); - const ATOM_Vega10_DISPCLK_Dependency_Table *dispclk_dep_table = - (const ATOM_Vega10_DISPCLK_Dependency_Table *) - (((unsigned long) powerplay_table) + - le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset)); - - pp_table_info->vdd_dep_on_socclk = NULL; - pp_table_info->vdd_dep_on_sclk = NULL; - pp_table_info->vdd_dep_on_mclk = NULL; - pp_table_info->vdd_dep_on_dcefclk = NULL; - pp_table_info->mm_dep_table = NULL; - pp_table_info->tdp_table = NULL; - pp_table_info->vdd_dep_on_pixclk = NULL; - pp_table_info->vdd_dep_on_phyclk = NULL; - pp_table_info->vdd_dep_on_dispclk = NULL; - - if (powerplay_table->usMMDependencyTableOffset) - result = get_mm_clock_voltage_table(hwmgr, - &pp_table_info->mm_dep_table, - mm_dependency_table); - - if (!result && powerplay_table->usPowerTuneTableOffset) - result = get_tdp_table(hwmgr, - &pp_table_info->tdp_table, - power_tune_table); - - if (!result && powerplay_table->usSocclkDependencyTableOffset) - result = get_socclk_voltage_dependency_table(hwmgr, - &pp_table_info->vdd_dep_on_socclk, - socclk_dep_table); - - if (!result && powerplay_table->usGfxclkDependencyTableOffset) - result = get_gfxclk_voltage_dependency_table(hwmgr, - &pp_table_info->vdd_dep_on_sclk, - gfxclk_dep_table); - - if (!result && powerplay_table->usPixclkDependencyTableOffset) - result = get_pix_clk_voltage_dependency_table(hwmgr, - &pp_table_info->vdd_dep_on_pixclk, - (const ATOM_Vega10_PIXCLK_Dependency_Table*) - pixclk_dep_table); - - if (!result && powerplay_table->usPhyClkDependencyTableOffset) - result = get_pix_clk_voltage_dependency_table(hwmgr, - &pp_table_info->vdd_dep_on_phyclk, - (const ATOM_Vega10_PIXCLK_Dependency_Table *) - phyclk_dep_table); - - if (!result && powerplay_table->usDispClkDependencyTableOffset) - result = get_pix_clk_voltage_dependency_table(hwmgr, - &pp_table_info->vdd_dep_on_dispclk, - (const ATOM_Vega10_PIXCLK_Dependency_Table *) - dispclk_dep_table); - - if (!result && powerplay_table->usDcefclkDependencyTableOffset) - result = get_dcefclk_voltage_dependency_table(hwmgr, - &pp_table_info->vdd_dep_on_dcefclk, - dcefclk_dep_table); - - if (!result && powerplay_table->usMclkDependencyTableOffset) - result = get_mclk_voltage_dependency_table(hwmgr, - &pp_table_info->vdd_dep_on_mclk, - mclk_dep_table); - - if (!result && powerplay_table->usPCIETableOffset) - result = get_pcie_table(hwmgr, - &pp_table_info->pcie_table, - pcie_table); - - if (!result && powerplay_table->usHardLimitTableOffset) - result = get_hard_limits(hwmgr, - &pp_table_info->max_clock_voltage_on_dc, - hard_limits); - - hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = - pp_table_info->max_clock_voltage_on_dc.sclk; - hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = - pp_table_info->max_clock_voltage_on_dc.mclk; - hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = - pp_table_info->max_clock_voltage_on_dc.vddc; - hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = - pp_table_info->max_clock_voltage_on_dc.vddci; - - if (!result && - pp_table_info->vdd_dep_on_socclk && - pp_table_info->vdd_dep_on_socclk->count) - result = get_valid_clk(hwmgr, - &pp_table_info->valid_socclk_values, - pp_table_info->vdd_dep_on_socclk); - - if (!result && - pp_table_info->vdd_dep_on_sclk && - pp_table_info->vdd_dep_on_sclk->count) - result = get_valid_clk(hwmgr, - &pp_table_info->valid_sclk_values, - pp_table_info->vdd_dep_on_sclk); - - if (!result && - pp_table_info->vdd_dep_on_dcefclk && - pp_table_info->vdd_dep_on_dcefclk->count) - result = get_valid_clk(hwmgr, - &pp_table_info->valid_dcefclk_values, - pp_table_info->vdd_dep_on_dcefclk); - - if (!result && - pp_table_info->vdd_dep_on_mclk && - pp_table_info->vdd_dep_on_mclk->count) - result = get_valid_clk(hwmgr, - &pp_table_info->valid_mclk_values, - pp_table_info->vdd_dep_on_mclk); - - return result; -} - -static int get_vddc_lookup_table( - struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table **lookup_table, - const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables, - uint32_t max_levels) -{ - uint32_t table_size, i; - phm_ppt_v1_voltage_lookup_table *table; - - PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0), - "Invalid SOC_VDDD Lookup Table!", return 1); - - table_size = sizeof(uint32_t) + - sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels; - - table = kzalloc(table_size, GFP_KERNEL); - - if (table == NULL) - return -ENOMEM; - - table->count = vddc_lookup_pp_tables->ucNumEntries; - - for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) - table->entries[i].us_vdd = - le16_to_cpu(vddc_lookup_pp_tables->entries[i].usVdd); - - *lookup_table = table; - - return 0; -} - -static int init_dpm_2_parameters( - struct pp_hwmgr *hwmgr, - const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) -{ - int result = 0; - struct phm_ppt_v2_information *pp_table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - uint32_t disable_power_control = 0; - - pp_table_info->us_ulv_voltage_offset = - le16_to_cpu(powerplay_table->usUlvVoltageOffset); - - pp_table_info->us_ulv_smnclk_did = - le16_to_cpu(powerplay_table->usUlvSmnclkDid); - pp_table_info->us_ulv_mp1clk_did = - le16_to_cpu(powerplay_table->usUlvMp1clkDid); - pp_table_info->us_ulv_gfxclk_bypass = - le16_to_cpu(powerplay_table->usUlvGfxclkBypass); - pp_table_info->us_gfxclk_slew_rate = - le16_to_cpu(powerplay_table->usGfxclkSlewRate); - pp_table_info->uc_gfx_dpm_voltage_mode = - le16_to_cpu(powerplay_table->ucGfxVoltageMode); - pp_table_info->uc_soc_dpm_voltage_mode = - le16_to_cpu(powerplay_table->ucSocVoltageMode); - pp_table_info->uc_uclk_dpm_voltage_mode = - le16_to_cpu(powerplay_table->ucUclkVoltageMode); - pp_table_info->uc_uvd_dpm_voltage_mode = - le16_to_cpu(powerplay_table->ucUvdVoltageMode); - pp_table_info->uc_vce_dpm_voltage_mode = - le16_to_cpu(powerplay_table->ucVceVoltageMode); - pp_table_info->uc_mp0_dpm_voltage_mode = - le16_to_cpu(powerplay_table->ucMp0VoltageMode); - pp_table_info->uc_dcef_dpm_voltage_mode = - le16_to_cpu(powerplay_table->ucDcefVoltageMode); - - pp_table_info->ppm_parameter_table = NULL; - pp_table_info->vddc_lookup_table = NULL; - pp_table_info->vddmem_lookup_table = NULL; - pp_table_info->vddci_lookup_table = NULL; - - /* TDP limits */ - hwmgr->platform_descriptor.TDPODLimit = - le16_to_cpu(powerplay_table->usPowerControlLimit); - hwmgr->platform_descriptor.TDPAdjustment = 0; - hwmgr->platform_descriptor.VidAdjustment = 0; - hwmgr->platform_descriptor.VidAdjustmentPolarity = 0; - hwmgr->platform_descriptor.VidMinLimit = 0; - hwmgr->platform_descriptor.VidMaxLimit = 1500000; - hwmgr->platform_descriptor.VidStep = 6250; - - disable_power_control = 0; - if (!disable_power_control) { - /* enable TDP overdrive (PowerControl) feature as well if supported */ - if (hwmgr->platform_descriptor.TDPODLimit) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerControl); - } - - if (powerplay_table->usVddcLookupTableOffset) { - const ATOM_Vega10_Voltage_Lookup_Table *vddc_table = - (ATOM_Vega10_Voltage_Lookup_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usVddcLookupTableOffset)); - result = get_vddc_lookup_table(hwmgr, - &pp_table_info->vddc_lookup_table, vddc_table, 8); - } - - if (powerplay_table->usVddmemLookupTableOffset) { - const ATOM_Vega10_Voltage_Lookup_Table *vdd_mem_table = - (ATOM_Vega10_Voltage_Lookup_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usVddmemLookupTableOffset)); - result = get_vddc_lookup_table(hwmgr, - &pp_table_info->vddmem_lookup_table, vdd_mem_table, 4); - } - - if (powerplay_table->usVddciLookupTableOffset) { - const ATOM_Vega10_Voltage_Lookup_Table *vddci_table = - (ATOM_Vega10_Voltage_Lookup_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usVddciLookupTableOffset)); - result = get_vddc_lookup_table(hwmgr, - &pp_table_info->vddci_lookup_table, vddci_table, 4); - } - - return result; -} - -int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr) -{ - int result = 0; - const ATOM_Vega10_POWERPLAYTABLE *powerplay_table; - - hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL); - - PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), - "Failed to allocate hwmgr->pptable!", return -ENOMEM); - - powerplay_table = get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE((powerplay_table != NULL), - "Missing PowerPlay Table!", return -1); - - result = check_powerplay_tables(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "check_powerplay_tables failed", return result); - - result = set_platform_caps(hwmgr, - le32_to_cpu(powerplay_table->ulPlatformCaps)); - - PP_ASSERT_WITH_CODE((result == 0), - "set_platform_caps failed", return result); - - result = init_thermal_controller(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_thermal_controller failed", return result); - - result = init_over_drive_limits(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_over_drive_limits failed", return result); - - result = init_powerplay_extended_tables(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_powerplay_extended_tables failed", return result); - - result = init_dpm_2_parameters(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "init_dpm_2_parameters failed", return result); - - return result; -} - -static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v2_information *pp_table_info = - (struct phm_ppt_v2_information *)(hwmgr->pptable); - - kfree(pp_table_info->vdd_dep_on_sclk); - pp_table_info->vdd_dep_on_sclk = NULL; - - kfree(pp_table_info->vdd_dep_on_mclk); - pp_table_info->vdd_dep_on_mclk = NULL; - - kfree(pp_table_info->valid_mclk_values); - pp_table_info->valid_mclk_values = NULL; - - kfree(pp_table_info->valid_sclk_values); - pp_table_info->valid_sclk_values = NULL; - - kfree(pp_table_info->vddc_lookup_table); - pp_table_info->vddc_lookup_table = NULL; - - kfree(pp_table_info->vddmem_lookup_table); - pp_table_info->vddmem_lookup_table = NULL; - - kfree(pp_table_info->vddci_lookup_table); - pp_table_info->vddci_lookup_table = NULL; - - kfree(pp_table_info->ppm_parameter_table); - pp_table_info->ppm_parameter_table = NULL; - - kfree(pp_table_info->mm_dep_table); - pp_table_info->mm_dep_table = NULL; - - kfree(pp_table_info->cac_dtp_table); - pp_table_info->cac_dtp_table = NULL; - - kfree(hwmgr->dyn_state.cac_dtp_table); - hwmgr->dyn_state.cac_dtp_table = NULL; - - kfree(pp_table_info->tdp_table); - pp_table_info->tdp_table = NULL; - - kfree(hwmgr->pptable); - hwmgr->pptable = NULL; - - return 0; -} - -const struct pp_table_func vega10_pptable_funcs = { - .pptable_init = vega10_pp_tables_initialize, - .pptable_fini = vega10_pp_tables_uninitialize, -}; - -int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) -{ - const ATOM_Vega10_State_Array *state_arrays; - const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE((pp_table != NULL), - "Missing PowerPlay Table!", return -1); - PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >= - ATOM_Vega10_TABLE_REVISION_VEGA10), - "Incorrect PowerPlay table revision!", return -1); - - state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)pp_table) + - le16_to_cpu(pp_table->usStateArrayOffset)); - - return (uint32_t)(state_arrays->ucNumEntries); -} - -static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, - uint16_t classification, uint16_t classification2) -{ - uint32_t result = 0; - - if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT) - result |= PP_StateClassificationFlag_Boot; - - if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL) - result |= PP_StateClassificationFlag_Thermal; - - if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) - result |= PP_StateClassificationFlag_LimitedPowerSource; - - if (classification & ATOM_PPLIB_CLASSIFICATION_REST) - result |= PP_StateClassificationFlag_Rest; - - if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED) - result |= PP_StateClassificationFlag_Forced; - - if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI) - result |= PP_StateClassificationFlag_ACPI; - - if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) - result |= PP_StateClassificationFlag_LimitedPowerSource_2; - - return result; -} - -int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, - uint32_t entry_index, struct pp_power_state *power_state, - int (*call_back_func)(struct pp_hwmgr *, void *, - struct pp_power_state *, void *, uint32_t)) -{ - int result = 0; - const ATOM_Vega10_State_Array *state_arrays; - const ATOM_Vega10_State *state_entry; - const ATOM_Vega10_POWERPLAYTABLE *pp_table = - get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!", - return -1;); - power_state->classification.bios_index = entry_index; - - if (pp_table->sHeader.format_revision >= - ATOM_Vega10_TABLE_REVISION_VEGA10) { - state_arrays = (ATOM_Vega10_State_Array *) - (((unsigned long)pp_table) + - le16_to_cpu(pp_table->usStateArrayOffset)); - - PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0, - "Invalid PowerPlay Table State Array Offset.", - return -1); - PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, - "Invalid PowerPlay Table State Array.", - return -1); - PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), - "Invalid PowerPlay Table State Array Entry.", - return -1); - - state_entry = &(state_arrays->states[entry_index]); - - result = call_back_func(hwmgr, (void *)state_entry, power_state, - (void *)pp_table, - make_classification_flags(hwmgr, - le16_to_cpu(state_entry->usClassification), - le16_to_cpu(state_entry->usClassification2))); - } - - if (!result && (power_state->classification.flags & - PP_StateClassificationFlag_Boot)) - result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); - - return result; -} - -int vega10_baco_set_cap(struct pp_hwmgr *hwmgr) -{ - int result = 0; - - const ATOM_Vega10_POWERPLAYTABLE *powerplay_table; - - powerplay_table = get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE((powerplay_table != NULL), - "Missing PowerPlay Table!", return -1); - - result = check_powerplay_tables(hwmgr, powerplay_table); - - PP_ASSERT_WITH_CODE((result == 0), - "check_powerplay_tables failed", return result); - - set_hw_cap( - hwmgr, - 0 != (le32_to_cpu(powerplay_table->ulPlatformCaps) & ATOM_VEGA10_PP_PLATFORM_CAP_BACO), - PHM_PlatformCaps_BACO); - return result; -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h deleted file mode 100644 index da5fbec9b0cd..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA10_PROCESSPPTABLES_H -#define VEGA10_PROCESSPPTABLES_H - -#include "hwmgr.h" - -enum Vega10_I2CLineID { - Vega10_I2CLineID_DDC1 = 0x90, - Vega10_I2CLineID_DDC2 = 0x91, - Vega10_I2CLineID_DDC3 = 0x92, - Vega10_I2CLineID_DDC4 = 0x93, - Vega10_I2CLineID_DDC5 = 0x94, - Vega10_I2CLineID_DDC6 = 0x95, - Vega10_I2CLineID_SCLSDA = 0x96, - Vega10_I2CLineID_DDCVGA = 0x97 -}; - -#define Vega10_I2C_DDC1DATA 0 -#define Vega10_I2C_DDC1CLK 1 -#define Vega10_I2C_DDC2DATA 2 -#define Vega10_I2C_DDC2CLK 3 -#define Vega10_I2C_DDC3DATA 4 -#define Vega10_I2C_DDC3CLK 5 -#define Vega10_I2C_SDA 40 -#define Vega10_I2C_SCL 41 -#define Vega10_I2C_DDC4DATA 65 -#define Vega10_I2C_DDC4CLK 66 -#define Vega10_I2C_DDC5DATA 0x48 -#define Vega10_I2C_DDC5CLK 0x49 -#define Vega10_I2C_DDC6DATA 0x4a -#define Vega10_I2C_DDC6CLK 0x4b -#define Vega10_I2C_DDCVGADATA 0x4c -#define Vega10_I2C_DDCVGACLK 0x4d - -extern const struct pp_table_func vega10_pptable_funcs; -extern int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr); -extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index, - struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *, - struct pp_power_state *, void *, uint32_t)); -extern int vega10_baco_set_cap(struct pp_hwmgr *hwmgr); -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c deleted file mode 100644 index 468bdd6f6697..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +++ /dev/null @@ -1,657 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "vega10_thermal.h" -#include "vega10_hwmgr.h" -#include "vega10_smumgr.h" -#include "vega10_ppsmc.h" -#include "vega10_inc.h" -#include "soc15_common.h" -#include "pp_debug.h" - -static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) -{ - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm); - return 0; -} - -int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info) -{ - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - fan_speed_info->supports_percent_read = true; - fan_speed_info->supports_percent_write = true; - fan_speed_info->min_percent = 0; - fan_speed_info->max_percent = 100; - - if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && - hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution) { - fan_speed_info->supports_rpm_read = true; - fan_speed_info->supports_rpm_write = true; - fan_speed_info->min_rpm = - hwmgr->thermal_controller.fanInfo.ulMinRPM; - fan_speed_info->max_rpm = - hwmgr->thermal_controller.fanInfo.ulMaxRPM; - } else { - fan_speed_info->min_rpm = 0; - fan_speed_info->max_rpm = 0; - } - - return 0; -} - -int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t *speed) -{ - uint32_t current_rpm; - uint32_t percent = 0; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - if (vega10_get_current_rpm(hwmgr, ¤t_rpm)) - return -1; - - if (hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanRPM != 0) - percent = current_rpm * 100 / - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanRPM; - - *speed = percent > 100 ? 100 : percent; - - return 0; -} - -int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) -{ - struct amdgpu_device *adev = hwmgr->adev; - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t tach_period; - uint32_t crystal_clock_freq; - int result = 0; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return -1; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - result = vega10_get_current_rpm(hwmgr, speed); - } else { - tach_period = - REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), - CG_TACH_STATUS, - TACH_PERIOD); - - if (tach_period == 0) - return -EINVAL; - - crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); - - *speed = 60 * crystal_clock_freq * 10000 / tach_period; - } - - return result; -} - -/** -* Set Fan Speed Control to static mode, -* so that the user can decide what speed to use. -* @param hwmgr the address of the powerplay hardware manager. -* mode the fan control mode, 0 default, 1 by percent, 5, by RPM -* @exception Should always succeed. -*/ -int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - struct amdgpu_device *adev = hwmgr->adev; - - if (hwmgr->fan_ctrl_is_in_default_mode) { - hwmgr->fan_ctrl_default_mode = - REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, FDO_PWM_MODE); - hwmgr->tmin = - REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, TMIN); - hwmgr->fan_ctrl_is_in_default_mode = false; - } - - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, TMIN, 0)); - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, FDO_PWM_MODE, mode)); - - return 0; -} - -/** -* Reset Fan Speed Control to default mode. -* @param hwmgr the address of the powerplay hardware manager. -* @exception Should always succeed. -*/ -int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - if (!hwmgr->fan_ctrl_is_in_default_mode) { - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, FDO_PWM_MODE, - hwmgr->fan_ctrl_default_mode)); - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, TMIN, - hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT)); - hwmgr->fan_ctrl_is_in_default_mode = true; - } - - return 0; -} - -/** - * @fn vega10_enable_fan_control_feature - * @brief Enables the SMC Fan Control Feature. - * - * @param hwmgr - the address of the powerplay hardware manager. - * @return 0 on success. -1 otherwise. - */ -static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( - hwmgr, true, - data->smu_features[GNLD_FAN_CONTROL]. - smu_feature_bitmap), - "Attempt to Enable FAN CONTROL feature Failed!", - return -1); - data->smu_features[GNLD_FAN_CONTROL].enabled = true; - } - - return 0; -} - -static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( - hwmgr, false, - data->smu_features[GNLD_FAN_CONTROL]. - smu_feature_bitmap), - "Attempt to Enable FAN CONTROL feature Failed!", - return -1); - data->smu_features[GNLD_FAN_CONTROL].enabled = false; - } - - return 0; -} - -int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return -1; - - PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr), - "Attempt to Enable SMC FAN CONTROL Feature Failed!", - return -1); - - return 0; -} - - -int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return -1; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr), - "Attempt to Disable SMC FAN CONTROL Feature Failed!", - return -1); - } - return 0; -} - -/** -* Set Fan Speed in percent. -* @param hwmgr the address of the powerplay hardware manager. -* @param speed is the percentage value (0% - 100%) to be set. -* @exception Fails is the 100% setting appears to be 0. -*/ -int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t speed) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t duty100; - uint32_t duty; - uint64_t tmp64; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - if (speed > 100) - speed = 100; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega10_fan_ctrl_stop_smc_fan_control(hwmgr); - - duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), - CG_FDO_CTRL1, FMAX_DUTY100); - - if (duty100 == 0) - return -EINVAL; - - tmp64 = (uint64_t)speed * duty100; - do_div(tmp64, 100); - duty = (uint32_t)tmp64; - - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), - CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); - - return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); -} - -/** -* Reset Fan Speed to default. -* @param hwmgr the address of the powerplay hardware manager. -* @exception Always succeeds. -*/ -int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - return vega10_fan_ctrl_start_smc_fan_control(hwmgr); - else - return vega10_fan_ctrl_set_default_mode(hwmgr); -} - -/** -* Set Fan Speed in RPM. -* @param hwmgr the address of the powerplay hardware manager. -* @param speed is the percentage value (min - max) to be set. -* @exception Fails is the speed not lie between min and max. -*/ -int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t tach_period; - uint32_t crystal_clock_freq; - int result = 0; - - if (hwmgr->thermal_controller.fanInfo.bNoFan || - speed == 0 || - (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || - (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) - return -1; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr); - - if (!result) { - crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); - tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); - WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), - CG_TACH_CTRL, TARGET_PERIOD, - tach_period)); - } - return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM); -} - -/** -* Reads the remote temperature from the SIslands thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int temp; - - temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); - - temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> - CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; - - temp = temp & 0x1ff; - - temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return temp; -} - -/** -* Set the requested temperature range for high and low alert signals -* -* @param hwmgr The address of the hardware manager. -* @param range Temperature range to be programmed for -* high and low alert signals -* @exception PP_Result_BadInput if the input data is not valid. -*/ -static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range) -{ - struct amdgpu_device *adev = hwmgr->adev; - int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - uint32_t val; - - if (low < range->min) - low = range->min; - if (high > range->max) - high = range->max; - - if (low > high) - return -EINVAL; - - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); - - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) & - (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) & - (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); - - return 0; -} - -/** -* Programs thermal controller one-time setting registers -* -* @param hwmgr The address of the hardware manager. -*/ -static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { - WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), - CG_TACH_CTRL, EDGE_PER_REV, - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1)); - } - - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28)); - - return 0; -} - -/** -* Enable thermal alerts on the RV770 thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - struct vega10_hwmgr *data = hwmgr->backend; - uint32_t val = 0; - - if (data->smu_features[GNLD_FW_CTF].supported) { - if (data->smu_features[GNLD_FW_CTF].enabled) - printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n"); - - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - true, - data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), - "Attempt to Enable FW CTF feature Failed!", - return -1); - data->smu_features[GNLD_FW_CTF].enabled = true; - } - - val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); - val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); - val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); - - return 0; -} - -/** -* Disable thermal alerts on the RV770 thermal controller. -* @param hwmgr The address of the hardware manager. -*/ -int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - struct vega10_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_FW_CTF].supported) { - if (!data->smu_features[GNLD_FW_CTF].enabled) - printk("[Thermal_EnableAlert] FW CTF Already disabled!\n"); - - - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, - false, - data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), - "Attempt to disable FW CTF feature Failed!", - return -1); - data->smu_features[GNLD_FW_CTF].enabled = false; - } - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); - - return 0; -} - -/** -* Uninitialize the thermal controller. -* Currently just disables alerts. -* @param hwmgr The address of the hardware manager. -*/ -int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) -{ - int result = vega10_thermal_disable_alert(hwmgr); - - if (!hwmgr->thermal_controller.fanInfo.bNoFan) - vega10_fan_ctrl_set_default_mode(hwmgr); - - return result; -} - -/** -* Set up the fan table to control the fan using the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) -{ - int ret; - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *table = &(data->smc_state_table.pp_table); - - if (!data->smu_features[GNLD_FAN_CONTROL].supported) - return 0; - - table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanRPM; - table->FanThrottlingRpm = hwmgr->thermal_controller. - advanceFanControlParameters.usFanRPMMaxLimit; - table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller. - advanceFanControlParameters.ulMinFanSCLKAcousticLimit); - table->FanTargetTemperature = hwmgr->thermal_controller. - advanceFanControlParameters.usTMax; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFanTemperatureTarget, - (uint32_t)table->FanTargetTemperature, - NULL); - - table->FanPwmMin = hwmgr->thermal_controller. - advanceFanControlParameters.usPWMMin * 255 / 100; - table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller. - advanceFanControlParameters.ulTargetGfxClk); - table->FanGainEdge = hwmgr->thermal_controller. - advanceFanControlParameters.usFanGainEdge; - table->FanGainHotspot = hwmgr->thermal_controller. - advanceFanControlParameters.usFanGainHotspot; - table->FanGainLiquid = hwmgr->thermal_controller. - advanceFanControlParameters.usFanGainLiquid; - table->FanGainVrVddc = hwmgr->thermal_controller. - advanceFanControlParameters.usFanGainVrVddc; - table->FanGainVrMvdd = hwmgr->thermal_controller. - advanceFanControlParameters.usFanGainVrMvdd; - table->FanGainPlx = hwmgr->thermal_controller. - advanceFanControlParameters.usFanGainPlx; - table->FanGainHbm = hwmgr->thermal_controller. - advanceFanControlParameters.usFanGainHbm; - table->FanZeroRpmEnable = hwmgr->thermal_controller. - advanceFanControlParameters.ucEnableZeroRPM; - table->FanStopTemp = hwmgr->thermal_controller. - advanceFanControlParameters.usZeroRPMStopTemperature; - table->FanStartTemp = hwmgr->thermal_controller. - advanceFanControlParameters.usZeroRPMStartTemperature; - - ret = smum_smc_table_manager(hwmgr, - (uint8_t *)(&(data->smc_state_table.pp_table)), - PPTABLE, false); - if (ret) - pr_info("Failed to update Fan Control Table in PPTable!"); - - return ret; -} - -int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr) -{ - struct vega10_hwmgr *data = hwmgr->backend; - PPTable_t *table = &(data->smc_state_table.pp_table); - int ret; - - if (!data->smu_features[GNLD_FAN_CONTROL].supported) - return 0; - - if (!hwmgr->thermal_controller.advanceFanControlParameters. - usMGpuThrottlingRPMLimit) - return 0; - - table->FanThrottlingRpm = hwmgr->thermal_controller. - advanceFanControlParameters.usMGpuThrottlingRPMLimit; - - ret = smum_smc_table_manager(hwmgr, - (uint8_t *)(&(data->smc_state_table.pp_table)), - PPTABLE, false); - if (ret) { - pr_info("Failed to update fan control table in pptable!"); - return ret; - } - - ret = vega10_disable_fan_control_feature(hwmgr); - if (ret) { - pr_info("Attempt to disable SMC fan control feature failed!"); - return ret; - } - - ret = vega10_enable_fan_control_feature(hwmgr); - if (ret) - pr_info("Attempt to enable SMC fan control feature failed!"); - - return ret; -} - -/** -* Start the fan control on the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ -/* If the fantable setup has failed we could have disabled - * PHM_PlatformCaps_MicrocodeFanControl even after - * this function was included in the table. - * Make sure that we still think controlling the fan is OK. -*/ - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega10_fan_ctrl_start_smc_fan_control(hwmgr); - - return 0; -} - - -int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range) -{ - int ret = 0; - - if (range == NULL) - return -EINVAL; - - vega10_thermal_initialize(hwmgr); - ret = vega10_thermal_set_temperature_range(hwmgr, range); - if (ret) - return -EINVAL; - - vega10_thermal_enable_alert(hwmgr); -/* We should restrict performance levels to low before we halt the SMC. - * On the other hand we are still in boot state when we do this - * so it would be pointless. - * If this assumption changes we have to revisit this table. - */ - ret = vega10_thermal_setup_fan_table(hwmgr); - if (ret) - return -EINVAL; - - vega10_thermal_start_smc_fan_control(hwmgr); - - return 0; -}; - - - - -int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr->thermal_controller.fanInfo.bNoFan) { - vega10_fan_ctrl_set_default_mode(hwmgr); - vega10_fan_ctrl_stop_smc_fan_control(hwmgr); - } - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h deleted file mode 100644 index 4a0ede7c1f07..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA10_THERMAL_H -#define VEGA10_THERMAL_H - -#include "hwmgr.h" - -struct vega10_temperature { - uint16_t edge_temp; - uint16_t hot_spot_temp; - uint16_t hbm_temp; - uint16_t vr_soc_temp; - uint16_t vr_mem_temp; - uint16_t liquid1_temp; - uint16_t liquid2_temp; - uint16_t plx_temp; -}; - -#define VEGA10_THERMAL_HIGH_ALERT_MASK 0x1 -#define VEGA10_THERMAL_LOW_ALERT_MASK 0x2 - -#define VEGA10_THERMAL_MINIMUM_TEMP_READING -256 -#define VEGA10_THERMAL_MAXIMUM_TEMP_READING 255 - -#define VEGA10_THERMAL_MINIMUM_ALERT_TEMP 0 -#define VEGA10_THERMAL_MAXIMUM_ALERT_TEMP 255 - -#define FDO_PWM_MODE_STATIC 1 -#define FDO_PWM_MODE_STATIC_RPM 5 - - -extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr); -extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); -extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info); -extern int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t *speed); -extern int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); -extern int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, - uint32_t mode); -extern int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t speed); -extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); -extern int vega10_thermal_ctrl_uninitialize_thermal_controller( - struct pp_hwmgr *hwmgr); -extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, - uint32_t speed); -extern int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, - uint32_t *speed); -extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr); -extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range); -extern int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr); - - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c deleted file mode 100644 index bc53cce4f32d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "soc15.h" -#include "soc15_hw_ip.h" -#include "vega10_ip_offset.h" -#include "soc15_common.h" -#include "vega12_inc.h" -#include "vega12_ppsmc.h" -#include "vega12_baco.h" - -static const struct soc15_baco_cmd_entry pre_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmBIF_DOORBELL_CNTL_BASE_IDX, mmBIF_DOORBELL_CNTL, BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK, BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT, 0, 0 }, - { CMD_WRITE, NBIF_HWID, 0, mmBIF_FB_EN_BASE_IDX, mmBIF_FB_EN, 0, 0, 0, 0 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_DSTATE_BYPASS_MASK, BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_RST_INTR_MASK_MASK, BACO_CNTL__BACO_RST_INTR_MASK__SHIFT, 0, 1 } -}; - -static const struct soc15_baco_cmd_entry enter_baco_tbl[] = -{ - { CMD_WAITFOR, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK, THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT, 0xffffffff, 0x80000000 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 1 }, - { CMD_DELAY_MS, 0, 0, 0, 5, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 0 }, - { CMD_WAITFOR, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MODE__SHIFT, 0xffffffff, 0x100 } -}; - -static const struct soc15_baco_cmd_entry exit_baco_tbl[] = -{ - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0 }, - { CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 10, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_EXIT_MASK, THM_BACO_CNTL__BACO_EXIT__SHIFT, 0, 1 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0 }, - { CMD_WAITFOR, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffffff, 0 }, - { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK, THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 0 }, - { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0 }, - { CMD_WAITFOR, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0 } -}; - -static const struct soc15_baco_cmd_entry clean_baco_tbl[] = -{ - { CMD_WRITE, NBIF_HWID, 0, mmBIOS_SCRATCH_6_BASE_IDX, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, - { CMD_WRITE, NBIF_HWID, 0, mmBIOS_SCRATCH_7_BASE_IDX, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } -}; - -int vega12_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - enum BACO_STATE cur_state; - - smu9_baco_get_state(hwmgr, &cur_state); - - if (cur_state == state) - /* aisc already in the target state */ - return 0; - - if (state == BACO_STATE_IN) { - if (soc15_baco_program_registers(hwmgr, pre_baco_tbl, - ARRAY_SIZE(pre_baco_tbl))) { - if (smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0, NULL)) - return -EINVAL; - - if (soc15_baco_program_registers(hwmgr, enter_baco_tbl, - ARRAY_SIZE(enter_baco_tbl))) - return 0; - } - } else if (state == BACO_STATE_OUT) { - /* HW requires at least 20ms between regulator off and on */ - msleep(20); - /* Execute Hardware BACO exit sequence */ - if (soc15_baco_program_registers(hwmgr, exit_baco_tbl, - ARRAY_SIZE(exit_baco_tbl))) { - if (soc15_baco_program_registers(hwmgr, clean_baco_tbl, - ARRAY_SIZE(clean_baco_tbl))) - return 0; - } - } - - return -EINVAL; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h deleted file mode 100644 index 57b72e5a95ae..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __VEGA12_BACO_H__ -#define __VEGA12_BACO_H__ -#include "smu9_baco.h" - -extern int vega12_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c deleted file mode 100644 index f0680dd58508..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +++ /dev/null @@ -1,2868 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/module.h> -#include <linux/slab.h> - -#include "hwmgr.h" -#include "amd_powerplay.h" -#include "vega12_smumgr.h" -#include "hardwaremanager.h" -#include "ppatomfwctrl.h" -#include "atomfirmware.h" -#include "cgs_common.h" -#include "vega12_inc.h" -#include "pppcielanes.h" -#include "vega12_hwmgr.h" -#include "vega12_processpptables.h" -#include "vega12_pptable.h" -#include "vega12_thermal.h" -#include "vega12_ppsmc.h" -#include "pp_debug.h" -#include "amd_pcie_helpers.h" -#include "ppinterrupt.h" -#include "pp_overdriver.h" -#include "pp_thermal.h" -#include "vega12_baco.h" - -#define smnPCIE_LC_SPEED_CNTL 0x11140290 -#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 - -#define LINK_WIDTH_MAX 6 -#define LINK_SPEED_MAX 3 -static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; -static int link_speed[] = {25, 50, 80, 160}; - -static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask); -static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, - uint32_t *clock, - PPCLK_e clock_select, - bool max); - -static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - - data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT; - data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT; - data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT; - data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT; - data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT; - - data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT; - data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; - - data->registry_data.disallowed_features = 0x0; - data->registry_data.od_state_in_dc_support = 0; - data->registry_data.thermal_support = 1; - data->registry_data.skip_baco_hardware = 0; - - data->registry_data.log_avfs_param = 0; - data->registry_data.sclk_throttle_low_notification = 1; - data->registry_data.force_dpm_high = 0; - data->registry_data.stable_pstate_sclk_dpm_percentage = 75; - - data->registry_data.didt_support = 0; - if (data->registry_data.didt_support) { - data->registry_data.didt_mode = 6; - data->registry_data.sq_ramping_support = 1; - data->registry_data.db_ramping_support = 0; - data->registry_data.td_ramping_support = 0; - data->registry_data.tcp_ramping_support = 0; - data->registry_data.dbr_ramping_support = 0; - data->registry_data.edc_didt_support = 1; - data->registry_data.gc_didt_support = 0; - data->registry_data.psm_didt_support = 0; - } - - data->registry_data.pcie_lane_override = 0xff; - data->registry_data.pcie_speed_override = 0xff; - data->registry_data.pcie_clock_override = 0xffffffff; - data->registry_data.regulator_hot_gpio_support = 1; - data->registry_data.ac_dc_switch_gpio_support = 0; - data->registry_data.quick_transition_support = 0; - data->registry_data.zrpm_start_temp = 0xffff; - data->registry_data.zrpm_stop_temp = 0xffff; - data->registry_data.odn_feature_enable = 1; - data->registry_data.disable_water_mark = 0; - data->registry_data.disable_pp_tuning = 0; - data->registry_data.disable_xlpp_tuning = 0; - data->registry_data.disable_workload_policy = 0; - data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; - data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; - data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; - data->registry_data.force_workload_policy_mask = 0; - data->registry_data.disable_3d_fs_detection = 0; - data->registry_data.fps_support = 1; - data->registry_data.disable_auto_wattman = 1; - data->registry_data.auto_wattman_debug = 0; - data->registry_data.auto_wattman_sample_period = 100; - data->registry_data.auto_wattman_threshold = 50; -} - -static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - struct amdgpu_device *adev = hwmgr->adev; - - if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableSMU7ThermalManagement); - - if (adev->pg_flags & AMD_PG_SUPPORT_UVD) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDynamicPowerGating); - } - - if (adev->pg_flags & AMD_PG_SUPPORT_VCE) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UnTabledHardwareInterface); - - if (data->registry_data.odn_feature_enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinACSupport); - else { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6inACSupport); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinACSupport); - } - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ActivityReporting); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM); - - if (data->registry_data.od_state_in_dc_support) { - if (data->registry_data.odn_feature_enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinDCSupport); - else { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6inDCSupport); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinDCSupport); - } - } - - if (data->registry_data.thermal_support - && data->registry_data.fuzzy_fan_control_support - && hwmgr->thermal_controller.advanceFanControlParameters.usTMax) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPowerManagement); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMC); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalPolicyDelay); - - if (data->registry_data.force_dpm_high) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ExclusiveModeAlwaysHigh); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicUVDState); - - if (data->registry_data.sclk_throttle_low_notification) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification); - - /* power tune caps */ - /* assume disabled */ - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtSupport); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtEDCEnable); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_GCEDC); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PSM); - - if (data->registry_data.didt_support) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); - if (data->registry_data.sq_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); - if (data->registry_data.db_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); - if (data->registry_data.td_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); - if (data->registry_data.tcp_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); - if (data->registry_data.dbr_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); - if (data->registry_data.edc_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); - if (data->registry_data.gc_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); - if (data->registry_data.psm_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); - } - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot); - - if (data->registry_data.ac_dc_switch_gpio_support) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); - } - - if (data->registry_data.quick_transition_support) { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_Falcon_QuickTransition); - } - - if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_LowestUclkReservedForUlv); - if (data->lowest_uclk_reserved_for_ulv == 1) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_LowestUclkReservedForUlv); - } - - if (data->registry_data.custom_fan_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CustomFanControlSupport); - - return 0; -} - -static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - struct amdgpu_device *adev = hwmgr->adev; - uint32_t top32, bottom32; - int i; - - data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = - FEATURE_DPM_PREFETCHER_BIT; - data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = - FEATURE_DPM_GFXCLK_BIT; - data->smu_features[GNLD_DPM_UCLK].smu_feature_id = - FEATURE_DPM_UCLK_BIT; - data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = - FEATURE_DPM_SOCCLK_BIT; - data->smu_features[GNLD_DPM_UVD].smu_feature_id = - FEATURE_DPM_UVD_BIT; - data->smu_features[GNLD_DPM_VCE].smu_feature_id = - FEATURE_DPM_VCE_BIT; - data->smu_features[GNLD_ULV].smu_feature_id = - FEATURE_ULV_BIT; - data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = - FEATURE_DPM_MP0CLK_BIT; - data->smu_features[GNLD_DPM_LINK].smu_feature_id = - FEATURE_DPM_LINK_BIT; - data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = - FEATURE_DPM_DCEFCLK_BIT; - data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = - FEATURE_DS_GFXCLK_BIT; - data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = - FEATURE_DS_SOCCLK_BIT; - data->smu_features[GNLD_DS_LCLK].smu_feature_id = - FEATURE_DS_LCLK_BIT; - data->smu_features[GNLD_PPT].smu_feature_id = - FEATURE_PPT_BIT; - data->smu_features[GNLD_TDC].smu_feature_id = - FEATURE_TDC_BIT; - data->smu_features[GNLD_THERMAL].smu_feature_id = - FEATURE_THERMAL_BIT; - data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = - FEATURE_GFX_PER_CU_CG_BIT; - data->smu_features[GNLD_RM].smu_feature_id = - FEATURE_RM_BIT; - data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = - FEATURE_DS_DCEFCLK_BIT; - data->smu_features[GNLD_ACDC].smu_feature_id = - FEATURE_ACDC_BIT; - data->smu_features[GNLD_VR0HOT].smu_feature_id = - FEATURE_VR0HOT_BIT; - data->smu_features[GNLD_VR1HOT].smu_feature_id = - FEATURE_VR1HOT_BIT; - data->smu_features[GNLD_FW_CTF].smu_feature_id = - FEATURE_FW_CTF_BIT; - data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = - FEATURE_LED_DISPLAY_BIT; - data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = - FEATURE_FAN_CONTROL_BIT; - data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; - data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; - data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; - data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; - - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - data->smu_features[i].smu_feature_bitmap = - (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); - data->smu_features[i].allowed = - ((data->registry_data.disallowed_features >> i) & 1) ? - false : true; - } - - /* Get the SN to turn into a Unique ID */ - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); - - adev->unique_id = ((uint64_t)bottom32 << 32) | top32; -} - -static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) -{ - return 0; -} - -static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) -{ - kfree(hwmgr->backend); - hwmgr->backend = NULL; - - return 0; -} - -static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) -{ - int result = 0; - struct vega12_hwmgr *data; - struct amdgpu_device *adev = hwmgr->adev; - - data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - - hwmgr->backend = data; - - vega12_set_default_registry_data(hwmgr); - - data->disable_dpm_mask = 0xff; - data->workload_mask = 0xff; - - /* need to set voltage control types before EVV patching */ - data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE; - data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE; - data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE; - - data->water_marks_bitmap = 0; - data->avfs_exist = false; - - vega12_set_features_platform_caps(hwmgr); - - vega12_init_dpm_defaults(hwmgr); - - /* Parse pptable data read from VBIOS */ - vega12_set_private_data_based_on_pptable(hwmgr); - - data->is_tlu_enabled = false; - - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = - VEGA12_MAX_HARDWARE_POWERLEVELS; - hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; - hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - - hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ - /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ - hwmgr->platform_descriptor.clockStep.engineClock = 500; - hwmgr->platform_descriptor.clockStep.memoryClock = 500; - - data->total_active_cus = adev->gfx.cu_info.number; - /* Setup default Overdrive Fan control settings */ - data->odn_fan_table.target_fan_speed = - hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; - data->odn_fan_table.target_temperature = - hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature; - data->odn_fan_table.min_performance_clock = - hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit; - data->odn_fan_table.min_fan_limit = - hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit * - hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; - - if (hwmgr->feature_mask & PP_GFXOFF_MASK) - data->gfxoff_controlled_by_driver = true; - else - data->gfxoff_controlled_by_driver = false; - - return result; -} - -static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - - data->low_sclk_interrupt_threshold = 0; - - return 0; -} - -static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr) -{ - PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), - "Failed to init sclk threshold!", - return -EINVAL); - - return 0; -} - -/* - * @fn vega12_init_dpm_state - * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. - * - * @param dpm_state - the address of the DPM Table to initiailize. - * @return None. - */ -static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state) -{ - dpm_state->soft_min_level = 0x0; - dpm_state->soft_max_level = 0xffff; - dpm_state->hard_min_level = 0x0; - dpm_state->hard_max_level = 0xffff; -} - -static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, - PPCLK_e clk_id, uint32_t *num_of_levels) -{ - int ret = 0; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmFreqByIndex, - (clk_id << 16 | 0xFF), - num_of_levels); - PP_ASSERT_WITH_CODE(!ret, - "[GetNumOfDpmLevel] failed to get dpm levels!", - return ret); - - return ret; -} - -static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, - PPCLK_e clkID, uint32_t index, uint32_t *clock) -{ - /* - *SMU expects the Clock ID to be in the top 16 bits. - *Lower 16 bits specify the level - */ - PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index), - clock) == 0, - "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!", - return -EINVAL); - - return 0; -} - -static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, - struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) -{ - int ret = 0; - uint32_t i, num_of_levels, clk; - - ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); - PP_ASSERT_WITH_CODE(!ret, - "[SetupSingleDpmTable] failed to get clk levels!", - return ret); - - dpm_table->count = num_of_levels; - - for (i = 0; i < num_of_levels; i++) { - ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); - PP_ASSERT_WITH_CODE(!ret, - "[SetupSingleDpmTable] failed to get clk of specific level!", - return ret); - dpm_table->dpm_levels[i].value = clk; - dpm_table->dpm_levels[i].enabled = true; - } - - return ret; -} - -/* - * This function is to initialize all DPM state tables - * for SMU based on the dependency table. - * Dynamic state patching function will then trim these - * state tables to the allowed range based - * on the power policy or external client requests, - * such as UVD request, etc. - */ -static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) -{ - - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - struct vega12_single_dpm_table *dpm_table; - int ret = 0; - - memset(&data->dpm_table, 0, sizeof(data->dpm_table)); - - /* socclk */ - dpm_table = &(data->dpm_table.soc_table); - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get socclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; - } - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* gfxclk */ - dpm_table = &(data->dpm_table.gfx_table); - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; - } - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* memclk */ - dpm_table = &(data->dpm_table.mem_table); - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get memclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; - } - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* eclk */ - dpm_table = &(data->dpm_table.eclk_table); - if (data->smu_features[GNLD_DPM_VCE].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get eclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; - } - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* vclk */ - dpm_table = &(data->dpm_table.vclk_table); - if (data->smu_features[GNLD_DPM_UVD].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get vclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; - } - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* dclk */ - dpm_table = &(data->dpm_table.dclk_table); - if (data->smu_features[GNLD_DPM_UVD].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get dclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; - } - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* dcefclk */ - dpm_table = &(data->dpm_table.dcef_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; - } - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* pixclk */ - dpm_table = &(data->dpm_table.pixel_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", - return ret); - } else - dpm_table->count = 0; - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* dispclk */ - dpm_table = &(data->dpm_table.display_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", - return ret); - } else - dpm_table->count = 0; - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* phyclk */ - dpm_table = &(data->dpm_table.phy_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", - return ret); - } else - dpm_table->count = 0; - vega12_init_dpm_state(&(dpm_table->dpm_state)); - - /* save a copy of the default DPM table */ - memcpy(&(data->golden_dpm_table), &(data->dpm_table), - sizeof(struct vega12_dpm_table)); - - return 0; -} - -#if 0 -static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); - uint32_t min_level; - - hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; - hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; - - /* Optimize compute power profile: Use only highest - * 2 power levels (if more than 2 are available) - */ - if (dpm_table->count > 2) - min_level = dpm_table->count - 2; - else if (dpm_table->count == 2) - min_level = 1; - else - min_level = 0; - - hwmgr->default_compute_power_profile.min_sclk = - dpm_table->dpm_levels[min_level].value; - - hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; - hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; - - return 0; -} -#endif - -/** -* Initializes the SMC table and uploads it -* -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data (PowerState) -* @return always 0 -*/ -static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) -{ - int result; - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct pp_atomfwctrl_bios_boot_up_values boot_up_values; - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - - result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); - if (!result) { - data->vbios_boot_state.vddc = boot_up_values.usVddc; - data->vbios_boot_state.vddci = boot_up_values.usVddci; - data->vbios_boot_state.mvddc = boot_up_values.usMvddc; - data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; - data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; - data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; - data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; - data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; - data->vbios_boot_state.eclock = boot_up_values.ulEClk; - data->vbios_boot_state.dclock = boot_up_values.ulDClk; - data->vbios_boot_state.vclock = boot_up_values.ulVClk; - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetMinDeepSleepDcefclk, - (uint32_t)(data->vbios_boot_state.dcef_clock / 100), - NULL); - } - - memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); - - result = smum_smc_table_manager(hwmgr, - (uint8_t *)pp_table, TABLE_PPTABLE, false); - PP_ASSERT_WITH_CODE(!result, - "Failed to upload PPtable!", return result); - - return 0; -} - -static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr) -{ - uint32_t result; - - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0, - "[Run_ACG_BTC] Attempt to run ACG BTC failed!", - return -EINVAL); - - PP_ASSERT_WITH_CODE(result == 1, - "Failed to run ACG BTC!", return -EINVAL); - - return 0; -} - -static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - int i; - uint32_t allowed_features_low = 0, allowed_features_high = 0; - - for (i = 0; i < GNLD_FEATURES_MAX; i++) - if (data->smu_features[i].allowed) - data->smu_features[i].smu_feature_id > 31 ? - (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) : - (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF)); - - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, - NULL) == 0, - "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!", - return -1); - - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, - NULL) == 0, - "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", - return -1); - - return 0; -} - -static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - - data->uvd_power_gated = true; - data->vce_power_gated = true; - - if (data->smu_features[GNLD_DPM_UVD].enabled) - data->uvd_power_gated = false; - - if (data->smu_features[GNLD_DPM_VCE].enabled) - data->vce_power_gated = false; -} - -static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - uint64_t features_enabled; - int i; - bool enabled; - - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0, - "[EnableAllSMUFeatures] Failed to enable all smu features!", - return -1); - - if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; - data->smu_features[i].enabled = enabled; - data->smu_features[i].supported = enabled; - } - } - - vega12_init_powergate_state(hwmgr); - - return 0; -} - -static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - uint64_t features_enabled; - int i; - bool enabled; - - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0, - "[DisableAllSMUFeatures] Failed to disable all smu features!", - return -1); - - if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; - data->smu_features[i].enabled = enabled; - data->smu_features[i].supported = enabled; - } - } - - return 0; -} - -static int vega12_odn_initialize_default_settings( - struct pp_hwmgr *hwmgr) -{ - return 0; -} - -static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, - uint32_t adjust_percent) -{ - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_OverDriveSetPercentage, adjust_percent, - NULL); -} - -static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr) -{ - int adjust_percent, result = 0; - - if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { - adjust_percent = - hwmgr->platform_descriptor.TDPAdjustmentPolarity ? - hwmgr->platform_descriptor.TDPAdjustment : - (-1 * hwmgr->platform_descriptor.TDPAdjustment); - result = vega12_set_overdrive_target_percentage(hwmgr, - (uint32_t)adjust_percent); - } - return result; -} - -static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, - PPCLK_e clkid, struct vega12_clock_range *clock) -{ - /* AC Max */ - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16), - &(clock->ACMax)) == 0, - "[GetClockRanges] Failed to get max ac clock from SMC!", - return -EINVAL); - - /* AC Min */ - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16), - &(clock->ACMin)) == 0, - "[GetClockRanges] Failed to get min ac clock from SMC!", - return -EINVAL); - - /* DC Max */ - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16), - &(clock->DCMax)) == 0, - "[GetClockRanges] Failed to get max dc clock from SMC!", - return -EINVAL); - - return 0; -} - -static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t i; - - for (i = 0; i < PPCLK_COUNT; i++) - PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr, - i, &(data->clk_range[i])), - "Failed to get clk range from SMC!", - return -EINVAL); - - return 0; -} - -static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, 0, NULL); - - result = vega12_set_allowed_featuresmask(hwmgr); - PP_ASSERT_WITH_CODE(result == 0, - "[EnableDPMTasks] Failed to set allowed featuresmask!\n", - return result); - - tmp_result = vega12_init_smc_table(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to initialize SMC table!", - result = tmp_result); - - tmp_result = vega12_run_acg_btc(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to run ACG BTC!", - result = tmp_result); - - result = vega12_enable_all_smu_features(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to enable all smu features!", - return result); - - tmp_result = vega12_power_control_set_level(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to power control set level!", - result = tmp_result); - - result = vega12_get_all_clock_ranges(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to get all clock ranges!", - return result); - - result = vega12_odn_initialize_default_settings(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to power control set level!", - return result); - - result = vega12_setup_default_dpm_tables(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "Failed to setup default DPM tables!", - return result); - return result; -} - -static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps) -{ - return 0; -} - -static uint32_t vega12_find_lowest_dpm_level( - struct vega12_single_dpm_table *table) -{ - uint32_t i; - - for (i = 0; i < table->count; i++) { - if (table->dpm_levels[i].enabled) - break; - } - - if (i >= table->count) { - i = 0; - table->dpm_levels[i].enabled = true; - } - - return i; -} - -static uint32_t vega12_find_highest_dpm_level( - struct vega12_single_dpm_table *table) -{ - int32_t i = 0; - PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, - "[FindHighestDPMLevel] DPM Table has too many entries!", - return MAX_REGULAR_DPM_NUMBER - 1); - - for (i = table->count - 1; i >= 0; i--) { - if (table->dpm_levels[i].enabled) - break; - } - - if (i < 0) { - i = 0; - table->dpm_levels[i].enabled = true; - } - - return (uint32_t)i; -} - -static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = hwmgr->backend; - uint32_t min_freq; - int ret = 0; - - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { - min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min gfxclk !", - return ret); - } - - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_UCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min memclk !", - return ret); - - min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetHardMinByFreq, - (PPCLK_UCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set hard min memclk !", - return ret); - } - - if (data->smu_features[GNLD_DPM_UVD].enabled) { - min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_VCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min vclk!", - return ret); - - min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_DCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min dclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_VCE].enabled) { - min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_ECLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min eclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { - min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min socclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetHardMinByFreq, - (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set hard min dcefclk!", - return ret); - } - - return ret; - -} - -static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = hwmgr->backend; - uint32_t max_freq; - int ret = 0; - - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { - max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max gfxclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_UCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max memclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_UVD].enabled) { - max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_VCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max vclk!", - return ret); - - max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_DCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max dclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_VCE].enabled) { - max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_ECLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max eclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { - max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max socclk!", - return ret); - } - - return ret; -} - -int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_DPM_VCE].supported) { - PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, - enable, - data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), - "Attempt to Enable/Disable DPM VCE Failed!", - return -1); - data->smu_features[GNLD_DPM_VCE].enabled = enable; - } - - return 0; -} - -static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t gfx_clk; - - if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) - return -1; - - if (low) - PP_ASSERT_WITH_CODE( - vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0, - "[GetSclks]: fail to get min PPCLK_GFXCLK\n", - return -1); - else - PP_ASSERT_WITH_CODE( - vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0, - "[GetSclks]: fail to get max PPCLK_GFXCLK\n", - return -1); - - return (gfx_clk * 100); -} - -static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t mem_clk; - - if (!data->smu_features[GNLD_DPM_UCLK].enabled) - return -1; - - if (low) - PP_ASSERT_WITH_CODE( - vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0, - "[GetMclks]: fail to get min PPCLK_UCLK\n", - return -1); - else - PP_ASSERT_WITH_CODE( - vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0, - "[GetMclks]: fail to get max PPCLK_UCLK\n", - return -1); - - return (mem_clk * 100); -} - -static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, - SmuMetrics_t *metrics_table, - bool bypass_cache) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (bypass_cache || - !data->metrics_time || - time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { - ret = smum_smc_table_manager(hwmgr, - (uint8_t *)(&data->metrics_table), - TABLE_SMU_METRICS, - true); - if (ret) { - pr_info("Failed to export SMU metrics table!\n"); - return ret; - } - data->metrics_time = jiffies; - } - - if (metrics_table) - memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); - - return ret; -} - -static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) -{ - SmuMetrics_t metrics_table; - int ret = 0; - - ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - *query = metrics_table.CurrSocketPower << 8; - - return ret; -} - -static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) -{ - uint32_t gfx_clk = 0; - - *gfx_freq = 0; - - PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16), - &gfx_clk) == 0, - "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!", - return -EINVAL); - - *gfx_freq = gfx_clk * 100; - - return 0; -} - -static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) -{ - uint32_t mem_clk = 0; - - *mclk_freq = 0; - - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16), - &mem_clk) == 0, - "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!", - return -EINVAL); - - *mclk_freq = mem_clk * 100; - - return 0; -} - -static int vega12_get_current_activity_percent( - struct pp_hwmgr *hwmgr, - int idx, - uint32_t *activity_percent) -{ - SmuMetrics_t metrics_table; - int ret = 0; - - ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - switch (idx) { - case AMDGPU_PP_SENSOR_GPU_LOAD: - *activity_percent = metrics_table.AverageGfxActivity; - break; - case AMDGPU_PP_SENSOR_MEM_LOAD: - *activity_percent = metrics_table.AverageUclkActivity; - break; - default: - pr_err("Invalid index for retrieving clock activity\n"); - return -EINVAL; - } - - return ret; -} - -static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, - void *value, int *size) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - SmuMetrics_t metrics_table; - int ret = 0; - - switch (idx) { - case AMDGPU_PP_SENSOR_GFX_SCLK: - ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value); - if (!ret) - *size = 4; - break; - case AMDGPU_PP_SENSOR_GFX_MCLK: - ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value); - if (!ret) - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_LOAD: - case AMDGPU_PP_SENSOR_MEM_LOAD: - ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); - if (!ret) - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_TEMP: - *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr); - *size = 4; - break; - case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: - ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - *((uint32_t *)value) = metrics_table.TemperatureHotspot * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - *size = 4; - break; - case AMDGPU_PP_SENSOR_MEM_TEMP: - ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - *((uint32_t *)value) = metrics_table.TemperatureHBM * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - *size = 4; - break; - case AMDGPU_PP_SENSOR_UVD_POWER: - *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; - *size = 4; - break; - case AMDGPU_PP_SENSOR_VCE_POWER: - *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_POWER: - ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value); - if (!ret) - *size = 4; - break; - case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: - ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value); - if (!ret) - *size = 8; - break; - default: - ret = -EINVAL; - break; - } - return ret; -} - -static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr, - bool has_disp) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_DPM_UCLK].enabled) - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetUclkFastSwitch, - has_disp ? 1 : 0, - NULL); - - return 0; -} - -static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr, - struct pp_display_clock_request *clock_req) -{ - int result = 0; - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - enum amd_pp_clock_type clk_type = clock_req->clock_type; - uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; - PPCLK_e clk_select = 0; - uint32_t clk_request = 0; - - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - switch (clk_type) { - case amd_pp_dcef_clock: - clk_select = PPCLK_DCEFCLK; - break; - case amd_pp_disp_clock: - clk_select = PPCLK_DISPCLK; - break; - case amd_pp_pixel_clock: - clk_select = PPCLK_PIXCLK; - break; - case amd_pp_phy_clock: - clk_select = PPCLK_PHYCLK; - break; - default: - pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); - result = -1; - break; - } - - if (!result) { - clk_request = (clk_select << 16) | clk_freq; - result = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinByFreq, - clk_request, - NULL); - } - } - - return result; -} - -static int vega12_notify_smc_display_config_after_ps_adjustment( - struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - struct PP_Clocks min_clocks = {0}; - struct pp_display_clock_request clock_req; - - if ((hwmgr->display_config->num_display > 1) && - !hwmgr->display_config->multi_monitor_in_sync && - !hwmgr->display_config->nb_pstate_switch_disable) - vega12_notify_smc_display_change(hwmgr, false); - else - vega12_notify_smc_display_change(hwmgr, true); - - min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; - min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; - min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; - - if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { - clock_req.clock_type = amd_pp_dcef_clock; - clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; - if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { - if (data->smu_features[GNLD_DS_DCEFCLK].supported) - PP_ASSERT_WITH_CODE( - !smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, - min_clocks.dcefClockInSR /100, - NULL), - "Attempt to set divider for DCEFCLK Failed!", - return -1); - } else { - pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); - } - } - - return 0; -} - -static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - - uint32_t soft_level; - - soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table)); - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->dpm_table.gfx_table.dpm_levels[soft_level].value; - - soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table)); - - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->dpm_table.mem_table.dpm_levels[soft_level].value; - - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), - "Failed to upload boot level to highest!", - return -1); - - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), - "Failed to upload dpm max level to highest!", - return -1); - - return 0; -} - -static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t soft_level; - - soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->dpm_table.gfx_table.dpm_levels[soft_level].value; - - soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table)); - - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->dpm_table.mem_table.dpm_levels[soft_level].value; - - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), - "Failed to upload boot level to highest!", - return -1); - - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), - "Failed to upload dpm max level to highest!", - return -1); - - return 0; - -} - -static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr) -{ - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), - "Failed to upload DPM Bootup Levels!", - return -1); - - PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), - "Failed to upload DPM Max Levels!", - return -1); - - return 0; -} - -static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, - uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); - struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); - struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); - - *sclk_mask = 0; - *mclk_mask = 0; - *soc_mask = 0; - - if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL && - mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL && - soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) { - *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; - *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; - *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; - } - - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { - *sclk_mask = 0; - } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { - *mclk_mask = 0; - } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - *sclk_mask = gfx_dpm_table->count - 1; - *mclk_mask = mem_dpm_table->count - 1; - *soc_mask = soc_dpm_table->count - 1; - } - - return 0; -} - -static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - switch (mode) { - case AMD_FAN_CTRL_NONE: - break; - case AMD_FAN_CTRL_MANUAL: - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega12_fan_ctrl_stop_smc_fan_control(hwmgr); - break; - case AMD_FAN_CTRL_AUTO: - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega12_fan_ctrl_start_smc_fan_control(hwmgr); - break; - default: - break; - } -} - -static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, - enum amd_dpm_forced_level level) -{ - int ret = 0; - uint32_t sclk_mask = 0; - uint32_t mclk_mask = 0; - uint32_t soc_mask = 0; - - switch (level) { - case AMD_DPM_FORCED_LEVEL_HIGH: - ret = vega12_force_dpm_highest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_LOW: - ret = vega12_force_dpm_lowest(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_AUTO: - ret = vega12_unforce_dpm_levels(hwmgr); - break; - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: - ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); - if (ret) - return ret; - vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); - vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); - break; - case AMD_DPM_FORCED_LEVEL_MANUAL: - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: - default: - break; - } - - return ret; -} - -static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) - return AMD_FAN_CTRL_MANUAL; - else - return AMD_FAN_CTRL_AUTO; -} - -static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr, - struct amd_pp_simple_clock_info *info) -{ -#if 0 - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_clock_and_voltage_limits *max_limits = - &table_info->max_clock_voltage_on_ac; - - info->engine_max_clock = max_limits->sclk; - info->memory_max_clock = max_limits->mclk; -#endif - return 0; -} - -static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, - uint32_t *clock, - PPCLK_e clock_select, - bool max) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (max) - *clock = data->clk_range[clock_select].ACMax; - else - *clock = data->clk_range[clock_select].ACMin; - - return 0; -} - -static int vega12_get_sclks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t ucount; - int i; - struct vega12_single_dpm_table *dpm_table; - - if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) - return -1; - - dpm_table = &(data->dpm_table.gfx_table); - ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? - MAX_NUM_CLOCKS : dpm_table->count; - - for (i = 0; i < ucount; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - - clocks->data[i].latency_in_us = 0; - } - - clocks->num_levels = ucount; - - return 0; -} - -static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, - uint32_t clock) -{ - return 25; -} - -static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t ucount; - int i; - struct vega12_single_dpm_table *dpm_table; - if (!data->smu_features[GNLD_DPM_UCLK].enabled) - return -1; - - dpm_table = &(data->dpm_table.mem_table); - ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? - MAX_NUM_CLOCKS : dpm_table->count; - - for (i = 0; i < ucount; i++) { - clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; - data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100; - clocks->data[i].latency_in_us = - data->mclk_latency_table.entries[i].latency = - vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); - } - - clocks->num_levels = data->mclk_latency_table.count = ucount; - - return 0; -} - -static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t ucount; - int i; - struct vega12_single_dpm_table *dpm_table; - - if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) - return -1; - - - dpm_table = &(data->dpm_table.dcef_table); - ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? - MAX_NUM_CLOCKS : dpm_table->count; - - for (i = 0; i < ucount; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - - clocks->data[i].latency_in_us = 0; - } - - clocks->num_levels = ucount; - - return 0; -} - -static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t ucount; - int i; - struct vega12_single_dpm_table *dpm_table; - - if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) - return -1; - - - dpm_table = &(data->dpm_table.soc_table); - ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? - MAX_NUM_CLOCKS : dpm_table->count; - - for (i = 0; i < ucount; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - - clocks->data[i].latency_in_us = 0; - } - - clocks->num_levels = ucount; - - return 0; - -} - -static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks) -{ - int ret; - - switch (type) { - case amd_pp_sys_clock: - ret = vega12_get_sclks(hwmgr, clocks); - break; - case amd_pp_mem_clock: - ret = vega12_get_memclocks(hwmgr, clocks); - break; - case amd_pp_dcef_clock: - ret = vega12_get_dcefclocks(hwmgr, clocks); - break; - case amd_pp_soc_clock: - ret = vega12_get_socclocks(hwmgr, clocks); - break; - default: - return -EINVAL; - } - - return ret; -} - -static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks) -{ - clocks->num_levels = 0; - - return 0; -} - -static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, - void *clock_ranges) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - Watermarks_t *table = &(data->smc_state_table.water_marks_table); - struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; - - if (!data->registry_data.disable_water_mark && - data->smu_features[GNLD_DPM_DCEFCLK].supported && - data->smu_features[GNLD_DPM_SOCCLK].supported) { - smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); - data->water_marks_bitmap |= WaterMarksExist; - data->water_marks_bitmap &= ~WaterMarksLoaded; - } - - return 0; -} - -static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - uint32_t soft_min_level, soft_max_level, hard_min_level; - int ret = 0; - - switch (type) { - case PP_SCLK: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; - - ret = vega12_upload_dpm_min_level(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - ret = vega12_upload_dpm_max_level(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - break; - - case PP_MCLK: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->dpm_table.mem_table.dpm_levels[soft_min_level].value; - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->dpm_table.mem_table.dpm_levels[soft_max_level].value; - - ret = vega12_upload_dpm_min_level(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - ret = vega12_upload_dpm_max_level(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - - break; - - case PP_SOCCLK: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - - if (soft_max_level >= data->dpm_table.soc_table.count) { - pr_err("Clock level specified %d is over max allowed %d\n", - soft_max_level, - data->dpm_table.soc_table.count - 1); - return -EINVAL; - } - - data->dpm_table.soc_table.dpm_state.soft_min_level = - data->dpm_table.soc_table.dpm_levels[soft_min_level].value; - data->dpm_table.soc_table.dpm_state.soft_max_level = - data->dpm_table.soc_table.dpm_levels[soft_max_level].value; - - ret = vega12_upload_dpm_min_level(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - ret = vega12_upload_dpm_max_level(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - - break; - - case PP_DCEFCLK: - hard_min_level = mask ? (ffs(mask) - 1) : 0; - - if (hard_min_level >= data->dpm_table.dcef_table.count) { - pr_err("Clock level specified %d is over max allowed %d\n", - hard_min_level, - data->dpm_table.dcef_table.count - 1); - return -EINVAL; - } - - data->dpm_table.dcef_table.dpm_state.hard_min_level = - data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; - - ret = vega12_upload_dpm_min_level(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - //TODO: Setting DCEFCLK max dpm level is not supported - - break; - - case PP_PCIE: - break; - - default: - break; - } - - return 0; -} - -static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) -{ - static const char *ppfeature_name[] = { - "DPM_PREFETCHER", - "GFXCLK_DPM", - "UCLK_DPM", - "SOCCLK_DPM", - "UVD_DPM", - "VCE_DPM", - "ULV", - "MP0CLK_DPM", - "LINK_DPM", - "DCEFCLK_DPM", - "GFXCLK_DS", - "SOCCLK_DS", - "LCLK_DS", - "PPT", - "TDC", - "THERMAL", - "GFX_PER_CU_CG", - "RM", - "DCEFCLK_DS", - "ACDC", - "VR0HOT", - "VR1HOT", - "FW_CTF", - "LED_DISPLAY", - "FAN_CONTROL", - "DIDT", - "GFXOFF", - "CG", - "ACG"}; - static const char *output_title[] = { - "FEATURES", - "BITMASK", - "ENABLEMENT"}; - uint64_t features_enabled; - int i; - int ret = 0; - int size = 0; - - ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); - PP_ASSERT_WITH_CODE(!ret, - "[EnableAllSmuFeatures] Failed to get enabled smc features!", - return ret); - - size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); - size += sprintf(buf + size, "%-19s %-22s %s\n", - output_title[0], - output_title[1], - output_title[2]); - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", - ppfeature_name[i], - 1ULL << i, - (features_enabled & (1ULL << i)) ? "Y" : "N"); - } - - return size; -} - -static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) -{ - uint64_t features_enabled; - uint64_t features_to_enable; - uint64_t features_to_disable; - int ret = 0; - - if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) - return -EINVAL; - - ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); - if (ret) - return ret; - - features_to_disable = - features_enabled & ~new_ppfeature_masks; - features_to_enable = - ~features_enabled & new_ppfeature_masks; - - pr_debug("features_to_disable 0x%llx\n", features_to_disable); - pr_debug("features_to_enable 0x%llx\n", features_to_enable); - - if (features_to_disable) { - ret = vega12_enable_smc_features(hwmgr, false, features_to_disable); - if (ret) - return ret; - } - - if (features_to_enable) { - ret = vega12_enable_smc_features(hwmgr, true, features_to_enable); - if (ret) - return ret; - } - - return 0; -} - -static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & - PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) - >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; -} - -static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) -{ - uint32_t width_level; - - width_level = vega12_get_current_pcie_link_width_level(hwmgr); - if (width_level > LINK_WIDTH_MAX) - width_level = 0; - - return link_width[width_level]; -} - -static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & - PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) - >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; -} - -static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) -{ - uint32_t speed_level; - - speed_level = vega12_get_current_pcie_link_speed_level(hwmgr); - if (speed_level > LINK_SPEED_MAX) - speed_level = 0; - - return link_speed[speed_level]; -} - -static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) -{ - int i, now, size = 0; - struct pp_clock_levels_with_latency clocks; - - switch (type) { - case PP_SCLK: - PP_ASSERT_WITH_CODE( - vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0, - "Attempt to get current gfx clk Failed!", - return -1); - - PP_ASSERT_WITH_CODE( - vega12_get_sclks(hwmgr, &clocks) == 0, - "Attempt to get gfx clk levels Failed!", - return -1); - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); - break; - - case PP_MCLK: - PP_ASSERT_WITH_CODE( - vega12_get_current_mclk_freq(hwmgr, &now) == 0, - "Attempt to get current mclk freq Failed!", - return -1); - - PP_ASSERT_WITH_CODE( - vega12_get_memclocks(hwmgr, &clocks) == 0, - "Attempt to get memory clk levels Failed!", - return -1); - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); - break; - - case PP_SOCCLK: - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16), - &now) == 0, - "Attempt to get Current SOCCLK Frequency Failed!", - return -EINVAL); - - PP_ASSERT_WITH_CODE( - vega12_get_socclocks(hwmgr, &clocks) == 0, - "Attempt to get soc clk levels Failed!", - return -1); - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); - break; - - case PP_DCEFCLK: - PP_ASSERT_WITH_CODE( - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16), - &now) == 0, - "Attempt to get Current DCEFCLK Frequency Failed!", - return -EINVAL); - - PP_ASSERT_WITH_CODE( - vega12_get_dcefclocks(hwmgr, &clocks) == 0, - "Attempt to get dcef clk levels Failed!", - return -1); - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); - break; - - case PP_PCIE: - break; - - default: - break; - } - return size; -} - -static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - struct vega12_single_dpm_table *dpm_table; - bool vblank_too_short = false; - bool disable_mclk_switching; - uint32_t i, latency; - - disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && - !hwmgr->display_config->multi_monitor_in_sync) || - vblank_too_short; - latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; - - /* gfxclk */ - dpm_table = &(data->dpm_table.gfx_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* memclk */ - dpm_table = &(data->dpm_table.mem_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* honour DAL's UCLK Hardmin */ - if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) - dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; - - /* Hardmin is dependent on displayconfig */ - if (disable_mclk_switching) { - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - for (i = 0; i < data->mclk_latency_table.count - 1; i++) { - if (data->mclk_latency_table.entries[i].latency <= latency) { - if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; - break; - } - } - } - } - - if (hwmgr->display_config->nb_pstate_switch_disable) - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - /* vclk */ - dpm_table = &(data->dpm_table.vclk_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* dclk */ - dpm_table = &(data->dpm_table.dclk_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* socclk */ - dpm_table = &(data->dpm_table.soc_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* eclk */ - dpm_table = &(data->dpm_table.eclk_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - return 0; -} - -static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, - struct vega12_single_dpm_table *dpm_table) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - PP_ASSERT_WITH_CODE(dpm_table->count > 0, - "[SetUclkToHightestDpmLevel] Dpm table has no entry!", - return -EINVAL); - PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, - "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", - return -EINVAL); - - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinByFreq, - (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, - NULL)), - "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", - return ret); - } - - return ret; -} - -static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - int ret = 0; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, 0, - NULL); - - ret = vega12_set_uclk_to_highest_dpm_level(hwmgr, - &data->dpm_table.mem_table); - - return ret; -} - -static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - int result = 0; - Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); - - if ((data->water_marks_bitmap & WaterMarksExist) && - !(data->water_marks_bitmap & WaterMarksLoaded)) { - result = smum_smc_table_manager(hwmgr, - (uint8_t *)wm_table, TABLE_WATERMARKS, false); - PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); - data->water_marks_bitmap |= WaterMarksLoaded; - } - - if ((data->water_marks_bitmap & WaterMarksExist) && - data->smu_features[GNLD_DPM_DCEFCLK].supported && - data->smu_features[GNLD_DPM_SOCCLK].supported) - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, - NULL); - - return result; -} - -static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_DPM_UVD].supported) { - PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, - enable, - data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), - "Attempt to Enable/Disable DPM UVD Failed!", - return -1); - data->smu_features[GNLD_DPM_UVD].enabled = enable; - } - - return 0; -} - -static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->vce_power_gated == bgate) - return; - - data->vce_power_gated = bgate; - vega12_enable_disable_vce_dpm(hwmgr, !bgate); -} - -static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->uvd_power_gated == bgate) - return; - - data->uvd_power_gated = bgate; - vega12_enable_disable_uvd_dpm(hwmgr, !bgate); -} - -static bool -vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - bool is_update_required = false; - - if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) - is_update_required = true; - - if (data->registry_data.gfx_clk_deep_sleep_support) { - if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) - is_update_required = true; - } - - return is_update_required; -} - -static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - - tmp_result = vega12_disable_all_smu_features(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable all smu features!", result = tmp_result); - - return result; -} - -static int vega12_power_off_asic(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - int result; - - result = vega12_disable_dpm_tasks(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "[disable_dpm_tasks] Failed to disable DPM!", - ); - data->water_marks_bitmap &= ~(WaterMarksLoaded); - - return result; -} - -#if 0 -static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr, - uint32_t *sclk_idx, uint32_t *mclk_idx, - uint32_t min_sclk, uint32_t min_mclk) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - struct vega12_dpm_table *dpm_table = &(data->dpm_table); - uint32_t i; - - for (i = 0; i < dpm_table->gfx_table.count; i++) { - if (dpm_table->gfx_table.dpm_levels[i].enabled && - dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { - *sclk_idx = i; - break; - } - } - - for (i = 0; i < dpm_table->mem_table.count; i++) { - if (dpm_table->mem_table.dpm_levels[i].enabled && - dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { - *mclk_idx = i; - break; - } - } -} -#endif - -#if 0 -static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr, - struct amd_pp_profile *request) -{ - return 0; -} - -static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); - struct vega12_single_dpm_table *golden_sclk_table = - &(data->golden_dpm_table.gfx_table); - int value = sclk_table->dpm_levels[sclk_table->count - 1].value; - int golden_value = golden_sclk_table->dpm_levels - [golden_sclk_table->count - 1].value; - - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) -{ - return 0; -} - -static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); - struct vega12_single_dpm_table *golden_mclk_table = - &(data->golden_dpm_table.mem_table); - int value = mclk_table->dpm_levels[mclk_table->count - 1].value; - int golden_value = golden_mclk_table->dpm_levels - [golden_mclk_table->count - 1].value; - - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) -{ - return 0; -} -#endif - -static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, - uint32_t virtual_addr_low, - uint32_t virtual_addr_hi, - uint32_t mc_addr_low, - uint32_t mc_addr_hi, - uint32_t size) -{ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSystemVirtualDramAddrHigh, - virtual_addr_hi, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSystemVirtualDramAddrLow, - virtual_addr_low, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramAddrHigh, - mc_addr_hi, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramAddrLow, - mc_addr_low, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramSize, - size, - NULL); - return 0; -} - -static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *thermal_data) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - - memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); - - thermal_data->max = pp_table->TedgeLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->mem_crit_max = pp_table->ThbmLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return 0; -} - -static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (data->gfxoff_controlled_by_driver) - ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL); - - return ret; -} - -static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (data->gfxoff_controlled_by_driver) - ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL); - - return ret; -} - -static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) -{ - if (enable) - return vega12_enable_gfx_off(hwmgr); - else - return vega12_disable_gfx_off(hwmgr); -} - -static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, - PHM_PerformanceLevelDesignation designation, uint32_t index, - PHM_PerformanceLevel *level) -{ - return 0; -} - -static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr, - enum pp_mp1_state mp1_state) -{ - uint16_t msg; - int ret; - - switch (mp1_state) { - case PP_MP1_STATE_UNLOAD: - msg = PPSMC_MSG_PrepareMp1ForUnload; - break; - case PP_MP1_STATE_SHUTDOWN: - case PP_MP1_STATE_RESET: - case PP_MP1_STATE_NONE: - default: - return 0; - } - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, - "[PrepareMp1] Failed!", - return ret); - - return 0; -} - -static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) -{ - memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); - - gpu_metrics->common_header.structure_size = - sizeof(struct gpu_metrics_v1_0); - gpu_metrics->common_header.format_revision = 1; - gpu_metrics->common_header.content_revision = 0; - - gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); -} - -static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr, - void **table) -{ - struct vega12_hwmgr *data = - (struct vega12_hwmgr *)(hwmgr->backend); - struct gpu_metrics_v1_0 *gpu_metrics = - &data->gpu_metrics_table; - SmuMetrics_t metrics; - uint32_t fan_speed_rpm; - int ret; - - ret = vega12_get_metrics_table(hwmgr, &metrics, true); - if (ret) - return ret; - - vega12_init_gpu_metrics_v1_0(gpu_metrics); - - gpu_metrics->temperature_edge = metrics.TemperatureEdge; - gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; - gpu_metrics->temperature_mem = metrics.TemperatureHBM; - gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; - gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; - - gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; - gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; - - gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; - gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; - gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; - - gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; - gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; - gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; - gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; - gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; - - gpu_metrics->throttle_status = metrics.ThrottlerStatus; - - vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); - gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; - - gpu_metrics->pcie_link_width = - vega12_get_current_pcie_link_width(hwmgr); - gpu_metrics->pcie_link_speed = - vega12_get_current_pcie_link_speed(hwmgr); - - *table = (void *)gpu_metrics; - - return sizeof(struct gpu_metrics_v1_0); -} - -static const struct pp_hwmgr_func vega12_hwmgr_funcs = { - .backend_init = vega12_hwmgr_backend_init, - .backend_fini = vega12_hwmgr_backend_fini, - .asic_setup = vega12_setup_asic_task, - .dynamic_state_management_enable = vega12_enable_dpm_tasks, - .dynamic_state_management_disable = vega12_disable_dpm_tasks, - .patch_boot_state = vega12_patch_boot_state, - .get_sclk = vega12_dpm_get_sclk, - .get_mclk = vega12_dpm_get_mclk, - .notify_smc_display_config_after_ps_adjustment = - vega12_notify_smc_display_config_after_ps_adjustment, - .force_dpm_level = vega12_dpm_force_dpm_level, - .stop_thermal_controller = vega12_thermal_stop_thermal_controller, - .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info, - .reset_fan_speed_to_default = - vega12_fan_ctrl_reset_fan_speed_to_default, - .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm, - .set_fan_control_mode = vega12_set_fan_control_mode, - .get_fan_control_mode = vega12_get_fan_control_mode, - .read_sensor = vega12_read_sensor, - .get_dal_power_level = vega12_get_dal_power_level, - .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency, - .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage, - .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges, - .display_clock_voltage_request = vega12_display_clock_voltage_request, - .force_clock_level = vega12_force_clock_level, - .print_clock_levels = vega12_print_clock_levels, - .apply_clocks_adjust_rules = - vega12_apply_clocks_adjust_rules, - .pre_display_config_changed = - vega12_pre_display_configuration_changed_task, - .display_config_changed = vega12_display_configuration_changed_task, - .powergate_uvd = vega12_power_gate_uvd, - .powergate_vce = vega12_power_gate_vce, - .check_smc_update_required_for_display_configuration = - vega12_check_smc_update_required_for_display_configuration, - .power_off_asic = vega12_power_off_asic, - .disable_smc_firmware_ctf = vega12_thermal_disable_alert, -#if 0 - .set_power_profile_state = vega12_set_power_profile_state, - .get_sclk_od = vega12_get_sclk_od, - .set_sclk_od = vega12_set_sclk_od, - .get_mclk_od = vega12_get_mclk_od, - .set_mclk_od = vega12_set_mclk_od, -#endif - .notify_cac_buffer_info = vega12_notify_cac_buffer_info, - .get_thermal_temperature_range = vega12_get_thermal_temperature_range, - .register_irq_handlers = smu9_register_irq_handlers, - .start_thermal_controller = vega12_start_thermal_controller, - .powergate_gfx = vega12_gfx_off_control, - .get_performance_level = vega12_get_performance_level, - .get_asic_baco_capability = smu9_baco_get_capability, - .get_asic_baco_state = smu9_baco_get_state, - .set_asic_baco_state = vega12_baco_set_state, - .get_ppfeature_status = vega12_get_ppfeature_status, - .set_ppfeature_status = vega12_set_ppfeature_status, - .set_mp1_state = vega12_set_mp1_state, - .get_gpu_metrics = vega12_get_gpu_metrics, -}; - -int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) -{ - hwmgr->hwmgr_func = &vega12_hwmgr_funcs; - hwmgr->pptable_func = &vega12_pptable_funcs; - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h deleted file mode 100644 index aa63ae41942d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _VEGA12_HWMGR_H_ -#define _VEGA12_HWMGR_H_ - -#include "hwmgr.h" -#include "vega12/smu9_driver_if.h" -#include "ppatomfwctrl.h" - -#define VEGA12_MAX_HARDWARE_POWERLEVELS 2 - -#define WaterMarksExist 1 -#define WaterMarksLoaded 2 - -#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 16 -#define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8 -#define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8 -#define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS 4 - -enum -{ - GNLD_DPM_PREFETCHER = 0, - GNLD_DPM_GFXCLK, - GNLD_DPM_UCLK, - GNLD_DPM_SOCCLK, - GNLD_DPM_UVD, - GNLD_DPM_VCE, - GNLD_ULV, - GNLD_DPM_MP0CLK, - GNLD_DPM_LINK, - GNLD_DPM_DCEFCLK, - GNLD_DS_GFXCLK, - GNLD_DS_SOCCLK, - GNLD_DS_LCLK, - GNLD_PPT, - GNLD_TDC, - GNLD_THERMAL, - GNLD_GFX_PER_CU_CG, - GNLD_RM, - GNLD_DS_DCEFCLK, - GNLD_ACDC, - GNLD_VR0HOT, - GNLD_VR1HOT, - GNLD_FW_CTF, - GNLD_LED_DISPLAY, - GNLD_FAN_CONTROL, - GNLD_DIDT, - GNLD_GFXOFF, - GNLD_CG, - GNLD_ACG, - - GNLD_FEATURES_MAX -}; - - -#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) - -#define SMC_DPM_FEATURES 0x30F - -struct smu_features { - bool supported; - bool enabled; - bool allowed; - uint32_t smu_feature_id; - uint64_t smu_feature_bitmap; -}; - -struct vega12_dpm_level { - bool enabled; - uint32_t value; - uint32_t param1; -}; - -#define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5 -#define MAX_REGULAR_DPM_NUMBER 16 -#define MAX_PCIE_CONF 2 -#define VEGA12_MINIMUM_ENGINE_CLOCK 2500 - -struct vega12_dpm_state { - uint32_t soft_min_level; - uint32_t soft_max_level; - uint32_t hard_min_level; - uint32_t hard_max_level; -}; - -struct vega12_single_dpm_table { - uint32_t count; - struct vega12_dpm_state dpm_state; - struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega12_odn_dpm_control { - uint32_t count; - uint32_t entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega12_pcie_table { - uint16_t count; - uint8_t pcie_gen[MAX_PCIE_CONF]; - uint8_t pcie_lane[MAX_PCIE_CONF]; - uint32_t lclk[MAX_PCIE_CONF]; -}; - -struct vega12_dpm_table { - struct vega12_single_dpm_table soc_table; - struct vega12_single_dpm_table gfx_table; - struct vega12_single_dpm_table mem_table; - struct vega12_single_dpm_table eclk_table; - struct vega12_single_dpm_table vclk_table; - struct vega12_single_dpm_table dclk_table; - struct vega12_single_dpm_table dcef_table; - struct vega12_single_dpm_table pixel_table; - struct vega12_single_dpm_table display_table; - struct vega12_single_dpm_table phy_table; - struct vega12_pcie_table pcie_table; -}; - -#define VEGA12_MAX_LEAKAGE_COUNT 8 -struct vega12_leakage_voltage { - uint16_t count; - uint16_t leakage_id[VEGA12_MAX_LEAKAGE_COUNT]; - uint16_t actual_voltage[VEGA12_MAX_LEAKAGE_COUNT]; -}; - -struct vega12_display_timing { - uint32_t min_clock_in_sr; - uint32_t num_existing_displays; -}; - -struct vega12_dpmlevel_enable_mask { - uint32_t uvd_dpm_enable_mask; - uint32_t vce_dpm_enable_mask; - uint32_t samu_dpm_enable_mask; - uint32_t sclk_dpm_enable_mask; - uint32_t mclk_dpm_enable_mask; -}; - -struct vega12_vbios_boot_state { - bool bsoc_vddc_lock; - uint8_t uc_cooling_id; - uint16_t vddc; - uint16_t vddci; - uint16_t mvddc; - uint16_t vdd_gfx; - uint32_t gfx_clock; - uint32_t mem_clock; - uint32_t soc_clock; - uint32_t dcef_clock; - uint32_t eclock; - uint32_t dclock; - uint32_t vclock; -}; - -#define DPMTABLE_OD_UPDATE_SCLK 0x00000001 -#define DPMTABLE_OD_UPDATE_MCLK 0x00000002 -#define DPMTABLE_UPDATE_SCLK 0x00000004 -#define DPMTABLE_UPDATE_MCLK 0x00000008 -#define DPMTABLE_OD_UPDATE_VDDC 0x00000010 - -struct vega12_smc_state_table { - uint32_t soc_boot_level; - uint32_t gfx_boot_level; - uint32_t dcef_boot_level; - uint32_t mem_boot_level; - uint32_t uvd_boot_level; - uint32_t vce_boot_level; - uint32_t gfx_max_level; - uint32_t mem_max_level; - uint8_t vr_hot_gpio; - uint8_t ac_dc_gpio; - uint8_t therm_out_gpio; - uint8_t therm_out_polarity; - uint8_t therm_out_mode; - PPTable_t pp_table; - Watermarks_t water_marks_table; - AvfsDebugTable_t avfs_debug_table; - AvfsFuseOverride_t avfs_fuse_override_table; - SmuMetrics_t smu_metrics; - DriverSmuConfig_t driver_smu_config; - DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint; - OverDriveTable_t overdrive_table; -}; - -struct vega12_mclk_latency_entries { - uint32_t frequency; - uint32_t latency; -}; - -struct vega12_mclk_latency_table { - uint32_t count; - struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega12_registry_data { - uint64_t disallowed_features; - uint8_t ac_dc_switch_gpio_support; - uint8_t acg_loop_support; - uint8_t clock_stretcher_support; - uint8_t db_ramping_support; - uint8_t didt_mode; - uint8_t didt_support; - uint8_t edc_didt_support; - uint8_t force_dpm_high; - uint8_t fuzzy_fan_control_support; - uint8_t mclk_dpm_key_disabled; - uint8_t od_state_in_dc_support; - uint8_t pcie_lane_override; - uint8_t pcie_speed_override; - uint32_t pcie_clock_override; - uint8_t pcie_dpm_key_disabled; - uint8_t dcefclk_dpm_key_disabled; - uint8_t prefetcher_dpm_key_disabled; - uint8_t quick_transition_support; - uint8_t regulator_hot_gpio_support; - uint8_t master_deep_sleep_support; - uint8_t gfx_clk_deep_sleep_support; - uint8_t sclk_deep_sleep_support; - uint8_t lclk_deep_sleep_support; - uint8_t dce_fclk_deep_sleep_support; - uint8_t sclk_dpm_key_disabled; - uint8_t sclk_throttle_low_notification; - uint8_t skip_baco_hardware; - uint8_t socclk_dpm_key_disabled; - uint8_t sq_ramping_support; - uint8_t tcp_ramping_support; - uint8_t td_ramping_support; - uint8_t dbr_ramping_support; - uint8_t gc_didt_support; - uint8_t psm_didt_support; - uint8_t thermal_support; - uint8_t fw_ctf_enabled; - uint8_t led_dpm_enabled; - uint8_t fan_control_support; - uint8_t ulv_support; - uint8_t odn_feature_enable; - uint8_t disable_water_mark; - uint8_t disable_workload_policy; - uint32_t force_workload_policy_mask; - uint8_t disable_3d_fs_detection; - uint8_t disable_pp_tuning; - uint8_t disable_xlpp_tuning; - uint32_t perf_ui_tuning_profile_turbo; - uint32_t perf_ui_tuning_profile_powerSave; - uint32_t perf_ui_tuning_profile_xl; - uint16_t zrpm_stop_temp; - uint16_t zrpm_start_temp; - uint32_t stable_pstate_sclk_dpm_percentage; - uint8_t fps_support; - uint8_t vr0hot; - uint8_t vr1hot; - uint8_t disable_auto_wattman; - uint32_t auto_wattman_debug; - uint32_t auto_wattman_sample_period; - uint8_t auto_wattman_threshold; - uint8_t log_avfs_param; - uint8_t enable_enginess; - uint8_t custom_fan_support; - uint8_t disable_pcc_limit_control; -}; - -struct vega12_odn_clock_voltage_dependency_table { - uint32_t count; - struct phm_ppt_v1_clock_voltage_dependency_record - entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega12_odn_dpm_table { - struct vega12_odn_dpm_control control_gfxclk_state; - struct vega12_odn_dpm_control control_memclk_state; - struct phm_odn_clock_levels odn_core_clock_dpm_levels; - struct phm_odn_clock_levels odn_memory_clock_dpm_levels; - struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; - struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; - struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_socclk; - uint32_t odn_mclk_min_limit; -}; - -struct vega12_odn_fan_table { - uint32_t target_fan_speed; - uint32_t target_temperature; - uint32_t min_performance_clock; - uint32_t min_fan_limit; - bool force_fan_pwm; -}; - -struct vega12_clock_range { - uint32_t ACMax; - uint32_t ACMin; - uint32_t DCMax; -}; - -struct vega12_hwmgr { - struct vega12_dpm_table dpm_table; - struct vega12_dpm_table golden_dpm_table; - struct vega12_registry_data registry_data; - struct vega12_vbios_boot_state vbios_boot_state; - struct vega12_mclk_latency_table mclk_latency_table; - - struct vega12_leakage_voltage vddc_leakage; - - uint32_t vddc_control; - struct pp_atomfwctrl_voltage_table vddc_voltage_table; - uint32_t mvdd_control; - struct pp_atomfwctrl_voltage_table mvdd_voltage_table; - uint32_t vddci_control; - struct pp_atomfwctrl_voltage_table vddci_voltage_table; - - uint32_t active_auto_throttle_sources; - uint32_t water_marks_bitmap; - - struct vega12_odn_dpm_table odn_dpm_table; - struct vega12_odn_fan_table odn_fan_table; - - /* ---- General data ---- */ - uint8_t need_update_dpm_table; - - bool cac_enabled; - bool battery_state; - bool is_tlu_enabled; - bool avfs_exist; - - uint32_t low_sclk_interrupt_threshold; - - uint32_t total_active_cus; - - struct vega12_display_timing display_timing; - - /* ---- Vega12 Dyn Register Settings ---- */ - - uint32_t debug_settings; - uint32_t lowest_uclk_reserved_for_ulv; - uint32_t gfxclk_average_alpha; - uint32_t socclk_average_alpha; - uint32_t uclk_average_alpha; - uint32_t gfx_activity_average_alpha; - uint32_t display_voltage_mode; - uint32_t dcef_clk_quad_eqn_a; - uint32_t dcef_clk_quad_eqn_b; - uint32_t dcef_clk_quad_eqn_c; - uint32_t disp_clk_quad_eqn_a; - uint32_t disp_clk_quad_eqn_b; - uint32_t disp_clk_quad_eqn_c; - uint32_t pixel_clk_quad_eqn_a; - uint32_t pixel_clk_quad_eqn_b; - uint32_t pixel_clk_quad_eqn_c; - uint32_t phy_clk_quad_eqn_a; - uint32_t phy_clk_quad_eqn_b; - uint32_t phy_clk_quad_eqn_c; - - /* ---- Thermal Temperature Setting ---- */ - struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; - - /* ---- Power Gating States ---- */ - bool uvd_power_gated; - bool vce_power_gated; - bool samu_power_gated; - bool need_long_memory_training; - - /* Internal settings to apply the application power optimization parameters */ - bool apply_optimized_settings; - uint32_t disable_dpm_mask; - - /* ---- Overdrive next setting ---- */ - uint32_t apply_overdrive_next_settings_mask; - - /* ---- Workload Mask ---- */ - uint32_t workload_mask; - - /* ---- SMU9 ---- */ - uint32_t smu_version; - struct smu_features smu_features[GNLD_FEATURES_MAX]; - struct vega12_smc_state_table smc_state_table; - - struct vega12_clock_range clk_range[PPCLK_COUNT]; - - /* ---- Gfxoff ---- */ - bool gfxoff_controlled_by_driver; - - unsigned long metrics_time; - SmuMetrics_t metrics_table; - struct gpu_metrics_v1_0 gpu_metrics_table; -}; - -#define VEGA12_DPM2_NEAR_TDP_DEC 10 -#define VEGA12_DPM2_ABOVE_SAFE_INC 5 -#define VEGA12_DPM2_BELOW_SAFE_INC 20 - -#define VEGA12_DPM2_LTA_WINDOW_SIZE 7 - -#define VEGA12_DPM2_LTS_TRUNCATE 0 - -#define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT 80 - -#define VEGA12_DPM2_MAXPS_PERCENT_M 90 -#define VEGA12_DPM2_MAXPS_PERCENT_H 90 - -#define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN 50 - -#define VEGA12_DPM2_SQ_RAMP_MAX_POWER 0x3FFF -#define VEGA12_DPM2_SQ_RAMP_MIN_POWER 0x12 -#define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 -#define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E -#define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF - -#define VEGA12_VOLTAGE_CONTROL_NONE 0x0 -#define VEGA12_VOLTAGE_CONTROL_BY_GPIO 0x1 -#define VEGA12_VOLTAGE_CONTROL_BY_SVID2 0x2 -#define VEGA12_VOLTAGE_CONTROL_MERGED 0x3 -/* To convert to Q8.8 format for firmware */ -#define VEGA12_Q88_FORMAT_CONVERSION_UNIT 256 - -#define VEGA12_UNUSED_GPIO_PIN 0x7F - -#define VEGA12_THERM_OUT_MODE_DISABLE 0x0 -#define VEGA12_THERM_OUT_MODE_THERM_ONLY 0x1 -#define VEGA12_THERM_OUT_MODE_THERM_VRHOT 0x2 - -#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff -#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff - -#define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff -#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff -#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff - -#define VEGA12_UMD_PSTATE_GFXCLK_LEVEL 0x3 -#define VEGA12_UMD_PSTATE_SOCCLK_LEVEL 0x3 -#define VEGA12_UMD_PSTATE_MCLK_LEVEL 0x2 -#define VEGA12_UMD_PSTATE_UVDCLK_LEVEL 0x3 -#define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL 0x3 - -int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); - -#endif /* _VEGA12_HWMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_inc.h deleted file mode 100644 index e6d9e84059e1..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_inc.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA12_INC_H -#define VEGA12_INC_H - -#include "asic_reg/thm/thm_9_0_default.h" -#include "asic_reg/thm/thm_9_0_offset.h" -#include "asic_reg/thm/thm_9_0_sh_mask.h" - -#include "asic_reg/mp/mp_9_0_offset.h" -#include "asic_reg/mp/mp_9_0_sh_mask.h" - -#include "asic_reg/gc/gc_9_2_1_offset.h" -#include "asic_reg/gc/gc_9_2_1_sh_mask.h" - -#include "asic_reg/nbio/nbio_6_1_offset.h" -#include "asic_reg/nbio/nbio_6_1_offset.h" -#include "asic_reg/nbio/nbio_6_1_sh_mask.h" - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_pptable.h deleted file mode 100644 index bf4f5095b80d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_pptable.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _VEGA12_PPTABLE_H_ -#define _VEGA12_PPTABLE_H_ - -#pragma pack(push, 1) - -#define ATOM_VEGA12_PP_THERMALCONTROLLER_NONE 0 -#define ATOM_VEGA12_PP_THERMALCONTROLLER_VEGA12 25 - -#define ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY 0x1 -#define ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 -#define ATOM_VEGA12_PP_PLATFORM_CAP_HARDWAREDC 0x4 -#define ATOM_VEGA12_PP_PLATFORM_CAP_BACO 0x8 -#define ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO 0x10 -#define ATOM_VEGA12_PP_PLATFORM_CAP_ENABLESHADOWPSTATE 0x20 - -#define ATOM_VEGA12_TABLE_REVISION_VEGA12 9 - -enum ATOM_VEGA12_ODSETTING_ID { - ATOM_VEGA12_ODSETTING_GFXCLKFMAX = 0, - ATOM_VEGA12_ODSETTING_GFXCLKFMIN, - ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P1, - ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1, - ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P2, - ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2, - ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P3, - ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3, - ATOM_VEGA12_ODSETTING_UCLKFMAX, - ATOM_VEGA12_ODSETTING_POWERPERCENTAGE, - ATOM_VEGA12_ODSETTING_FANRPMMIN, - ATOM_VEGA12_ODSETTING_FANRPMACOUSTICLIMIT, - ATOM_VEGA12_ODSETTING_FANTARGETTEMPERATURE, - ATOM_VEGA12_ODSETTING_OPERATINGTEMPMAX, - ATOM_VEGA12_ODSETTING_COUNT, -}; -typedef enum ATOM_VEGA12_ODSETTING_ID ATOM_VEGA12_ODSETTING_ID; - -enum ATOM_VEGA12_PPCLOCK_ID { - ATOM_VEGA12_PPCLOCK_GFXCLK = 0, - ATOM_VEGA12_PPCLOCK_VCLK, - ATOM_VEGA12_PPCLOCK_DCLK, - ATOM_VEGA12_PPCLOCK_ECLK, - ATOM_VEGA12_PPCLOCK_SOCCLK, - ATOM_VEGA12_PPCLOCK_UCLK, - ATOM_VEGA12_PPCLOCK_DCEFCLK, - ATOM_VEGA12_PPCLOCK_DISPCLK, - ATOM_VEGA12_PPCLOCK_PIXCLK, - ATOM_VEGA12_PPCLOCK_PHYCLK, - ATOM_VEGA12_PPCLOCK_COUNT, -}; -typedef enum ATOM_VEGA12_PPCLOCK_ID ATOM_VEGA12_PPCLOCK_ID; - - -typedef struct _ATOM_VEGA12_POWERPLAYTABLE -{ - struct atom_common_table_header sHeader; - UCHAR ucTableRevision; - USHORT usTableSize; - ULONG ulGoldenPPID; - ULONG ulGoldenRevision; - USHORT usFormatID; - - ULONG ulPlatformCaps; - - UCHAR ucThermalControllerType; - - USHORT usSmallPowerLimit1; - USHORT usSmallPowerLimit2; - USHORT usBoostPowerLimit; - USHORT usODTurboPowerLimit; - USHORT usODPowerSavePowerLimit; - USHORT usSoftwareShutdownTemp; - - ULONG PowerSavingClockMax [ATOM_VEGA12_PPCLOCK_COUNT]; - ULONG PowerSavingClockMin [ATOM_VEGA12_PPCLOCK_COUNT]; - - ULONG ODSettingsMax [ATOM_VEGA12_ODSETTING_COUNT]; - ULONG ODSettingsMin [ATOM_VEGA12_ODSETTING_COUNT]; - - USHORT usReserve[5]; - - PPTable_t smcPPTable; - -} ATOM_Vega12_POWERPLAYTABLE; - -#pragma pack(pop) - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c deleted file mode 100644 index 195d8539fbb4..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/fb.h> - -#include "vega12/smu9_driver_if.h" -#include "vega12_processpptables.h" -#include "ppatomfwctrl.h" -#include "atomfirmware.h" -#include "pp_debug.h" -#include "cgs_common.h" -#include "vega12_pptable.h" - -static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, - enum phm_platform_caps cap) -{ - if (enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); - else - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); -} - -static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) -{ - int index = GetIndexIntoMasterDataTable(powerplayinfo); - - u16 size; - u8 frev, crev; - const void *table_address = hwmgr->soft_pp_table; - - if (!table_address) { - table_address = (ATOM_Vega12_POWERPLAYTABLE *) - smu_atom_get_data_table(hwmgr->adev, index, - &size, &frev, &crev); - - hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ - hwmgr->soft_pp_table_size = size; - } - - return table_address; -} - -static int check_powerplay_tables( - struct pp_hwmgr *hwmgr, - const ATOM_Vega12_POWERPLAYTABLE *powerplay_table) -{ - PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= - ATOM_VEGA12_TABLE_REVISION_VEGA12), - "Unsupported PPTable format!", return -1); - PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, - "Invalid PowerPlay Table!", return -1); - - return 0; -} - -static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) -{ - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY), - PHM_PlatformCaps_PowerPlaySupport); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), - PHM_PlatformCaps_BiosPowerSourceControl); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO), - PHM_PlatformCaps_BACO); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO), - PHM_PlatformCaps_BAMACO); - - return 0; -} - -static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable) -{ - struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table; - - PP_ASSERT_WITH_CODE( - pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0, - "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!", - return -1); - - ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address; - ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address; - ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address; - ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address; - - ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl; - ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda; - ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl; - ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda; - - ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl; - ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda; - ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent; - ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent; - - ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx; - ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc; - - ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping; - ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping; - ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping; - ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping; - - ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask; - ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask; - - ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent; - ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset; - ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx; - - ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent; - ppsmc_pptable->SocOffset = smc_dpm_table.socoffset; - ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc; - - ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent; - ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset; - ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0; - - ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent; - ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset; - ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1; - - ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio; - ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity; - ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio; - ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity; - - ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio; - ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity; - ppsmc_pptable->Padding1 = smc_dpm_table.padding1; - ppsmc_pptable->Padding2 = smc_dpm_table.padding2; - - ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0; - ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1; - ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2; - - ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled; - ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent; - ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq; - - ppsmc_pptable->UclkSpreadEnabled = 0; - ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent; - ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq; - - ppsmc_pptable->SocclkSpreadEnabled = 0; - ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent; - ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq; - - ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled; - ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent; - ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq; - - ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address; - - ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address; - - return 0; -} - -#define VEGA12_ENGINECLOCK_HARDMAX 198000 -static int init_powerplay_table_information( - struct pp_hwmgr *hwmgr, - const ATOM_Vega12_POWERPLAYTABLE *powerplay_table) -{ - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - uint32_t disable_power_control = 0; - int result; - - hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType; - pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType; - - set_hw_cap(hwmgr, - ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, - PHM_PlatformCaps_ThermalController); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); - - if (le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]) > VEGA12_ENGINECLOCK_HARDMAX) - hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; - else - hwmgr->platform_descriptor.overdriveLimit.engineClock = - le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]); - hwmgr->platform_descriptor.overdriveLimit.memoryClock = - le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX]); - - phm_copy_overdrive_settings_limits_array(hwmgr, - &pptable_information->od_settings_max, - powerplay_table->ODSettingsMax, - ATOM_VEGA12_ODSETTING_COUNT); - phm_copy_overdrive_settings_limits_array(hwmgr, - &pptable_information->od_settings_min, - powerplay_table->ODSettingsMin, - ATOM_VEGA12_ODSETTING_COUNT); - - /* hwmgr->platformDescriptor.minOverdriveVDDC = 0; - hwmgr->platformDescriptor.maxOverdriveVDDC = 0; - hwmgr->platformDescriptor.overdriveVDDCStep = 0; */ - - if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 - && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport); - - pptable_information->us_small_power_limit1 = le16_to_cpu(powerplay_table->usSmallPowerLimit1); - pptable_information->us_small_power_limit2 = le16_to_cpu(powerplay_table->usSmallPowerLimit2); - pptable_information->us_boost_power_limit = le16_to_cpu(powerplay_table->usBoostPowerLimit); - pptable_information->us_od_turbo_power_limit = le16_to_cpu(powerplay_table->usODTurboPowerLimit); - pptable_information->us_od_powersave_power_limit = le16_to_cpu(powerplay_table->usODPowerSavePowerLimit); - - pptable_information->us_software_shutdown_temp = le16_to_cpu(powerplay_table->usSoftwareShutdownTemp); - - hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]); - - disable_power_control = 0; - if (!disable_power_control) { - /* enable TDP overdrive (PowerControl) feature as well if supported */ - if (hwmgr->platform_descriptor.TDPODLimit) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerControl); - } - - phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax, ATOM_VEGA12_PPCLOCK_COUNT); - phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin, ATOM_VEGA12_PPCLOCK_COUNT); - - pptable_information->smc_pptable = (PPTable_t *)kmalloc(sizeof(PPTable_t), GFP_KERNEL); - if (pptable_information->smc_pptable == NULL) - return -ENOMEM; - - memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t)); - - result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable)); - - return result; -} - -static int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr) -{ - int result = 0; - const ATOM_Vega12_POWERPLAYTABLE *powerplay_table; - - hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL); - PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), - "Failed to allocate hwmgr->pptable!", return -ENOMEM); - - powerplay_table = get_powerplay_table(hwmgr); - PP_ASSERT_WITH_CODE((powerplay_table != NULL), - "Missing PowerPlay Table!", return -1); - - result = check_powerplay_tables(hwmgr, powerplay_table); - PP_ASSERT_WITH_CODE((result == 0), - "check_powerplay_tables failed", return result); - - result = set_platform_caps(hwmgr, - le32_to_cpu(powerplay_table->ulPlatformCaps)); - PP_ASSERT_WITH_CODE((result == 0), - "set_platform_caps failed", return result); - - result = init_powerplay_table_information(hwmgr, powerplay_table); - PP_ASSERT_WITH_CODE((result == 0), - "init_powerplay_table_information failed", return result); - - return result; -} - -static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v3_information *pp_table_info = - (struct phm_ppt_v3_information *)(hwmgr->pptable); - - kfree(pp_table_info->power_saving_clock_max); - pp_table_info->power_saving_clock_max = NULL; - - kfree(pp_table_info->power_saving_clock_min); - pp_table_info->power_saving_clock_min = NULL; - - kfree(pp_table_info->od_settings_max); - pp_table_info->od_settings_max = NULL; - - kfree(pp_table_info->od_settings_min); - pp_table_info->od_settings_min = NULL; - - kfree(pp_table_info->smc_pptable); - pp_table_info->smc_pptable = NULL; - - kfree(hwmgr->pptable); - hwmgr->pptable = NULL; - - return 0; -} - -const struct pp_table_func vega12_pptable_funcs = { - .pptable_init = vega12_pp_tables_initialize, - .pptable_fini = vega12_pp_tables_uninitialize, -}; - -#if 0 -static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, - uint16_t classification, uint16_t classification2) -{ - uint32_t result = 0; - - if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT) - result |= PP_StateClassificationFlag_Boot; - - if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL) - result |= PP_StateClassificationFlag_Thermal; - - if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) - result |= PP_StateClassificationFlag_LimitedPowerSource; - - if (classification & ATOM_PPLIB_CLASSIFICATION_REST) - result |= PP_StateClassificationFlag_Rest; - - if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED) - result |= PP_StateClassificationFlag_Forced; - - if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI) - result |= PP_StateClassificationFlag_ACPI; - - if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) - result |= PP_StateClassificationFlag_LimitedPowerSource_2; - - return result; -} - -int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, - uint32_t entry_index, struct pp_power_state *power_state, - int (*call_back_func)(struct pp_hwmgr *, void *, - struct pp_power_state *, void *, uint32_t)) -{ - int result = 0; - const ATOM_Vega12_State_Array *state_arrays; - const ATOM_Vega12_State *state_entry; - const ATOM_Vega12_POWERPLAYTABLE *pp_table = - get_powerplay_table(hwmgr); - - PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!", - return -1;); - power_state->classification.bios_index = entry_index; - - if (pp_table->sHeader.format_revision >= - ATOM_Vega12_TABLE_REVISION_VEGA12) { - state_arrays = (ATOM_Vega12_State_Array *) - (((unsigned long)pp_table) + - le16_to_cpu(pp_table->usStateArrayOffset)); - - PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0, - "Invalid PowerPlay Table State Array Offset.", - return -1); - PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, - "Invalid PowerPlay Table State Array.", - return -1); - PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), - "Invalid PowerPlay Table State Array Entry.", - return -1); - - state_entry = &(state_arrays->states[entry_index]); - - result = call_back_func(hwmgr, (void *)state_entry, power_state, - (void *)pp_table, - make_classification_flags(hwmgr, - le16_to_cpu(state_entry->usClassification), - le16_to_cpu(state_entry->usClassification2))); - } - - if (!result && (power_state->classification.flags & - PP_StateClassificationFlag_Boot)) - result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); - - return result; -} -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.h deleted file mode 100644 index 65652ae65929..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA12_PROCESSPPTABLES_H -#define VEGA12_PROCESSPPTABLES_H - -#include "hwmgr.h" - -enum Vega12_I2CLineID { - Vega12_I2CLineID_DDC1 = 0x90, - Vega12_I2CLineID_DDC2 = 0x91, - Vega12_I2CLineID_DDC3 = 0x92, - Vega12_I2CLineID_DDC4 = 0x93, - Vega12_I2CLineID_DDC5 = 0x94, - Vega12_I2CLineID_DDC6 = 0x95, - Vega12_I2CLineID_SCLSDA = 0x96, - Vega12_I2CLineID_DDCVGA = 0x97 -}; - -#define Vega12_I2C_DDC1DATA 0 -#define Vega12_I2C_DDC1CLK 1 -#define Vega12_I2C_DDC2DATA 2 -#define Vega12_I2C_DDC2CLK 3 -#define Vega12_I2C_DDC3DATA 4 -#define Vega12_I2C_DDC3CLK 5 -#define Vega12_I2C_SDA 40 -#define Vega12_I2C_SCL 41 -#define Vega12_I2C_DDC4DATA 65 -#define Vega12_I2C_DDC4CLK 66 -#define Vega12_I2C_DDC5DATA 0x48 -#define Vega12_I2C_DDC5CLK 0x49 -#define Vega12_I2C_DDC6DATA 0x4a -#define Vega12_I2C_DDC6CLK 0x4b -#define Vega12_I2C_DDCVGADATA 0x4c -#define Vega12_I2C_DDCVGACLK 0x4d - -extern const struct pp_table_func vega12_pptable_funcs; -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c deleted file mode 100644 index c15b9756025d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "vega12_thermal.h" -#include "vega12_hwmgr.h" -#include "vega12_smumgr.h" -#include "vega12_ppsmc.h" -#include "vega12_inc.h" -#include "soc15_common.h" -#include "pp_debug.h" - -static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) -{ - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_GetCurrentRpm, - current_rpm), - "Attempt to get current RPM from SMC Failed!", - return -EINVAL); - - return 0; -} - -int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info) -{ - memset(fan_speed_info, 0, sizeof(*fan_speed_info)); - fan_speed_info->supports_percent_read = false; - fan_speed_info->supports_percent_write = false; - fan_speed_info->supports_rpm_read = true; - fan_speed_info->supports_rpm_write = true; - - return 0; -} - -int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) -{ - *speed = 0; - - return vega12_get_current_rpm(hwmgr, speed); -} - -/** - * @fn vega12_enable_fan_control_feature - * @brief Enables the SMC Fan Control Feature. - * - * @param hwmgr - the address of the powerplay hardware manager. - * @return 0 on success. -1 otherwise. - */ -static int vega12_enable_fan_control_feature(struct pp_hwmgr *hwmgr) -{ -#if 0 - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( - hwmgr, true, - data->smu_features[GNLD_FAN_CONTROL]. - smu_feature_bitmap), - "Attempt to Enable FAN CONTROL feature Failed!", - return -1); - data->smu_features[GNLD_FAN_CONTROL].enabled = true; - } -#endif - return 0; -} - -static int vega12_disable_fan_control_feature(struct pp_hwmgr *hwmgr) -{ -#if 0 - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( - hwmgr, false, - data->smu_features[GNLD_FAN_CONTROL]. - smu_feature_bitmap), - "Attempt to Enable FAN CONTROL feature Failed!", - return -1); - data->smu_features[GNLD_FAN_CONTROL].enabled = false; - } -#endif - return 0; -} - -int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_FAN_CONTROL].supported) - PP_ASSERT_WITH_CODE( - !vega12_enable_fan_control_feature(hwmgr), - "Attempt to Enable SMC FAN CONTROL Feature Failed!", - return -1); - - return 0; -} - - -int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_FAN_CONTROL].supported) - PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr), - "Attempt to Disable SMC FAN CONTROL Feature Failed!", - return -1); - - return 0; -} - -/** -* Reset Fan Speed to default. -* @param hwmgr the address of the powerplay hardware manager. -* @exception Always succeeds. -*/ -int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) -{ - return vega12_fan_ctrl_start_smc_fan_control(hwmgr); -} - -/** -* Reads the remote temperature from the SIslands thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int temp = 0; - - temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); - - temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> - CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; - - temp = temp & 0x1ff; - - temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - return temp; -} - -/** -* Set the requested temperature range for high and low alert signals -* -* @param hwmgr The address of the hardware manager. -* @param range Temperature range to be programmed for -* high and low alert signals -* @exception PP_Result_BadInput if the input data is not valid. -*/ -static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range) -{ - struct amdgpu_device *adev = hwmgr->adev; - int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - uint32_t val; - - if (low < range->min) - low = range->min; - if (high > range->max) - high = range->max; - - if (low > high) - return -EINVAL; - - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); - - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); - - return 0; -} - -/** -* Enable thermal alerts on the RV770 thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -static int vega12_thermal_enable_alert(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t val = 0; - - val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); - val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); - val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); - - return 0; -} - -/** -* Disable thermal alerts on the RV770 thermal controller. -* @param hwmgr The address of the hardware manager. -*/ -int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); - - return 0; -} - -/** -* Uninitialize the thermal controller. -* Currently just disables alerts. -* @param hwmgr The address of the hardware manager. -*/ -int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) -{ - int result = vega12_thermal_disable_alert(hwmgr); - - return result; -} - -/** -* Set up the fan table to control the fan using the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -static int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) -{ - int ret; - struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); - PPTable_t *table = &(data->smc_state_table.pp_table); - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFanTemperatureTarget, - (uint32_t)table->FanTargetTemperature, - NULL); - - return ret; -} - -/** -* Start the fan control on the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -static int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - /* If the fantable setup has failed we could have disabled - * PHM_PlatformCaps_MicrocodeFanControl even after - * this function was included in the table. - * Make sure that we still think controlling the fan is OK. - */ - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega12_fan_ctrl_start_smc_fan_control(hwmgr); - - return 0; -} - - -int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range) -{ - int ret = 0; - - if (range == NULL) - return -EINVAL; - - ret = vega12_thermal_set_temperature_range(hwmgr, range); - if (ret) - return -EINVAL; - - vega12_thermal_enable_alert(hwmgr); - /* We should restrict performance levels to low before we halt the SMC. - * On the other hand we are still in boot state when we do this - * so it would be pointless. - * If this assumption changes we have to revisit this table. - */ - ret = vega12_thermal_setup_fan_table(hwmgr); - if (ret) - return -EINVAL; - - vega12_thermal_start_smc_fan_control(hwmgr); - - return 0; -}; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h deleted file mode 100644 index 0d8ed039ab12..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA12_THERMAL_H -#define VEGA12_THERMAL_H - -#include "hwmgr.h" - -struct vega12_temperature { - uint16_t edge_temp; - uint16_t hot_spot_temp; - uint16_t hbm_temp; - uint16_t vr_soc_temp; - uint16_t vr_mem_temp; - uint16_t liquid1_temp; - uint16_t liquid2_temp; - uint16_t plx_temp; -}; - -#define VEGA12_THERMAL_HIGH_ALERT_MASK 0x1 -#define VEGA12_THERMAL_LOW_ALERT_MASK 0x2 - -#define VEGA12_THERMAL_MINIMUM_TEMP_READING -256 -#define VEGA12_THERMAL_MAXIMUM_TEMP_READING 255 - -#define VEGA12_THERMAL_MINIMUM_ALERT_TEMP 0 -#define VEGA12_THERMAL_MAXIMUM_ALERT_TEMP 255 - -#define FDO_PWM_MODE_STATIC 1 -#define FDO_PWM_MODE_STATIC_RPM 5 - -extern int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr); -extern int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); -extern int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info); -extern int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); -extern int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, - uint32_t *speed); -extern int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr); -extern int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range); - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c deleted file mode 100644 index 2a28c9df15a0..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "amdgpu.h" -#include "soc15.h" -#include "soc15_hw_ip.h" -#include "soc15_common.h" -#include "vega20_inc.h" -#include "vega20_ppsmc.h" -#include "vega20_baco.h" -#include "vega20_smumgr.h" - -#include "amdgpu_ras.h" - -static const struct soc15_baco_cmd_entry clean_baco_tbl[] = -{ - {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0}, - {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0}, -}; - -int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - uint32_t reg; - - *cap = false; - if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) - return 0; - - if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) { - reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); - - if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) - *cap = true; - } - - return 0; -} - -int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - uint32_t reg; - - reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); - - if (reg & BACO_CNTL__BACO_MODE_MASK) - /* gfx has already entered BACO state */ - *state = BACO_STATE_IN; - else - *state = BACO_STATE_OUT; - return 0; -} - -int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); - enum BACO_STATE cur_state; - uint32_t data; - - vega20_baco_get_state(hwmgr, &cur_state); - - if (cur_state == state) - /* aisc already in the target state */ - return 0; - - if (state == BACO_STATE_IN) { - if (!ras || !ras->supported) { - data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); - data |= 0x80000000; - WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); - - if(smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_EnterBaco, 0, NULL)) - return -EINVAL; - } else { - if(smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_EnterBaco, 1, NULL)) - return -EINVAL; - } - - } else if (state == BACO_STATE_OUT) { - if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco, NULL)) - return -EINVAL; - if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl, - ARRAY_SIZE(clean_baco_tbl))) - return -EINVAL; - } - - return 0; -} - -int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - - ret = vega20_set_pptable_driver_address(hwmgr); - if (ret) - return ret; - - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI, NULL); -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h deleted file mode 100644 index f06471e712dc..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __VEGA20_BACO_H__ -#define __VEGA20_BACO_H__ -#include "hwmgr.h" -#include "common_baco.h" - -extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); -extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); -extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); -extern int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr); - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c deleted file mode 100644 index c7216362b68d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +++ /dev/null @@ -1,4409 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/module.h> -#include <linux/slab.h> - -#include "hwmgr.h" -#include "amd_powerplay.h" -#include "vega20_smumgr.h" -#include "hardwaremanager.h" -#include "ppatomfwctrl.h" -#include "atomfirmware.h" -#include "cgs_common.h" -#include "vega20_powertune.h" -#include "vega20_inc.h" -#include "pppcielanes.h" -#include "vega20_hwmgr.h" -#include "vega20_processpptables.h" -#include "vega20_pptable.h" -#include "vega20_thermal.h" -#include "vega20_ppsmc.h" -#include "pp_debug.h" -#include "amd_pcie_helpers.h" -#include "ppinterrupt.h" -#include "pp_overdriver.h" -#include "pp_thermal.h" -#include "soc15_common.h" -#include "vega20_baco.h" -#include "smuio/smuio_9_0_offset.h" -#include "smuio/smuio_9_0_sh_mask.h" -#include "nbio/nbio_7_4_sh_mask.h" - -#define smnPCIE_LC_SPEED_CNTL 0x11140290 -#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 - -#define LINK_WIDTH_MAX 6 -#define LINK_SPEED_MAX 3 -static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; -static int link_speed[] = {25, 50, 80, 160}; - -static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - - data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT; - data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT; - data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT; - data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT; - data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT; - - data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT; - data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; - - /* - * Disable the following features for now: - * GFXCLK DS - * SOCLK DS - * LCLK DS - * DCEFCLK DS - * FCLK DS - * MP1CLK DS - * MP0CLK DS - */ - data->registry_data.disallowed_features = 0xE0041C00; - /* ECC feature should be disabled on old SMUs */ - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version); - if (hwmgr->smu_version < 0x282100) - data->registry_data.disallowed_features |= FEATURE_ECC_MASK; - - if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) - data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK; - - if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) - data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK; - - if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) - data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK; - - if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) - data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK; - - if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) - data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK; - - if (!(hwmgr->feature_mask & PP_ULV_MASK)) - data->registry_data.disallowed_features |= FEATURE_ULV_MASK; - - if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) - data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK; - - data->registry_data.od_state_in_dc_support = 0; - data->registry_data.thermal_support = 1; - data->registry_data.skip_baco_hardware = 0; - - data->registry_data.log_avfs_param = 0; - data->registry_data.sclk_throttle_low_notification = 1; - data->registry_data.force_dpm_high = 0; - data->registry_data.stable_pstate_sclk_dpm_percentage = 75; - - data->registry_data.didt_support = 0; - if (data->registry_data.didt_support) { - data->registry_data.didt_mode = 6; - data->registry_data.sq_ramping_support = 1; - data->registry_data.db_ramping_support = 0; - data->registry_data.td_ramping_support = 0; - data->registry_data.tcp_ramping_support = 0; - data->registry_data.dbr_ramping_support = 0; - data->registry_data.edc_didt_support = 1; - data->registry_data.gc_didt_support = 0; - data->registry_data.psm_didt_support = 0; - } - - data->registry_data.pcie_lane_override = 0xff; - data->registry_data.pcie_speed_override = 0xff; - data->registry_data.pcie_clock_override = 0xffffffff; - data->registry_data.regulator_hot_gpio_support = 1; - data->registry_data.ac_dc_switch_gpio_support = 0; - data->registry_data.quick_transition_support = 0; - data->registry_data.zrpm_start_temp = 0xffff; - data->registry_data.zrpm_stop_temp = 0xffff; - data->registry_data.od8_feature_enable = 1; - data->registry_data.disable_water_mark = 0; - data->registry_data.disable_pp_tuning = 0; - data->registry_data.disable_xlpp_tuning = 0; - data->registry_data.disable_workload_policy = 0; - data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; - data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; - data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; - data->registry_data.force_workload_policy_mask = 0; - data->registry_data.disable_3d_fs_detection = 0; - data->registry_data.fps_support = 1; - data->registry_data.disable_auto_wattman = 1; - data->registry_data.auto_wattman_debug = 0; - data->registry_data.auto_wattman_sample_period = 100; - data->registry_data.fclk_gfxclk_ratio = 0; - data->registry_data.auto_wattman_threshold = 50; - data->registry_data.gfxoff_controlled_by_driver = 1; - data->gfxoff_allowed = false; - data->counter_gfxoff = 0; -} - -static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct amdgpu_device *adev = hwmgr->adev; - - if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_BACO); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableSMU7ThermalManagement); - - if (adev->pg_flags & AMD_PG_SUPPORT_UVD) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - - if (adev->pg_flags & AMD_PG_SUPPORT_VCE) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UnTabledHardwareInterface); - - if (data->registry_data.od8_feature_enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD8inACSupport); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ActivityReporting); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM); - - if (data->registry_data.od_state_in_dc_support) { - if (data->registry_data.od8_feature_enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD8inDCSupport); - } - - if (data->registry_data.thermal_support && - data->registry_data.fuzzy_fan_control_support && - hwmgr->thermal_controller.advanceFanControlParameters.usTMax) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPowerManagement); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMC); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalPolicyDelay); - - if (data->registry_data.force_dpm_high) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ExclusiveModeAlwaysHigh); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicUVDState); - - if (data->registry_data.sclk_throttle_low_notification) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification); - - /* power tune caps */ - /* assume disabled */ - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtSupport); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtEDCEnable); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_GCEDC); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PSM); - - if (data->registry_data.didt_support) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtSupport); - if (data->registry_data.sq_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - if (data->registry_data.db_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - if (data->registry_data.td_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - if (data->registry_data.tcp_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - if (data->registry_data.dbr_ramping_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRRamping); - if (data->registry_data.edc_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DiDtEDCEnable); - if (data->registry_data.gc_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_GCEDC); - if (data->registry_data.psm_didt_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PSM); - } - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot); - - if (data->registry_data.ac_dc_switch_gpio_support) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); - } - - if (data->registry_data.quick_transition_support) { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_Falcon_QuickTransition); - } - - if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_LowestUclkReservedForUlv); - if (data->lowest_uclk_reserved_for_ulv == 1) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_LowestUclkReservedForUlv); - } - - if (data->registry_data.custom_fan_support) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CustomFanControlSupport); - - return 0; -} - -static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct amdgpu_device *adev = hwmgr->adev; - uint32_t top32, bottom32; - int i; - - data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = - FEATURE_DPM_PREFETCHER_BIT; - data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = - FEATURE_DPM_GFXCLK_BIT; - data->smu_features[GNLD_DPM_UCLK].smu_feature_id = - FEATURE_DPM_UCLK_BIT; - data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = - FEATURE_DPM_SOCCLK_BIT; - data->smu_features[GNLD_DPM_UVD].smu_feature_id = - FEATURE_DPM_UVD_BIT; - data->smu_features[GNLD_DPM_VCE].smu_feature_id = - FEATURE_DPM_VCE_BIT; - data->smu_features[GNLD_ULV].smu_feature_id = - FEATURE_ULV_BIT; - data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = - FEATURE_DPM_MP0CLK_BIT; - data->smu_features[GNLD_DPM_LINK].smu_feature_id = - FEATURE_DPM_LINK_BIT; - data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = - FEATURE_DPM_DCEFCLK_BIT; - data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = - FEATURE_DS_GFXCLK_BIT; - data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = - FEATURE_DS_SOCCLK_BIT; - data->smu_features[GNLD_DS_LCLK].smu_feature_id = - FEATURE_DS_LCLK_BIT; - data->smu_features[GNLD_PPT].smu_feature_id = - FEATURE_PPT_BIT; - data->smu_features[GNLD_TDC].smu_feature_id = - FEATURE_TDC_BIT; - data->smu_features[GNLD_THERMAL].smu_feature_id = - FEATURE_THERMAL_BIT; - data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = - FEATURE_GFX_PER_CU_CG_BIT; - data->smu_features[GNLD_RM].smu_feature_id = - FEATURE_RM_BIT; - data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = - FEATURE_DS_DCEFCLK_BIT; - data->smu_features[GNLD_ACDC].smu_feature_id = - FEATURE_ACDC_BIT; - data->smu_features[GNLD_VR0HOT].smu_feature_id = - FEATURE_VR0HOT_BIT; - data->smu_features[GNLD_VR1HOT].smu_feature_id = - FEATURE_VR1HOT_BIT; - data->smu_features[GNLD_FW_CTF].smu_feature_id = - FEATURE_FW_CTF_BIT; - data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = - FEATURE_LED_DISPLAY_BIT; - data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = - FEATURE_FAN_CONTROL_BIT; - data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; - data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; - data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; - data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT; - data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT; - data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT; - data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT; - data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT; - data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT; - - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - data->smu_features[i].smu_feature_bitmap = - (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); - data->smu_features[i].allowed = - ((data->registry_data.disallowed_features >> i) & 1) ? - false : true; - } - - /* Get the SN to turn into a Unique ID */ - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); - - adev->unique_id = ((uint64_t)bottom32 << 32) | top32; -} - -static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) -{ - return 0; -} - -static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) -{ - kfree(hwmgr->backend); - hwmgr->backend = NULL; - - return 0; -} - -static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data; - struct amdgpu_device *adev = hwmgr->adev; - - data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - - hwmgr->backend = data; - - hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; - hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - - vega20_set_default_registry_data(hwmgr); - - data->disable_dpm_mask = 0xff; - - /* need to set voltage control types before EVV patching */ - data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE; - data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE; - data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE; - - data->water_marks_bitmap = 0; - data->avfs_exist = false; - - vega20_set_features_platform_caps(hwmgr); - - vega20_init_dpm_defaults(hwmgr); - - /* Parse pptable data read from VBIOS */ - vega20_set_private_data_based_on_pptable(hwmgr); - - data->is_tlu_enabled = false; - - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = - VEGA20_MAX_HARDWARE_POWERLEVELS; - hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; - hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - - hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ - /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ - hwmgr->platform_descriptor.clockStep.engineClock = 500; - hwmgr->platform_descriptor.clockStep.memoryClock = 500; - - data->total_active_cus = adev->gfx.cu_info.number; - data->is_custom_profile_set = false; - - return 0; -} - -static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - - data->low_sclk_interrupt_threshold = 0; - - return 0; -} - -static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - int ret = 0; - bool use_baco = (adev->in_gpu_reset && - (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || - (adev->in_runpm && amdgpu_asic_supports_baco(adev)); - - ret = vega20_init_sclk_threshold(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "Failed to init sclk threshold!", - return ret); - - if (use_baco) { - ret = vega20_baco_apply_vdci_flush_workaround(hwmgr); - if (ret) - pr_err("Failed to apply vega20 baco workaround!\n"); - } - - return ret; -} - -/* - * @fn vega20_init_dpm_state - * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. - * - * @param dpm_state - the address of the DPM Table to initiailize. - * @return None. - */ -static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state) -{ - dpm_state->soft_min_level = 0x0; - dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_state->hard_min_level = 0x0; - dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT; -} - -static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, - PPCLK_e clk_id, uint32_t *num_of_levels) -{ - int ret = 0; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmFreqByIndex, - (clk_id << 16 | 0xFF), - num_of_levels); - PP_ASSERT_WITH_CODE(!ret, - "[GetNumOfDpmLevel] failed to get dpm levels!", - return ret); - - return ret; -} - -static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, - PPCLK_e clk_id, uint32_t index, uint32_t *clk) -{ - int ret = 0; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmFreqByIndex, - (clk_id << 16 | index), - clk); - PP_ASSERT_WITH_CODE(!ret, - "[GetDpmFreqByIndex] failed to get dpm freq by index!", - return ret); - - return ret; -} - -static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, - struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) -{ - int ret = 0; - uint32_t i, num_of_levels, clk; - - ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); - PP_ASSERT_WITH_CODE(!ret, - "[SetupSingleDpmTable] failed to get clk levels!", - return ret); - - dpm_table->count = num_of_levels; - - for (i = 0; i < num_of_levels; i++) { - ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); - PP_ASSERT_WITH_CODE(!ret, - "[SetupSingleDpmTable] failed to get clk of specific level!", - return ret); - dpm_table->dpm_levels[i].value = clk; - dpm_table->dpm_levels[i].enabled = true; - } - - return ret; -} - -static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table; - int ret = 0; - - dpm_table = &(data->dpm_table.gfx_table); - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; - } - - return ret; -} - -static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table; - int ret = 0; - - dpm_table = &(data->dpm_table.mem_table); - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get memclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; - } - - return ret; -} - -/* - * This function is to initialize all DPM state tables - * for SMU based on the dependency table. - * Dynamic state patching function will then trim these - * state tables to the allowed range based - * on the power policy or external client requests, - * such as UVD request, etc. - */ -static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table; - int ret = 0; - - memset(&data->dpm_table, 0, sizeof(data->dpm_table)); - - /* socclk */ - dpm_table = &(data->dpm_table.soc_table); - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get socclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; - } - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* gfxclk */ - dpm_table = &(data->dpm_table.gfx_table); - ret = vega20_setup_gfxclk_dpm_table(hwmgr); - if (ret) - return ret; - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* memclk */ - dpm_table = &(data->dpm_table.mem_table); - ret = vega20_setup_memclk_dpm_table(hwmgr); - if (ret) - return ret; - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* eclk */ - dpm_table = &(data->dpm_table.eclk_table); - if (data->smu_features[GNLD_DPM_VCE].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get eclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; - } - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* vclk */ - dpm_table = &(data->dpm_table.vclk_table); - if (data->smu_features[GNLD_DPM_UVD].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get vclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; - } - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* dclk */ - dpm_table = &(data->dpm_table.dclk_table); - if (data->smu_features[GNLD_DPM_UVD].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get dclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; - } - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* dcefclk */ - dpm_table = &(data->dpm_table.dcef_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; - } - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* pixclk */ - dpm_table = &(data->dpm_table.pixel_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", - return ret); - } else - dpm_table->count = 0; - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* dispclk */ - dpm_table = &(data->dpm_table.display_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", - return ret); - } else - dpm_table->count = 0; - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* phyclk */ - dpm_table = &(data->dpm_table.phy_table); - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", - return ret); - } else - dpm_table->count = 0; - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* fclk */ - dpm_table = &(data->dpm_table.fclk_table); - if (data->smu_features[GNLD_DPM_FCLK].enabled) { - ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK); - PP_ASSERT_WITH_CODE(!ret, - "[SetupDefaultDpmTable] failed to get fclk dpm levels!", - return ret); - } else { - dpm_table->count = 1; - dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100; - } - vega20_init_dpm_state(&(dpm_table->dpm_state)); - - /* save a copy of the default DPM table */ - memcpy(&(data->golden_dpm_table), &(data->dpm_table), - sizeof(struct vega20_dpm_table)); - - return 0; -} - -/** -* Initializes the SMC table and uploads it -* -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data (PowerState) -* @return always 0 -*/ -static int vega20_init_smc_table(struct pp_hwmgr *hwmgr) -{ - int result; - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct pp_atomfwctrl_bios_boot_up_values boot_up_values; - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - - result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); - PP_ASSERT_WITH_CODE(!result, - "[InitSMCTable] Failed to get vbios bootup values!", - return result); - - data->vbios_boot_state.vddc = boot_up_values.usVddc; - data->vbios_boot_state.vddci = boot_up_values.usVddci; - data->vbios_boot_state.mvddc = boot_up_values.usMvddc; - data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; - data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; - data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; - data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; - data->vbios_boot_state.eclock = boot_up_values.ulEClk; - data->vbios_boot_state.vclock = boot_up_values.ulVClk; - data->vbios_boot_state.dclock = boot_up_values.ulDClk; - data->vbios_boot_state.fclock = boot_up_values.ulFClk; - data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetMinDeepSleepDcefclk, - (uint32_t)(data->vbios_boot_state.dcef_clock / 100), - NULL); - - memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); - - result = smum_smc_table_manager(hwmgr, - (uint8_t *)pp_table, TABLE_PPTABLE, false); - PP_ASSERT_WITH_CODE(!result, - "[InitSMCTable] Failed to upload PPtable!", - return result); - - return 0; -} - -/* - * Override PCIe link speed and link width for DPM Level 1. PPTable entries - * reflect the ASIC capabilities and not the system capabilities. For e.g. - * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch - * to DPM1, it fails as system doesn't support Gen4. - */ -static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg; - int ret; - - if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) - pcie_gen = 3; - else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - pcie_gen = 2; - else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) - pcie_gen = 1; - else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) - pcie_gen = 0; - - if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) - pcie_width = 6; - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) - pcie_width = 5; - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) - pcie_width = 4; - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) - pcie_width = 3; - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) - pcie_width = 2; - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) - pcie_width = 1; - - /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 - * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 - * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 - */ - smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width; - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, - NULL); - PP_ASSERT_WITH_CODE(!ret, - "[OverridePcieParameters] Attempt to override pcie params failed!", - return ret); - - data->pcie_parameters_override = true; - data->pcie_gen_level1 = pcie_gen; - data->pcie_width_level1 = pcie_width; - - return 0; -} - -static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t allowed_features_low = 0, allowed_features_high = 0; - int i; - int ret = 0; - - for (i = 0; i < GNLD_FEATURES_MAX; i++) - if (data->smu_features[i].allowed) - data->smu_features[i].smu_feature_id > 31 ? - (allowed_features_high |= - ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) - & 0xFFFFFFFF)) : - (allowed_features_low |= - ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) - & 0xFFFFFFFF)); - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, NULL); - PP_ASSERT_WITH_CODE(!ret, - "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!", - return ret); - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, NULL); - PP_ASSERT_WITH_CODE(!ret, - "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", - return ret); - - return 0; -} - -static int vega20_run_btc(struct pp_hwmgr *hwmgr) -{ - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc, NULL); -} - -static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr) -{ - return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc, NULL); -} - -static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint64_t features_enabled; - int i; - bool enabled; - int ret = 0; - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_EnableAllSmuFeatures, - NULL)) == 0, - "[EnableAllSMUFeatures] Failed to enable all smu features!", - return ret); - - ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); - PP_ASSERT_WITH_CODE(!ret, - "[EnableAllSmuFeatures] Failed to get enabled smc features!", - return ret); - - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? - true : false; - data->smu_features[i].enabled = enabled; - data->smu_features[i].supported = enabled; - -#if 0 - if (data->smu_features[i].allowed && !enabled) - pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i); - else if (!data->smu_features[i].allowed && enabled) - pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i); -#endif - } - - return 0; -} - -static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_DPM_UCLK].enabled) - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetUclkFastSwitch, - 1, - NULL); - - return 0; -} - -static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFclkGfxClkRatio, - data->registry_data.fclk_gfxclk_ratio, - NULL); -} - -static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - int i, ret = 0; - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_DisableAllSmuFeatures, - NULL)) == 0, - "[DisableAllSMUFeatures] Failed to disable all smu features!", - return ret); - - for (i = 0; i < GNLD_FEATURES_MAX; i++) - data->smu_features[i].enabled = 0; - - return 0; -} - -static int vega20_od8_set_feature_capabilities( - struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - struct vega20_od8_settings *od_settings = &(data->od8_settings); - - od_settings->overdrive8_capabilities = 0; - - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] && - pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 && - pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 && - (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >= - pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) - od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS; - - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] && - (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >= - pp_table->MinVoltageGfx / VOLTAGE_SCALE) && - (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <= - pp_table->MaxVoltageGfx / VOLTAGE_SCALE) && - (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >= - pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1])) - od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE; - } - - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] = - data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value; - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] && - pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 && - pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 && - (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >= - pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX])) - od_settings->overdrive8_capabilities |= OD8_UCLK_MAX; - } - - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] && - pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 && - pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 && - pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 && - pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100) - od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT; - - if (data->smu_features[GNLD_FAN_CONTROL].enabled) { - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] && - pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 && - pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 && - (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >= - pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) - od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK; - - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] && - (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >= - (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) && - pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 && - (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >= - pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) - od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN; - } - - if (data->smu_features[GNLD_THERMAL].enabled) { - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] && - pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 && - pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 && - (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >= - pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) - od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN; - - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] && - pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 && - pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 && - (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >= - pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) - od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM; - } - - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE]) - od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE; - - if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] && - pp_table->FanZeroRpmEnable) - od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL; - - if (!od_settings->overdrive8_capabilities) - hwmgr->od_enabled = false; - - return 0; -} - -static int vega20_od8_set_feature_id( - struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_od8_settings *od_settings = &(data->od8_settings); - - if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) { - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id = - OD8_GFXCLK_LIMITS; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id = - OD8_GFXCLK_LIMITS; - } else { - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id = - 0; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id = - 0; - } - - if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) { - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id = - OD8_GFXCLK_CURVE; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id = - OD8_GFXCLK_CURVE; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id = - OD8_GFXCLK_CURVE; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id = - OD8_GFXCLK_CURVE; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id = - OD8_GFXCLK_CURVE; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id = - OD8_GFXCLK_CURVE; - } else { - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id = - 0; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id = - 0; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id = - 0; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id = - 0; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id = - 0; - od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id = - 0; - } - - if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX) - od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX; - else - od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0; - - if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT) - od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT; - else - od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0; - - if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK) - od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id = - OD8_ACOUSTIC_LIMIT_SCLK; - else - od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id = - 0; - - if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN) - od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id = - OD8_FAN_SPEED_MIN; - else - od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id = - 0; - - if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN) - od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id = - OD8_TEMPERATURE_FAN; - else - od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id = - 0; - - if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM) - od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id = - OD8_TEMPERATURE_SYSTEM; - else - od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id = - 0; - - return 0; -} - -static int vega20_od8_get_gfx_clock_base_voltage( - struct pp_hwmgr *hwmgr, - uint32_t *voltage, - uint32_t freq) -{ - int ret = 0; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetAVFSVoltageByDpm, - ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq), - voltage); - PP_ASSERT_WITH_CODE(!ret, - "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!", - return ret); - - *voltage = *voltage / VOLTAGE_SCALE; - - return 0; -} - -static int vega20_od8_initialize_default_settings( - struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_od8_settings *od8_settings = &(data->od8_settings); - OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); - int i, ret = 0; - - /* Set Feature Capabilities */ - vega20_od8_set_feature_capabilities(hwmgr); - - /* Map FeatureID to individual settings */ - vega20_od8_set_feature_id(hwmgr); - - /* Set default values */ - ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true); - PP_ASSERT_WITH_CODE(!ret, - "Failed to export over drive table!", - return ret); - - if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) { - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value = - od_table->GfxclkFmin; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value = - od_table->GfxclkFmax; - } else { - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value = - 0; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value = - 0; - } - - if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) { - od_table->GfxclkFreq1 = od_table->GfxclkFmin; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value = - od_table->GfxclkFreq1; - - od_table->GfxclkFreq3 = od_table->GfxclkFmax; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value = - od_table->GfxclkFreq3; - - od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value = - od_table->GfxclkFreq2; - - PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, - &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value), - od_table->GfxclkFreq1), - "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0); - od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value - * VOLTAGE_SCALE; - - PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, - &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value), - od_table->GfxclkFreq2), - "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0); - od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value - * VOLTAGE_SCALE; - - PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, - &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value), - od_table->GfxclkFreq3), - "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0); - od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value - * VOLTAGE_SCALE; - } else { - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value = - 0; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = - 0; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value = - 0; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = - 0; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value = - 0; - od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = - 0; - } - - if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX) - od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value = - od_table->UclkFmax; - else - od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value = - 0; - - if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT) - od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value = - od_table->OverDrivePct; - else - od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value = - 0; - - if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK) - od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value = - od_table->FanMaximumRpm; - else - od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value = - 0; - - if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN) - od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value = - od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100; - else - od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value = - 0; - - if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN) - od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value = - od_table->FanTargetTemperature; - else - od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value = - 0; - - if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM) - od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value = - od_table->MaxOpTemp; - else - od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value = - 0; - - for (i = 0; i < OD8_SETTING_COUNT; i++) { - if (od8_settings->od8_settings_array[i].feature_id) { - od8_settings->od8_settings_array[i].min_value = - pptable_information->od_settings_min[i]; - od8_settings->od8_settings_array[i].max_value = - pptable_information->od_settings_max[i]; - od8_settings->od8_settings_array[i].current_value = - od8_settings->od8_settings_array[i].default_value; - } else { - od8_settings->od8_settings_array[i].min_value = - 0; - od8_settings->od8_settings_array[i].max_value = - 0; - od8_settings->od8_settings_array[i].current_value = - 0; - } - } - - ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false); - PP_ASSERT_WITH_CODE(!ret, - "Failed to import over drive table!", - return ret); - - return 0; -} - -static int vega20_od8_set_settings( - struct pp_hwmgr *hwmgr, - uint32_t index, - uint32_t value) -{ - OverDriveTable_t od_table; - int ret = 0; - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_od8_single_setting *od8_settings = - data->od8_settings.od8_settings_array; - - ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true); - PP_ASSERT_WITH_CODE(!ret, - "Failed to export over drive table!", - return ret); - - switch(index) { - case OD8_SETTING_GFXCLK_FMIN: - od_table.GfxclkFmin = (uint16_t)value; - break; - case OD8_SETTING_GFXCLK_FMAX: - if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value || - value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) - return -EINVAL; - - od_table.GfxclkFmax = (uint16_t)value; - break; - case OD8_SETTING_GFXCLK_FREQ1: - od_table.GfxclkFreq1 = (uint16_t)value; - break; - case OD8_SETTING_GFXCLK_VOLTAGE1: - od_table.GfxclkVolt1 = (uint16_t)value; - break; - case OD8_SETTING_GFXCLK_FREQ2: - od_table.GfxclkFreq2 = (uint16_t)value; - break; - case OD8_SETTING_GFXCLK_VOLTAGE2: - od_table.GfxclkVolt2 = (uint16_t)value; - break; - case OD8_SETTING_GFXCLK_FREQ3: - od_table.GfxclkFreq3 = (uint16_t)value; - break; - case OD8_SETTING_GFXCLK_VOLTAGE3: - od_table.GfxclkVolt3 = (uint16_t)value; - break; - case OD8_SETTING_UCLK_FMAX: - if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value || - value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) - return -EINVAL; - od_table.UclkFmax = (uint16_t)value; - break; - case OD8_SETTING_POWER_PERCENTAGE: - od_table.OverDrivePct = (int16_t)value; - break; - case OD8_SETTING_FAN_ACOUSTIC_LIMIT: - od_table.FanMaximumRpm = (uint16_t)value; - break; - case OD8_SETTING_FAN_MIN_SPEED: - od_table.FanMinimumPwm = (uint16_t)value; - break; - case OD8_SETTING_FAN_TARGET_TEMP: - od_table.FanTargetTemperature = (uint16_t)value; - break; - case OD8_SETTING_OPERATING_TEMP_MAX: - od_table.MaxOpTemp = (uint16_t)value; - break; - } - - ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false); - PP_ASSERT_WITH_CODE(!ret, - "Failed to import over drive table!", - return ret); - - return 0; -} - -static int vega20_get_sclk_od( - struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = hwmgr->backend; - struct vega20_single_dpm_table *sclk_table = - &(data->dpm_table.gfx_table); - struct vega20_single_dpm_table *golden_sclk_table = - &(data->golden_dpm_table.gfx_table); - int value = sclk_table->dpm_levels[sclk_table->count - 1].value; - int golden_value = golden_sclk_table->dpm_levels - [golden_sclk_table->count - 1].value; - - /* od percentage */ - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int vega20_set_sclk_od( - struct pp_hwmgr *hwmgr, uint32_t value) -{ - struct vega20_hwmgr *data = hwmgr->backend; - struct vega20_single_dpm_table *golden_sclk_table = - &(data->golden_dpm_table.gfx_table); - uint32_t od_sclk; - int ret = 0; - - od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value; - od_sclk /= 100; - od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; - - ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk); - PP_ASSERT_WITH_CODE(!ret, - "[SetSclkOD] failed to set od gfxclk!", - return ret); - - /* retrieve updated gfxclk table */ - ret = vega20_setup_gfxclk_dpm_table(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "[SetSclkOD] failed to refresh gfxclk table!", - return ret); - - return 0; -} - -static int vega20_get_mclk_od( - struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = hwmgr->backend; - struct vega20_single_dpm_table *mclk_table = - &(data->dpm_table.mem_table); - struct vega20_single_dpm_table *golden_mclk_table = - &(data->golden_dpm_table.mem_table); - int value = mclk_table->dpm_levels[mclk_table->count - 1].value; - int golden_value = golden_mclk_table->dpm_levels - [golden_mclk_table->count - 1].value; - - /* od percentage */ - value -= golden_value; - value = DIV_ROUND_UP(value * 100, golden_value); - - return value; -} - -static int vega20_set_mclk_od( - struct pp_hwmgr *hwmgr, uint32_t value) -{ - struct vega20_hwmgr *data = hwmgr->backend; - struct vega20_single_dpm_table *golden_mclk_table = - &(data->golden_dpm_table.mem_table); - uint32_t od_mclk; - int ret = 0; - - od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value; - od_mclk /= 100; - od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; - - ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk); - PP_ASSERT_WITH_CODE(!ret, - "[SetMclkOD] failed to set od memclk!", - return ret); - - /* retrieve updated memclk table */ - ret = vega20_setup_memclk_dpm_table(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "[SetMclkOD] failed to refresh memclk table!", - return ret); - - return 0; -} - -static int vega20_populate_umdpstate_clocks( - struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); - struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); - - hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; - hwmgr->pstate_mclk = mem_table->dpm_levels[0].value; - - if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && - mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) { - hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; - hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; - } - - hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100; - hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100; - - return 0; -} - -static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr, - PP_Clock *clock, PPCLK_e clock_select) -{ - int ret = 0; - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDcModeMaxDpmFreq, - (clock_select << 16), - clock)) == 0, - "[GetMaxSustainableClock] Failed to get max DC clock from SMC!", - return ret); - - /* if DC limit is zero, return AC limit */ - if (*clock == 0) { - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetMaxDpmFreq, - (clock_select << 16), - clock)) == 0, - "[GetMaxSustainableClock] failed to get max AC clock from SMC!", - return ret); - } - - return 0; -} - -static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_max_sustainable_clocks *max_sustainable_clocks = - &(data->max_sustainable_clocks); - int ret = 0; - - max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100; - max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100; - max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100; - max_sustainable_clocks->display_clock = 0xFFFFFFFF; - max_sustainable_clocks->phy_clock = 0xFFFFFFFF; - max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; - - if (data->smu_features[GNLD_DPM_UCLK].enabled) - PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, - &(max_sustainable_clocks->uclock), - PPCLK_UCLK)) == 0, - "[InitMaxSustainableClocks] failed to get max UCLK from SMC!", - return ret); - - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) - PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, - &(max_sustainable_clocks->soc_clock), - PPCLK_SOCCLK)) == 0, - "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!", - return ret); - - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, - &(max_sustainable_clocks->dcef_clock), - PPCLK_DCEFCLK)) == 0, - "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!", - return ret); - PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, - &(max_sustainable_clocks->display_clock), - PPCLK_DISPCLK)) == 0, - "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!", - return ret); - PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, - &(max_sustainable_clocks->phy_clock), - PPCLK_PHYCLK)) == 0, - "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!", - return ret); - PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, - &(max_sustainable_clocks->pixel_clock), - PPCLK_PIXCLK)) == 0, - "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!", - return ret); - } - - if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) - max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; - - return 0; -} - -static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr) -{ - int result; - - result = smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_SetMGpuFanBoostLimitRpm, - NULL); - PP_ASSERT_WITH_CODE(!result, - "[EnableMgpuFan] Failed to enable mgpu fan boost!", - return result); - - return 0; -} - -static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - - data->uvd_power_gated = true; - data->vce_power_gated = true; -} - -static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int result = 0; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, 0, NULL); - - result = vega20_set_allowed_featuresmask(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to set allowed featuresmask!\n", - return result); - - result = vega20_init_smc_table(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to initialize SMC table!", - return result); - - result = vega20_run_btc(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to run btc!", - return result); - - result = vega20_run_btc_afll(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to run btc afll!", - return result); - - result = vega20_enable_all_smu_features(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to enable all smu features!", - return result); - - result = vega20_override_pcie_parameters(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to override pcie parameters!", - return result); - - result = vega20_notify_smc_display_change(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to notify smc display change!", - return result); - - result = vega20_send_clock_ratio(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to send clock ratio!", - return result); - - /* Initialize UVD/VCE powergating state */ - vega20_init_powergate_state(hwmgr); - - result = vega20_setup_default_dpm_tables(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to setup default DPM tables!", - return result); - - result = vega20_init_max_sustainable_clocks(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to get maximum sustainable clocks!", - return result); - - result = vega20_power_control_set_level(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to power control set level!", - return result); - - result = vega20_od8_initialize_default_settings(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to initialize odn settings!", - return result); - - result = vega20_populate_umdpstate_clocks(hwmgr); - PP_ASSERT_WITH_CODE(!result, - "[EnableDPMTasks] Failed to populate umdpstate clocks!", - return result); - - result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit, - POWER_SOURCE_AC << 16, &hwmgr->default_power_limit); - PP_ASSERT_WITH_CODE(!result, - "[GetPptLimit] get default PPT limit failed!", - return result); - hwmgr->power_limit = - hwmgr->default_power_limit; - - return 0; -} - -static uint32_t vega20_find_lowest_dpm_level( - struct vega20_single_dpm_table *table) -{ - uint32_t i; - - for (i = 0; i < table->count; i++) { - if (table->dpm_levels[i].enabled) - break; - } - if (i >= table->count) { - i = 0; - table->dpm_levels[i].enabled = true; - } - - return i; -} - -static uint32_t vega20_find_highest_dpm_level( - struct vega20_single_dpm_table *table) -{ - int i = 0; - - PP_ASSERT_WITH_CODE(table != NULL, - "[FindHighestDPMLevel] DPM Table does not exist!", - return 0); - PP_ASSERT_WITH_CODE(table->count > 0, - "[FindHighestDPMLevel] DPM Table has no entry!", - return 0); - PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, - "[FindHighestDPMLevel] DPM Table has too many entries!", - return MAX_REGULAR_DPM_NUMBER - 1); - - for (i = table->count - 1; i >= 0; i--) { - if (table->dpm_levels[i].enabled) - break; - } - if (i < 0) { - i = 0; - table->dpm_levels[i].enabled = true; - } - - return i; -} - -static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t min_freq; - int ret = 0; - - if (data->smu_features[GNLD_DPM_GFXCLK].enabled && - (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { - min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min gfxclk !", - return ret); - } - - if (data->smu_features[GNLD_DPM_UCLK].enabled && - (feature_mask & FEATURE_DPM_UCLK_MASK)) { - min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_UCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min memclk !", - return ret); - } - - if (data->smu_features[GNLD_DPM_UVD].enabled && - (feature_mask & FEATURE_DPM_UVD_MASK)) { - min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_VCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min vclk!", - return ret); - - min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_DCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min dclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_VCE].enabled && - (feature_mask & FEATURE_DPM_VCE_MASK)) { - min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_ECLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min eclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_SOCCLK].enabled && - (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { - min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min socclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_FCLK].enabled && - (feature_mask & FEATURE_DPM_FCLK_MASK)) { - min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_FCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set soft min fclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled && - (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) { - min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetHardMinByFreq, - (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), - NULL)), - "Failed to set hard min dcefclk!", - return ret); - } - - return ret; -} - -static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t max_freq; - int ret = 0; - - if (data->smu_features[GNLD_DPM_GFXCLK].enabled && - (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { - max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max gfxclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_UCLK].enabled && - (feature_mask & FEATURE_DPM_UCLK_MASK)) { - max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_UCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max memclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_UVD].enabled && - (feature_mask & FEATURE_DPM_UVD_MASK)) { - max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_VCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max vclk!", - return ret); - - max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_DCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max dclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_VCE].enabled && - (feature_mask & FEATURE_DPM_VCE_MASK)) { - max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_ECLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max eclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_SOCCLK].enabled && - (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { - max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max socclk!", - return ret); - } - - if (data->smu_features[GNLD_DPM_FCLK].enabled && - (feature_mask & FEATURE_DPM_FCLK_MASK)) { - max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level; - - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetSoftMaxByFreq, - (PPCLK_FCLK << 16) | (max_freq & 0xffff), - NULL)), - "Failed to set soft max fclk!", - return ret); - } - - return ret; -} - -static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (data->smu_features[GNLD_DPM_VCE].supported) { - if (data->smu_features[GNLD_DPM_VCE].enabled == enable) { - if (enable) - PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n"); - else - PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n"); - } - - ret = vega20_enable_smc_features(hwmgr, - enable, - data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap); - PP_ASSERT_WITH_CODE(!ret, - "Attempt to Enable/Disable DPM VCE Failed!", - return ret); - data->smu_features[GNLD_DPM_VCE].enabled = enable; - } - - return 0; -} - -static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr, - uint32_t *clock, - PPCLK_e clock_select, - bool max) -{ - int ret; - *clock = 0; - - if (max) { - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16), - clock)) == 0, - "[GetClockRanges] Failed to get max clock from SMC!", - return ret); - } else { - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetMinDpmFreq, - (clock_select << 16), - clock)) == 0, - "[GetClockRanges] Failed to get min clock from SMC!", - return ret); - } - - return 0; -} - -static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t gfx_clk; - int ret = 0; - - PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled, - "[GetSclks]: gfxclk dpm not enabled!\n", - return -EPERM); - - if (low) { - ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false); - PP_ASSERT_WITH_CODE(!ret, - "[GetSclks]: fail to get min PPCLK_GFXCLK\n", - return ret); - } else { - ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true); - PP_ASSERT_WITH_CODE(!ret, - "[GetSclks]: fail to get max PPCLK_GFXCLK\n", - return ret); - } - - return (gfx_clk * 100); -} - -static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t mem_clk; - int ret = 0; - - PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled, - "[MemMclks]: memclk dpm not enabled!\n", - return -EPERM); - - if (low) { - ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false); - PP_ASSERT_WITH_CODE(!ret, - "[GetMclks]: fail to get min PPCLK_UCLK\n", - return ret); - } else { - ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true); - PP_ASSERT_WITH_CODE(!ret, - "[GetMclks]: fail to get max PPCLK_UCLK\n", - return ret); - } - - return (mem_clk * 100); -} - -static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, - SmuMetrics_t *metrics_table, - bool bypass_cache) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (bypass_cache || - !data->metrics_time || - time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { - ret = smum_smc_table_manager(hwmgr, - (uint8_t *)(&data->metrics_table), - TABLE_SMU_METRICS, - true); - if (ret) { - pr_info("Failed to export SMU metrics table!\n"); - return ret; - } - data->metrics_time = jiffies; - } - - if (metrics_table) - memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); - - return ret; -} - -static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr, - uint32_t *query) -{ - int ret = 0; - SmuMetrics_t metrics_table; - - ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - /* For the 40.46 release, they changed the value name */ - if (hwmgr->smu_version == 0x282e00) - *query = metrics_table.AverageSocketPower << 8; - else - *query = metrics_table.CurrSocketPower << 8; - - return ret; -} - -static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr, - PPCLK_e clk_id, uint32_t *clk_freq) -{ - int ret = 0; - - *clk_freq = 0; - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetDpmClockFreq, (clk_id << 16), - clk_freq)) == 0, - "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!", - return ret); - - *clk_freq = *clk_freq * 100; - - return 0; -} - -static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr, - int idx, - uint32_t *activity_percent) -{ - int ret = 0; - SmuMetrics_t metrics_table; - - ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - switch (idx) { - case AMDGPU_PP_SENSOR_GPU_LOAD: - *activity_percent = metrics_table.AverageGfxActivity; - break; - case AMDGPU_PP_SENSOR_MEM_LOAD: - *activity_percent = metrics_table.AverageUclkActivity; - break; - default: - pr_err("Invalid index for retrieving clock activity\n"); - return -EINVAL; - } - - return ret; -} - -static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx, - void *value, int *size) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct amdgpu_device *adev = hwmgr->adev; - SmuMetrics_t metrics_table; - uint32_t val_vid; - int ret = 0; - - switch (idx) { - case AMDGPU_PP_SENSOR_GFX_SCLK: - ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100; - *size = 4; - break; - case AMDGPU_PP_SENSOR_GFX_MCLK: - ret = vega20_get_current_clk_freq(hwmgr, - PPCLK_UCLK, - (uint32_t *)value); - if (!ret) - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_LOAD: - case AMDGPU_PP_SENSOR_MEM_LOAD: - ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); - if (!ret) - *size = 4; - break; - case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: - *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr); - *size = 4; - break; - case AMDGPU_PP_SENSOR_EDGE_TEMP: - ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - *((uint32_t *)value) = metrics_table.TemperatureEdge * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - *size = 4; - break; - case AMDGPU_PP_SENSOR_MEM_TEMP: - ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); - if (ret) - return ret; - - *((uint32_t *)value) = metrics_table.TemperatureHBM * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - *size = 4; - break; - case AMDGPU_PP_SENSOR_UVD_POWER: - *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; - *size = 4; - break; - case AMDGPU_PP_SENSOR_VCE_POWER: - *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; - *size = 4; - break; - case AMDGPU_PP_SENSOR_GPU_POWER: - *size = 16; - ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value); - break; - case AMDGPU_PP_SENSOR_VDDGFX: - val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & - SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> - SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; - *((uint32_t *)value) = - (uint32_t)convert_to_vddc((uint8_t)val_vid); - break; - case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: - ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value); - if (!ret) - *size = 8; - break; - default: - ret = -EINVAL; - break; - } - return ret; -} - -static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr, - struct pp_display_clock_request *clock_req) -{ - int result = 0; - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - enum amd_pp_clock_type clk_type = clock_req->clock_type; - uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; - PPCLK_e clk_select = 0; - uint32_t clk_request = 0; - - if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { - switch (clk_type) { - case amd_pp_dcef_clock: - clk_select = PPCLK_DCEFCLK; - break; - case amd_pp_disp_clock: - clk_select = PPCLK_DISPCLK; - break; - case amd_pp_pixel_clock: - clk_select = PPCLK_PIXCLK; - break; - case amd_pp_phy_clock: - clk_select = PPCLK_PHYCLK; - break; - default: - pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); - result = -EINVAL; - break; - } - - if (!result) { - clk_request = (clk_select << 16) | clk_freq; - result = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinByFreq, - clk_request, - NULL); - } - } - - return result; -} - -static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, - PHM_PerformanceLevelDesignation designation, uint32_t index, - PHM_PerformanceLevel *level) -{ - return 0; -} - -static int vega20_notify_smc_display_config_after_ps_adjustment( - struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table = - &data->dpm_table.mem_table; - struct PP_Clocks min_clocks = {0}; - struct pp_display_clock_request clock_req; - int ret = 0; - - min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; - min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; - min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; - - if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { - clock_req.clock_type = amd_pp_dcef_clock; - clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; - if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) { - if (data->smu_features[GNLD_DS_DCEFCLK].supported) - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter( - hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, - min_clocks.dcefClockInSR / 100, - NULL)) == 0, - "Attempt to set divider for DCEFCLK Failed!", - return ret); - } else { - pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); - } - } - - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinByFreq, - (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, - NULL)), - "[SetHardMinFreq] Set hard min uclk failed!", - return ret); - } - - return 0; -} - -static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t soft_level; - int ret = 0; - - soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->dpm_table.gfx_table.dpm_levels[soft_level].value; - - soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); - - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->dpm_table.mem_table.dpm_levels[soft_level].value; - - soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); - - data->dpm_table.soc_table.dpm_state.soft_min_level = - data->dpm_table.soc_table.dpm_state.soft_max_level = - data->dpm_table.soc_table.dpm_levels[soft_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | - FEATURE_DPM_UCLK_MASK | - FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to highest!", - return ret); - - ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | - FEATURE_DPM_UCLK_MASK | - FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - - return 0; -} - -static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t soft_level; - int ret = 0; - - soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->dpm_table.gfx_table.dpm_levels[soft_level].value; - - soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); - - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->dpm_table.mem_table.dpm_levels[soft_level].value; - - soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); - - data->dpm_table.soc_table.dpm_state.soft_min_level = - data->dpm_table.soc_table.dpm_state.soft_max_level = - data->dpm_table.soc_table.dpm_levels[soft_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | - FEATURE_DPM_UCLK_MASK | - FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to highest!", - return ret); - - ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | - FEATURE_DPM_UCLK_MASK | - FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - - return 0; - -} - -static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t soft_min_level, soft_max_level; - int ret = 0; - - /* gfxclk soft min/max settings */ - soft_min_level = - vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); - soft_max_level = - vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; - - /* uclk soft min/max settings */ - soft_min_level = - vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); - soft_max_level = - vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); - - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->dpm_table.mem_table.dpm_levels[soft_min_level].value; - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->dpm_table.mem_table.dpm_levels[soft_max_level].value; - - /* socclk soft min/max settings */ - soft_min_level = - vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); - soft_max_level = - vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); - - data->dpm_table.soc_table.dpm_state.soft_min_level = - data->dpm_table.soc_table.dpm_levels[soft_min_level].value; - data->dpm_table.soc_table.dpm_state.soft_max_level = - data->dpm_table.soc_table.dpm_levels[soft_max_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | - FEATURE_DPM_UCLK_MASK | - FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload DPM Bootup Levels!", - return ret); - - ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | - FEATURE_DPM_UCLK_MASK | - FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload DPM Max Levels!", - return ret); - - return 0; -} - -static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, - uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); - struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); - struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); - - *sclk_mask = 0; - *mclk_mask = 0; - *soc_mask = 0; - - if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && - mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL && - soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) { - *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; - *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; - *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL; - } - - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { - *sclk_mask = 0; - } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { - *mclk_mask = 0; - } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - *sclk_mask = gfx_dpm_table->count - 1; - *mclk_mask = mem_dpm_table->count - 1; - *soc_mask = soc_dpm_table->count - 1; - } - - return 0; -} - -static int vega20_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, uint32_t mask) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - uint32_t soft_min_level, soft_max_level, hard_min_level; - int ret = 0; - - switch (type) { - case PP_SCLK: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - - if (soft_max_level >= data->dpm_table.gfx_table.count) { - pr_err("Clock level specified %d is over max allowed %d\n", - soft_max_level, - data->dpm_table.gfx_table.count - 1); - return -EINVAL; - } - - data->dpm_table.gfx_table.dpm_state.soft_min_level = - data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; - data->dpm_table.gfx_table.dpm_state.soft_max_level = - data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - break; - - case PP_MCLK: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - - if (soft_max_level >= data->dpm_table.mem_table.count) { - pr_err("Clock level specified %d is over max allowed %d\n", - soft_max_level, - data->dpm_table.mem_table.count - 1); - return -EINVAL; - } - - data->dpm_table.mem_table.dpm_state.soft_min_level = - data->dpm_table.mem_table.dpm_levels[soft_min_level].value; - data->dpm_table.mem_table.dpm_state.soft_max_level = - data->dpm_table.mem_table.dpm_levels[soft_max_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - - break; - - case PP_SOCCLK: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - - if (soft_max_level >= data->dpm_table.soc_table.count) { - pr_err("Clock level specified %d is over max allowed %d\n", - soft_max_level, - data->dpm_table.soc_table.count - 1); - return -EINVAL; - } - - data->dpm_table.soc_table.dpm_state.soft_min_level = - data->dpm_table.soc_table.dpm_levels[soft_min_level].value; - data->dpm_table.soc_table.dpm_state.soft_max_level = - data->dpm_table.soc_table.dpm_levels[soft_max_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - - break; - - case PP_FCLK: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - - if (soft_max_level >= data->dpm_table.fclk_table.count) { - pr_err("Clock level specified %d is over max allowed %d\n", - soft_max_level, - data->dpm_table.fclk_table.count - 1); - return -EINVAL; - } - - data->dpm_table.fclk_table.dpm_state.soft_min_level = - data->dpm_table.fclk_table.dpm_levels[soft_min_level].value; - data->dpm_table.fclk_table.dpm_state.soft_max_level = - data->dpm_table.fclk_table.dpm_levels[soft_max_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload dpm max level to highest!", - return ret); - - break; - - case PP_DCEFCLK: - hard_min_level = mask ? (ffs(mask) - 1) : 0; - - if (hard_min_level >= data->dpm_table.dcef_table.count) { - pr_err("Clock level specified %d is over max allowed %d\n", - hard_min_level, - data->dpm_table.dcef_table.count - 1); - return -EINVAL; - } - - data->dpm_table.dcef_table.dpm_state.hard_min_level = - data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; - - ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK); - PP_ASSERT_WITH_CODE(!ret, - "Failed to upload boot level to lowest!", - return ret); - - //TODO: Setting DCEFCLK max dpm level is not supported - - break; - - case PP_PCIE: - soft_min_level = mask ? (ffs(mask) - 1) : 0; - soft_max_level = mask ? (fls(mask) - 1) : 0; - if (soft_min_level >= NUM_LINK_LEVELS || - soft_max_level >= NUM_LINK_LEVELS) - return -EINVAL; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level, - NULL); - PP_ASSERT_WITH_CODE(!ret, - "Failed to set min link dpm level!", - return ret); - - break; - - default: - break; - } - - return 0; -} - -static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, - enum amd_dpm_forced_level level) -{ - int ret = 0; - uint32_t sclk_mask, mclk_mask, soc_mask; - - switch (level) { - case AMD_DPM_FORCED_LEVEL_HIGH: - ret = vega20_force_dpm_highest(hwmgr); - break; - - case AMD_DPM_FORCED_LEVEL_LOW: - ret = vega20_force_dpm_lowest(hwmgr); - break; - - case AMD_DPM_FORCED_LEVEL_AUTO: - ret = vega20_unforce_dpm_levels(hwmgr); - break; - - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: - ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); - if (ret) - return ret; - vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); - vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); - vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask); - break; - - case AMD_DPM_FORCED_LEVEL_MANUAL: - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: - default: - break; - } - - return ret; -} - -static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) - return AMD_FAN_CTRL_MANUAL; - else - return AMD_FAN_CTRL_AUTO; -} - -static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - switch (mode) { - case AMD_FAN_CTRL_NONE: - vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100); - break; - case AMD_FAN_CTRL_MANUAL: - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega20_fan_ctrl_stop_smc_fan_control(hwmgr); - break; - case AMD_FAN_CTRL_AUTO: - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega20_fan_ctrl_start_smc_fan_control(hwmgr); - break; - default: - break; - } -} - -static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr, - struct amd_pp_simple_clock_info *info) -{ -#if 0 - struct phm_ppt_v2_information *table_info = - (struct phm_ppt_v2_information *)hwmgr->pptable; - struct phm_clock_and_voltage_limits *max_limits = - &table_info->max_clock_voltage_on_ac; - - info->engine_max_clock = max_limits->sclk; - info->memory_max_clock = max_limits->mclk; -#endif - return 0; -} - - -static int vega20_get_sclks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); - int i, count; - - if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) - return -1; - - count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; - clocks->num_levels = count; - - for (i = 0; i < count; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - clocks->data[i].latency_in_us = 0; - } - - return 0; -} - -static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr, - uint32_t clock) -{ - return 25; -} - -static int vega20_get_memclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); - int i, count; - - if (!data->smu_features[GNLD_DPM_UCLK].enabled) - return -1; - - count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; - clocks->num_levels = data->mclk_latency_table.count = count; - - for (i = 0; i < count; i++) { - clocks->data[i].clocks_in_khz = - data->mclk_latency_table.entries[i].frequency = - dpm_table->dpm_levels[i].value * 1000; - clocks->data[i].latency_in_us = - data->mclk_latency_table.entries[i].latency = - vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); - } - - return 0; -} - -static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); - int i, count; - - if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) - return -1; - - count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; - clocks->num_levels = count; - - for (i = 0; i < count; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - clocks->data[i].latency_in_us = 0; - } - - return 0; -} - -static int vega20_get_socclocks(struct pp_hwmgr *hwmgr, - struct pp_clock_levels_with_latency *clocks) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); - int i, count; - - if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) - return -1; - - count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; - clocks->num_levels = count; - - for (i = 0; i < count; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - clocks->data[i].latency_in_us = 0; - } - - return 0; - -} - -static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks) -{ - int ret; - - switch (type) { - case amd_pp_sys_clock: - ret = vega20_get_sclks(hwmgr, clocks); - break; - case amd_pp_mem_clock: - ret = vega20_get_memclocks(hwmgr, clocks); - break; - case amd_pp_dcef_clock: - ret = vega20_get_dcefclocks(hwmgr, clocks); - break; - case amd_pp_soc_clock: - ret = vega20_get_socclocks(hwmgr, clocks); - break; - default: - return -EINVAL; - } - - return ret; -} - -static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks) -{ - clocks->num_levels = 0; - - return 0; -} - -static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, - void *clock_ranges) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - Watermarks_t *table = &(data->smc_state_table.water_marks_table); - struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; - - if (!data->registry_data.disable_water_mark && - data->smu_features[GNLD_DPM_DCEFCLK].supported && - data->smu_features[GNLD_DPM_SOCCLK].supported) { - smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); - data->water_marks_bitmap |= WaterMarksExist; - data->water_marks_bitmap &= ~WaterMarksLoaded; - } - - return 0; -} - -static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, - enum PP_OD_DPM_TABLE_COMMAND type, - long *input, uint32_t size) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_od8_single_setting *od8_settings = - data->od8_settings.od8_settings_array; - OverDriveTable_t *od_table = - &(data->smc_state_table.overdrive_table); - int32_t input_index, input_clk, input_vol, i; - int od8_id; - int ret; - - PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", - return -EINVAL); - - switch (type) { - case PP_OD_EDIT_SCLK_VDDC_TABLE: - if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) { - pr_info("Sclk min/max frequency overdrive not supported\n"); - return -EOPNOTSUPP; - } - - for (i = 0; i < size; i += 2) { - if (i + 2 > size) { - pr_info("invalid number of input parameters %d\n", - size); - return -EINVAL; - } - - input_index = input[i]; - input_clk = input[i + 1]; - - if (input_index != 0 && input_index != 1) { - pr_info("Invalid index %d\n", input_index); - pr_info("Support min/max sclk frequency setting only which index by 0/1\n"); - return -EINVAL; - } - - if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value || - input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) { - pr_info("clock freq %d is not within allowed range [%d - %d]\n", - input_clk, - od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value, - od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value); - return -EINVAL; - } - - if ((input_index == 0 && od_table->GfxclkFmin != input_clk) || - (input_index == 1 && od_table->GfxclkFmax != input_clk)) - data->gfxclk_overdrive = true; - - if (input_index == 0) - od_table->GfxclkFmin = input_clk; - else - od_table->GfxclkFmax = input_clk; - } - - break; - - case PP_OD_EDIT_MCLK_VDDC_TABLE: - if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { - pr_info("Mclk max frequency overdrive not supported\n"); - return -EOPNOTSUPP; - } - - for (i = 0; i < size; i += 2) { - if (i + 2 > size) { - pr_info("invalid number of input parameters %d\n", - size); - return -EINVAL; - } - - input_index = input[i]; - input_clk = input[i + 1]; - - if (input_index != 1) { - pr_info("Invalid index %d\n", input_index); - pr_info("Support max Mclk frequency setting only which index by 1\n"); - return -EINVAL; - } - - if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value || - input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) { - pr_info("clock freq %d is not within allowed range [%d - %d]\n", - input_clk, - od8_settings[OD8_SETTING_UCLK_FMAX].min_value, - od8_settings[OD8_SETTING_UCLK_FMAX].max_value); - return -EINVAL; - } - - if (input_index == 1 && od_table->UclkFmax != input_clk) - data->memclk_overdrive = true; - - od_table->UclkFmax = input_clk; - } - - break; - - case PP_OD_EDIT_VDDC_CURVE: - if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) { - pr_info("Voltage curve calibrate not supported\n"); - return -EOPNOTSUPP; - } - - for (i = 0; i < size; i += 3) { - if (i + 3 > size) { - pr_info("invalid number of input parameters %d\n", - size); - return -EINVAL; - } - - input_index = input[i]; - input_clk = input[i + 1]; - input_vol = input[i + 2]; - - if (input_index > 2) { - pr_info("Setting for point %d is not supported\n", - input_index + 1); - pr_info("Three supported points index by 0, 1, 2\n"); - return -EINVAL; - } - - od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index; - if (input_clk < od8_settings[od8_id].min_value || - input_clk > od8_settings[od8_id].max_value) { - pr_info("clock freq %d is not within allowed range [%d - %d]\n", - input_clk, - od8_settings[od8_id].min_value, - od8_settings[od8_id].max_value); - return -EINVAL; - } - - od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index; - if (input_vol < od8_settings[od8_id].min_value || - input_vol > od8_settings[od8_id].max_value) { - pr_info("clock voltage %d is not within allowed range [%d - %d]\n", - input_vol, - od8_settings[od8_id].min_value, - od8_settings[od8_id].max_value); - return -EINVAL; - } - - switch (input_index) { - case 0: - od_table->GfxclkFreq1 = input_clk; - od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE; - break; - case 1: - od_table->GfxclkFreq2 = input_clk; - od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE; - break; - case 2: - od_table->GfxclkFreq3 = input_clk; - od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE; - break; - } - } - break; - - case PP_OD_RESTORE_DEFAULT_TABLE: - data->gfxclk_overdrive = false; - data->memclk_overdrive = false; - - ret = smum_smc_table_manager(hwmgr, - (uint8_t *)od_table, - TABLE_OVERDRIVE, true); - PP_ASSERT_WITH_CODE(!ret, - "Failed to export overdrive table!", - return ret); - break; - - case PP_OD_COMMIT_DPM_TABLE: - ret = smum_smc_table_manager(hwmgr, - (uint8_t *)od_table, - TABLE_OVERDRIVE, false); - PP_ASSERT_WITH_CODE(!ret, - "Failed to import overdrive table!", - return ret); - - /* retrieve updated gfxclk table */ - if (data->gfxclk_overdrive) { - data->gfxclk_overdrive = false; - - ret = vega20_setup_gfxclk_dpm_table(hwmgr); - if (ret) - return ret; - } - - /* retrieve updated memclk table */ - if (data->memclk_overdrive) { - data->memclk_overdrive = false; - - ret = vega20_setup_memclk_dpm_table(hwmgr); - if (ret) - return ret; - } - break; - - default: - return -EINVAL; - } - - return 0; -} - -static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr, - enum pp_mp1_state mp1_state) -{ - uint16_t msg; - int ret; - - switch (mp1_state) { - case PP_MP1_STATE_SHUTDOWN: - msg = PPSMC_MSG_PrepareMp1ForShutdown; - break; - case PP_MP1_STATE_UNLOAD: - msg = PPSMC_MSG_PrepareMp1ForUnload; - break; - case PP_MP1_STATE_RESET: - msg = PPSMC_MSG_PrepareMp1ForReset; - break; - case PP_MP1_STATE_NONE: - default: - return 0; - } - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, - "[PrepareMp1] Failed!", - return ret); - - return 0; -} - -static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) -{ - static const char *ppfeature_name[] = { - "DPM_PREFETCHER", - "GFXCLK_DPM", - "UCLK_DPM", - "SOCCLK_DPM", - "UVD_DPM", - "VCE_DPM", - "ULV", - "MP0CLK_DPM", - "LINK_DPM", - "DCEFCLK_DPM", - "GFXCLK_DS", - "SOCCLK_DS", - "LCLK_DS", - "PPT", - "TDC", - "THERMAL", - "GFX_PER_CU_CG", - "RM", - "DCEFCLK_DS", - "ACDC", - "VR0HOT", - "VR1HOT", - "FW_CTF", - "LED_DISPLAY", - "FAN_CONTROL", - "GFX_EDC", - "GFXOFF", - "CG", - "FCLK_DPM", - "FCLK_DS", - "MP1CLK_DS", - "MP0CLK_DS", - "XGMI", - "ECC"}; - static const char *output_title[] = { - "FEATURES", - "BITMASK", - "ENABLEMENT"}; - uint64_t features_enabled; - int i; - int ret = 0; - int size = 0; - - ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); - PP_ASSERT_WITH_CODE(!ret, - "[EnableAllSmuFeatures] Failed to get enabled smc features!", - return ret); - - size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); - size += sprintf(buf + size, "%-19s %-22s %s\n", - output_title[0], - output_title[1], - output_title[2]); - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", - ppfeature_name[i], - 1ULL << i, - (features_enabled & (1ULL << i)) ? "Y" : "N"); - } - - return size; -} - -static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - uint64_t features_enabled, features_to_enable, features_to_disable; - int i, ret = 0; - bool enabled; - - if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) - return -EINVAL; - - ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); - if (ret) - return ret; - - features_to_disable = - features_enabled & ~new_ppfeature_masks; - features_to_enable = - ~features_enabled & new_ppfeature_masks; - - pr_debug("features_to_disable 0x%llx\n", features_to_disable); - pr_debug("features_to_enable 0x%llx\n", features_to_enable); - - if (features_to_disable) { - ret = vega20_enable_smc_features(hwmgr, false, features_to_disable); - if (ret) - return ret; - } - - if (features_to_enable) { - ret = vega20_enable_smc_features(hwmgr, true, features_to_enable); - if (ret) - return ret; - } - - /* Update the cached feature enablement state */ - ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); - if (ret) - return ret; - - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? - true : false; - data->smu_features[i].enabled = enabled; - } - - return 0; -} - -static int vega20_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & - PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) - >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; -} - -static int vega20_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) -{ - uint32_t width_level; - - width_level = vega20_get_current_pcie_link_width_level(hwmgr); - if (width_level > LINK_WIDTH_MAX) - width_level = 0; - - return link_width[width_level]; -} - -static int vega20_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & - PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) - >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; -} - -static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) -{ - uint32_t speed_level; - - speed_level = vega20_get_current_pcie_link_speed_level(hwmgr); - if (speed_level > LINK_SPEED_MAX) - speed_level = 0; - - return link_speed[speed_level]; -} - -static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_od8_single_setting *od8_settings = - data->od8_settings.od8_settings_array; - OverDriveTable_t *od_table = - &(data->smc_state_table.overdrive_table); - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable; - struct pp_clock_levels_with_latency clocks; - struct vega20_single_dpm_table *fclk_dpm_table = - &(data->dpm_table.fclk_table); - int i, now, size = 0; - int ret = 0; - uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; - - switch (type) { - case PP_SCLK: - ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now); - PP_ASSERT_WITH_CODE(!ret, - "Attempt to get current gfx clk Failed!", - return ret); - - if (vega20_get_sclks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); - break; - } - - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); - break; - - case PP_MCLK: - ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now); - PP_ASSERT_WITH_CODE(!ret, - "Attempt to get current mclk freq Failed!", - return ret); - - if (vega20_get_memclocks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); - break; - } - - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); - break; - - case PP_SOCCLK: - ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now); - PP_ASSERT_WITH_CODE(!ret, - "Attempt to get current socclk freq Failed!", - return ret); - - if (vega20_get_socclocks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); - break; - } - - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); - break; - - case PP_FCLK: - ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now); - PP_ASSERT_WITH_CODE(!ret, - "Attempt to get current fclk freq Failed!", - return ret); - - for (i = 0; i < fclk_dpm_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, fclk_dpm_table->dpm_levels[i].value, - fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : ""); - break; - - case PP_DCEFCLK: - ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now); - PP_ASSERT_WITH_CODE(!ret, - "Attempt to get current dcefclk freq Failed!", - return ret); - - if (vega20_get_dcefclocks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); - break; - } - - for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); - break; - - case PP_PCIE: - current_gen_speed = - vega20_get_current_pcie_link_speed_level(hwmgr); - current_lane_width = - vega20_get_current_pcie_link_width_level(hwmgr); - for (i = 0; i < NUM_LINK_LEVELS; i++) { - if (i == 1 && data->pcie_parameters_override) { - gen_speed = data->pcie_gen_level1; - lane_width = data->pcie_width_level1; - } else { - gen_speed = pptable->PcieGenSpeed[i]; - lane_width = pptable->PcieLaneCount[i]; - } - size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, - (gen_speed == 0) ? "2.5GT/s," : - (gen_speed == 1) ? "5.0GT/s," : - (gen_speed == 2) ? "8.0GT/s," : - (gen_speed == 3) ? "16.0GT/s," : "", - (lane_width == 1) ? "x1" : - (lane_width == 2) ? "x2" : - (lane_width == 3) ? "x4" : - (lane_width == 4) ? "x8" : - (lane_width == 5) ? "x12" : - (lane_width == 6) ? "x16" : "", - pptable->LclkFreq[i], - (current_gen_speed == gen_speed) && - (current_lane_width == lane_width) ? - "*" : ""); - } - break; - - case OD_SCLK: - if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { - size = sprintf(buf, "%s:\n", "OD_SCLK"); - size += sprintf(buf + size, "0: %10uMhz\n", - od_table->GfxclkFmin); - size += sprintf(buf + size, "1: %10uMhz\n", - od_table->GfxclkFmax); - } - break; - - case OD_MCLK: - if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { - size = sprintf(buf, "%s:\n", "OD_MCLK"); - size += sprintf(buf + size, "1: %10uMhz\n", - od_table->UclkFmax); - } - - break; - - case OD_VDDC_CURVE: - if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { - size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE"); - size += sprintf(buf + size, "0: %10uMhz %10dmV\n", - od_table->GfxclkFreq1, - od_table->GfxclkVolt1 / VOLTAGE_SCALE); - size += sprintf(buf + size, "1: %10uMhz %10dmV\n", - od_table->GfxclkFreq2, - od_table->GfxclkVolt2 / VOLTAGE_SCALE); - size += sprintf(buf + size, "2: %10uMhz %10dmV\n", - od_table->GfxclkFreq3, - od_table->GfxclkVolt3 / VOLTAGE_SCALE); - } - - break; - - case OD_RANGE: - size = sprintf(buf, "%s:\n", "OD_RANGE"); - - if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { - size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", - od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value, - od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value); - } - - if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { - size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", - od8_settings[OD8_SETTING_UCLK_FMAX].min_value, - od8_settings[OD8_SETTING_UCLK_FMAX].max_value); - } - - if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && - od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { - size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", - od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value, - od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value); - size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value, - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value); - size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", - od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value, - od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value); - size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value, - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value); - size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", - od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value, - od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value); - size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value, - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value); - } - - break; - default: - break; - } - return size; -} - -static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, - struct vega20_single_dpm_table *dpm_table) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (data->smu_features[GNLD_DPM_UCLK].enabled) { - PP_ASSERT_WITH_CODE(dpm_table->count > 0, - "[SetUclkToHightestDpmLevel] Dpm table has no entry!", - return -EINVAL); - PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, - "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", - return -EINVAL); - - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinByFreq, - (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, - NULL)), - "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", - return ret); - } - - return ret; -} - -static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table); - int ret = 0; - - if (data->smu_features[GNLD_DPM_FCLK].enabled) { - PP_ASSERT_WITH_CODE(dpm_table->count > 0, - "[SetFclkToHightestDpmLevel] Dpm table has no entry!", - return -EINVAL); - PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS, - "[SetFclkToHightestDpmLevel] Dpm table has too many entries!", - return -EINVAL); - - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMinByFreq, - (PPCLK_FCLK << 16 ) | dpm_table->dpm_state.soft_min_level, - NULL)), - "[SetFclkToHightestDpmLevel] Set soft min fclk failed!", - return ret); - } - - return ret; -} - -static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - int ret = 0; - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, 0, NULL); - - ret = vega20_set_uclk_to_highest_dpm_level(hwmgr, - &data->dpm_table.mem_table); - if (ret) - return ret; - - return vega20_set_fclk_to_highest_dpm_level(hwmgr); -} - -static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - int result = 0; - Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); - - if ((data->water_marks_bitmap & WaterMarksExist) && - !(data->water_marks_bitmap & WaterMarksLoaded)) { - result = smum_smc_table_manager(hwmgr, - (uint8_t *)wm_table, TABLE_WATERMARKS, false); - PP_ASSERT_WITH_CODE(!result, - "Failed to update WMTABLE!", - return result); - data->water_marks_bitmap |= WaterMarksLoaded; - } - - if ((data->water_marks_bitmap & WaterMarksExist) && - data->smu_features[GNLD_DPM_DCEFCLK].supported && - data->smu_features[GNLD_DPM_SOCCLK].supported) { - result = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_NumOfDisplays, - hwmgr->display_config->num_display, - NULL); - } - - return result; -} - -static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - int ret = 0; - - if (data->smu_features[GNLD_DPM_UVD].supported) { - if (data->smu_features[GNLD_DPM_UVD].enabled == enable) { - if (enable) - PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n"); - else - PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n"); - } - - ret = vega20_enable_smc_features(hwmgr, - enable, - data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap); - PP_ASSERT_WITH_CODE(!ret, - "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!", - return ret); - data->smu_features[GNLD_DPM_UVD].enabled = enable; - } - - return 0; -} - -static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - - if (data->vce_power_gated == bgate) - return ; - - data->vce_power_gated = bgate; - if (bgate) { - vega20_enable_disable_vce_dpm(hwmgr, !bgate); - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_GATE); - } else { - amdgpu_device_ip_set_powergating_state(hwmgr->adev, - AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_UNGATE); - vega20_enable_disable_vce_dpm(hwmgr, !bgate); - } - -} - -static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - - if (data->uvd_power_gated == bgate) - return ; - - data->uvd_power_gated = bgate; - vega20_enable_disable_uvd_dpm(hwmgr, !bgate); -} - -static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - struct vega20_single_dpm_table *dpm_table; - bool vblank_too_short = false; - bool disable_mclk_switching; - bool disable_fclk_switching; - uint32_t i, latency; - - disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && - !hwmgr->display_config->multi_monitor_in_sync) || - vblank_too_short; - latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; - - /* gfxclk */ - dpm_table = &(data->dpm_table.gfx_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* memclk */ - dpm_table = &(data->dpm_table.mem_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* honour DAL's UCLK Hardmin */ - if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) - dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; - - /* Hardmin is dependent on displayconfig */ - if (disable_mclk_switching) { - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - for (i = 0; i < data->mclk_latency_table.count - 1; i++) { - if (data->mclk_latency_table.entries[i].latency <= latency) { - if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; - break; - } - } - } - } - - if (hwmgr->display_config->nb_pstate_switch_disable) - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - if ((disable_mclk_switching && - (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) || - hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value) - disable_fclk_switching = true; - else - disable_fclk_switching = false; - - /* fclk */ - dpm_table = &(data->dpm_table.fclk_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; - if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching) - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - - /* vclk */ - dpm_table = &(data->dpm_table.vclk_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* dclk */ - dpm_table = &(data->dpm_table.dclk_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* socclk */ - dpm_table = &(data->dpm_table.soc_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - /* eclk */ - dpm_table = &(data->dpm_table.eclk_table); - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; - dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; - dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; - - if (PP_CAP(PHM_PlatformCaps_UMDPState)) { - if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value; - } - - if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { - dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; - } - } - - return 0; -} - -static bool -vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - bool is_update_required = false; - - if (data->display_timing.num_existing_displays != - hwmgr->display_config->num_display) - is_update_required = true; - - if (data->registry_data.gfx_clk_deep_sleep_support && - (data->display_timing.min_clock_in_sr != - hwmgr->display_config->min_core_set_clock_in_sr)) - is_update_required = true; - - return is_update_required; -} - -static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int ret = 0; - - ret = vega20_disable_all_smu_features(hwmgr); - PP_ASSERT_WITH_CODE(!ret, - "[DisableDpmTasks] Failed to disable all smu features!", - return ret); - - return 0; -} - -static int vega20_power_off_asic(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - int result; - - result = vega20_disable_dpm_tasks(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "[PowerOffAsic] Failed to disable DPM!", - ); - data->water_marks_bitmap &= ~(WaterMarksLoaded); - - return result; -} - -static int conv_power_profile_to_pplib_workload(int power_profile) -{ - int pplib_workload = 0; - - switch (power_profile) { - case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT: - pplib_workload = WORKLOAD_DEFAULT_BIT; - break; - case PP_SMC_POWER_PROFILE_FULLSCREEN3D: - pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; - break; - case PP_SMC_POWER_PROFILE_POWERSAVING: - pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; - break; - case PP_SMC_POWER_PROFILE_VIDEO: - pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; - break; - case PP_SMC_POWER_PROFILE_VR: - pplib_workload = WORKLOAD_PPLIB_VR_BIT; - break; - case PP_SMC_POWER_PROFILE_COMPUTE: - pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; - break; - case PP_SMC_POWER_PROFILE_CUSTOM: - pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; - break; - } - - return pplib_workload; -} - -static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) -{ - DpmActivityMonitorCoeffInt_t activity_monitor; - uint32_t i, size = 0; - uint16_t workload_type = 0; - static const char *profile_name[] = { - "BOOTUP_DEFAULT", - "3D_FULL_SCREEN", - "POWER_SAVING", - "VIDEO", - "VR", - "COMPUTE", - "CUSTOM"}; - static const char *title[] = { - "PROFILE_INDEX(NAME)", - "CLOCK_TYPE(NAME)", - "FPS", - "UseRlcBusy", - "MinActiveFreqType", - "MinActiveFreq", - "BoosterFreqType", - "BoosterFreq", - "PD_Data_limit_c", - "PD_Data_error_coeff", - "PD_Data_error_rate_coeff"}; - int result = 0; - - if (!buf) - return -EINVAL; - - size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", - title[0], title[1], title[2], title[3], title[4], title[5], - title[6], title[7], title[8], title[9], title[10]); - - for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { - /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ - workload_type = conv_power_profile_to_pplib_workload(i); - result = vega20_get_activity_monitor_coeff(hwmgr, - (uint8_t *)(&activity_monitor), workload_type); - PP_ASSERT_WITH_CODE(!result, - "[GetPowerProfile] Failed to get activity monitor!", - return result); - - size += sprintf(buf + size, "%2d %14s%s:\n", - i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " "); - - size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", - " ", - 0, - "GFXCLK", - activity_monitor.Gfx_FPS, - activity_monitor.Gfx_UseRlcBusy, - activity_monitor.Gfx_MinActiveFreqType, - activity_monitor.Gfx_MinActiveFreq, - activity_monitor.Gfx_BoosterFreqType, - activity_monitor.Gfx_BoosterFreq, - activity_monitor.Gfx_PD_Data_limit_c, - activity_monitor.Gfx_PD_Data_error_coeff, - activity_monitor.Gfx_PD_Data_error_rate_coeff); - - size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", - " ", - 1, - "SOCCLK", - activity_monitor.Soc_FPS, - activity_monitor.Soc_UseRlcBusy, - activity_monitor.Soc_MinActiveFreqType, - activity_monitor.Soc_MinActiveFreq, - activity_monitor.Soc_BoosterFreqType, - activity_monitor.Soc_BoosterFreq, - activity_monitor.Soc_PD_Data_limit_c, - activity_monitor.Soc_PD_Data_error_coeff, - activity_monitor.Soc_PD_Data_error_rate_coeff); - - size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", - " ", - 2, - "UCLK", - activity_monitor.Mem_FPS, - activity_monitor.Mem_UseRlcBusy, - activity_monitor.Mem_MinActiveFreqType, - activity_monitor.Mem_MinActiveFreq, - activity_monitor.Mem_BoosterFreqType, - activity_monitor.Mem_BoosterFreq, - activity_monitor.Mem_PD_Data_limit_c, - activity_monitor.Mem_PD_Data_error_coeff, - activity_monitor.Mem_PD_Data_error_rate_coeff); - - size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", - " ", - 3, - "FCLK", - activity_monitor.Fclk_FPS, - activity_monitor.Fclk_UseRlcBusy, - activity_monitor.Fclk_MinActiveFreqType, - activity_monitor.Fclk_MinActiveFreq, - activity_monitor.Fclk_BoosterFreqType, - activity_monitor.Fclk_BoosterFreq, - activity_monitor.Fclk_PD_Data_limit_c, - activity_monitor.Fclk_PD_Data_error_coeff, - activity_monitor.Fclk_PD_Data_error_rate_coeff); - } - - return size; -} - -static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) -{ - DpmActivityMonitorCoeffInt_t activity_monitor; - int workload_type, result = 0; - uint32_t power_profile_mode = input[size]; - - if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { - pr_err("Invalid power profile mode %d\n", power_profile_mode); - return -EINVAL; - } - - if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - if (size == 0 && !data->is_custom_profile_set) - return -EINVAL; - if (size < 10 && size != 0) - return -EINVAL; - - result = vega20_get_activity_monitor_coeff(hwmgr, - (uint8_t *)(&activity_monitor), - WORKLOAD_PPLIB_CUSTOM_BIT); - PP_ASSERT_WITH_CODE(!result, - "[SetPowerProfile] Failed to get activity monitor!", - return result); - - /* If size==0, then we want to apply the already-configured - * CUSTOM profile again. Just apply it, since we checked its - * validity above - */ - if (size == 0) - goto out; - - switch (input[0]) { - case 0: /* Gfxclk */ - activity_monitor.Gfx_FPS = input[1]; - activity_monitor.Gfx_UseRlcBusy = input[2]; - activity_monitor.Gfx_MinActiveFreqType = input[3]; - activity_monitor.Gfx_MinActiveFreq = input[4]; - activity_monitor.Gfx_BoosterFreqType = input[5]; - activity_monitor.Gfx_BoosterFreq = input[6]; - activity_monitor.Gfx_PD_Data_limit_c = input[7]; - activity_monitor.Gfx_PD_Data_error_coeff = input[8]; - activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; - break; - case 1: /* Socclk */ - activity_monitor.Soc_FPS = input[1]; - activity_monitor.Soc_UseRlcBusy = input[2]; - activity_monitor.Soc_MinActiveFreqType = input[3]; - activity_monitor.Soc_MinActiveFreq = input[4]; - activity_monitor.Soc_BoosterFreqType = input[5]; - activity_monitor.Soc_BoosterFreq = input[6]; - activity_monitor.Soc_PD_Data_limit_c = input[7]; - activity_monitor.Soc_PD_Data_error_coeff = input[8]; - activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; - break; - case 2: /* Uclk */ - activity_monitor.Mem_FPS = input[1]; - activity_monitor.Mem_UseRlcBusy = input[2]; - activity_monitor.Mem_MinActiveFreqType = input[3]; - activity_monitor.Mem_MinActiveFreq = input[4]; - activity_monitor.Mem_BoosterFreqType = input[5]; - activity_monitor.Mem_BoosterFreq = input[6]; - activity_monitor.Mem_PD_Data_limit_c = input[7]; - activity_monitor.Mem_PD_Data_error_coeff = input[8]; - activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; - break; - case 3: /* Fclk */ - activity_monitor.Fclk_FPS = input[1]; - activity_monitor.Fclk_UseRlcBusy = input[2]; - activity_monitor.Fclk_MinActiveFreqType = input[3]; - activity_monitor.Fclk_MinActiveFreq = input[4]; - activity_monitor.Fclk_BoosterFreqType = input[5]; - activity_monitor.Fclk_BoosterFreq = input[6]; - activity_monitor.Fclk_PD_Data_limit_c = input[7]; - activity_monitor.Fclk_PD_Data_error_coeff = input[8]; - activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9]; - break; - } - - result = vega20_set_activity_monitor_coeff(hwmgr, - (uint8_t *)(&activity_monitor), - WORKLOAD_PPLIB_CUSTOM_BIT); - data->is_custom_profile_set = true; - PP_ASSERT_WITH_CODE(!result, - "[SetPowerProfile] Failed to set activity monitor!", - return result); - } - -out: - /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ - workload_type = - conv_power_profile_to_pplib_workload(power_profile_mode); - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, - 1 << workload_type, - NULL); - - hwmgr->power_profile_mode = power_profile_mode; - - return 0; -} - -static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, - uint32_t virtual_addr_low, - uint32_t virtual_addr_hi, - uint32_t mc_addr_low, - uint32_t mc_addr_hi, - uint32_t size) -{ - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSystemVirtualDramAddrHigh, - virtual_addr_hi, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSystemVirtualDramAddrLow, - virtual_addr_low, - NULL); - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramAddrHigh, - mc_addr_hi, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramAddrLow, - mc_addr_low, - NULL); - - smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_DramLogSetDramSize, - size, - NULL); - return 0; -} - -static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *thermal_data) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - - memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); - - thermal_data->max = pp_table->TedgeLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->mem_crit_max = pp_table->ThbmLimit * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return 0; -} - -static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire) -{ - int res; - - /* I2C bus access can happen very early, when SMU not loaded yet */ - if (!vega20_is_smc_ram_running(hwmgr)) - return 0; - - res = smum_send_msg_to_smc_with_parameter(hwmgr, - (acquire ? - PPSMC_MSG_RequestI2CBus : - PPSMC_MSG_ReleaseI2CBus), - 0, - NULL); - - PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res); - return res; -} - -static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr, - enum pp_df_cstate state) -{ - int ret; - - /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */ - if (hwmgr->smu_version < 0x283200) { - pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n"); - return -EINVAL; - } - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state, - NULL); - if (ret) - pr_err("SetDfCstate failed!\n"); - - return ret; -} - -static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr, - uint32_t pstate) -{ - int ret; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetXgmiMode, - pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, - NULL); - if (ret) - pr_err("SetXgmiPstate failed!\n"); - - return ret; -} - -static void vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) -{ - memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); - - gpu_metrics->common_header.structure_size = - sizeof(struct gpu_metrics_v1_0); - gpu_metrics->common_header.format_revision = 1; - gpu_metrics->common_header.content_revision = 0; - - gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); -} - -static ssize_t vega20_get_gpu_metrics(struct pp_hwmgr *hwmgr, - void **table) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - struct gpu_metrics_v1_0 *gpu_metrics = - &data->gpu_metrics_table; - SmuMetrics_t metrics; - uint32_t fan_speed_rpm; - int ret; - - ret = vega20_get_metrics_table(hwmgr, &metrics, true); - if (ret) - return ret; - - vega20_init_gpu_metrics_v1_0(gpu_metrics); - - gpu_metrics->temperature_edge = metrics.TemperatureEdge; - gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; - gpu_metrics->temperature_mem = metrics.TemperatureHBM; - gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; - gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; - gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; - - gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; - gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; - - gpu_metrics->average_socket_power = metrics.AverageSocketPower; - - gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; - gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; - gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; - - gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; - gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; - gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; - gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; - gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; - - gpu_metrics->throttle_status = metrics.ThrottlerStatus; - - vega20_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); - gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; - - gpu_metrics->pcie_link_width = - vega20_get_current_pcie_link_width(hwmgr); - gpu_metrics->pcie_link_speed = - vega20_get_current_pcie_link_speed(hwmgr); - - *table = (void *)gpu_metrics; - - return sizeof(struct gpu_metrics_v1_0); -} - -static const struct pp_hwmgr_func vega20_hwmgr_funcs = { - /* init/fini related */ - .backend_init = vega20_hwmgr_backend_init, - .backend_fini = vega20_hwmgr_backend_fini, - .asic_setup = vega20_setup_asic_task, - .power_off_asic = vega20_power_off_asic, - .dynamic_state_management_enable = vega20_enable_dpm_tasks, - .dynamic_state_management_disable = vega20_disable_dpm_tasks, - /* power state related */ - .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules, - .pre_display_config_changed = vega20_pre_display_configuration_changed_task, - .display_config_changed = vega20_display_configuration_changed_task, - .check_smc_update_required_for_display_configuration = - vega20_check_smc_update_required_for_display_configuration, - .notify_smc_display_config_after_ps_adjustment = - vega20_notify_smc_display_config_after_ps_adjustment, - /* export to DAL */ - .get_sclk = vega20_dpm_get_sclk, - .get_mclk = vega20_dpm_get_mclk, - .get_dal_power_level = vega20_get_dal_power_level, - .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency, - .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage, - .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges, - .display_clock_voltage_request = vega20_display_clock_voltage_request, - .get_performance_level = vega20_get_performance_level, - /* UMD pstate, profile related */ - .force_dpm_level = vega20_dpm_force_dpm_level, - .get_power_profile_mode = vega20_get_power_profile_mode, - .set_power_profile_mode = vega20_set_power_profile_mode, - /* od related */ - .set_power_limit = vega20_set_power_limit, - .get_sclk_od = vega20_get_sclk_od, - .set_sclk_od = vega20_set_sclk_od, - .get_mclk_od = vega20_get_mclk_od, - .set_mclk_od = vega20_set_mclk_od, - .odn_edit_dpm_table = vega20_odn_edit_dpm_table, - /* for sysfs to retrive/set gfxclk/memclk */ - .force_clock_level = vega20_force_clock_level, - .print_clock_levels = vega20_print_clock_levels, - .read_sensor = vega20_read_sensor, - .get_ppfeature_status = vega20_get_ppfeature_status, - .set_ppfeature_status = vega20_set_ppfeature_status, - /* powergate related */ - .powergate_uvd = vega20_power_gate_uvd, - .powergate_vce = vega20_power_gate_vce, - /* thermal related */ - .start_thermal_controller = vega20_start_thermal_controller, - .stop_thermal_controller = vega20_thermal_stop_thermal_controller, - .get_thermal_temperature_range = vega20_get_thermal_temperature_range, - .register_irq_handlers = smu9_register_irq_handlers, - .disable_smc_firmware_ctf = vega20_thermal_disable_alert, - /* fan control related */ - .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent, - .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent, - .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info, - .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm, - .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm, - .get_fan_control_mode = vega20_get_fan_control_mode, - .set_fan_control_mode = vega20_set_fan_control_mode, - /* smu memory related */ - .notify_cac_buffer_info = vega20_notify_cac_buffer_info, - .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost, - /* BACO related */ - .get_asic_baco_capability = vega20_baco_get_capability, - .get_asic_baco_state = vega20_baco_get_state, - .set_asic_baco_state = vega20_baco_set_state, - .set_mp1_state = vega20_set_mp1_state, - .smu_i2c_bus_access = vega20_smu_i2c_bus_access, - .set_df_cstate = vega20_set_df_cstate, - .set_xgmi_pstate = vega20_set_xgmi_pstate, - .get_gpu_metrics = vega20_get_gpu_metrics, -}; - -int vega20_hwmgr_init(struct pp_hwmgr *hwmgr) -{ - hwmgr->hwmgr_func = &vega20_hwmgr_funcs; - hwmgr->pptable_func = &vega20_pptable_funcs; - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h deleted file mode 100644 index 075c0094da9c..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h +++ /dev/null @@ -1,590 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _VEGA20_HWMGR_H_ -#define _VEGA20_HWMGR_H_ - -#include "hwmgr.h" -#include "smu11_driver_if.h" -#include "ppatomfwctrl.h" - -#define VEGA20_MAX_HARDWARE_POWERLEVELS 2 - -#define WaterMarksExist 1 -#define WaterMarksLoaded 2 - -#define VG20_PSUEDO_NUM_GFXCLK_DPM_LEVELS 8 -#define VG20_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8 -#define VG20_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8 -#define VG20_PSUEDO_NUM_UCLK_DPM_LEVELS 4 - -//OverDriver8 macro defs -#define AVFS_CURVE 0 -#define OD8_HOTCURVE_TEMPERATURE 85 - -#define VG20_CLOCK_MAX_DEFAULT 0xFFFF - -typedef uint32_t PP_Clock; - -enum { - GNLD_DPM_PREFETCHER = 0, - GNLD_DPM_GFXCLK, - GNLD_DPM_UCLK, - GNLD_DPM_SOCCLK, - GNLD_DPM_UVD, - GNLD_DPM_VCE, - GNLD_ULV, - GNLD_DPM_MP0CLK, - GNLD_DPM_LINK, - GNLD_DPM_DCEFCLK, - GNLD_DS_GFXCLK, - GNLD_DS_SOCCLK, - GNLD_DS_LCLK, - GNLD_PPT, - GNLD_TDC, - GNLD_THERMAL, - GNLD_GFX_PER_CU_CG, - GNLD_RM, - GNLD_DS_DCEFCLK, - GNLD_ACDC, - GNLD_VR0HOT, - GNLD_VR1HOT, - GNLD_FW_CTF, - GNLD_LED_DISPLAY, - GNLD_FAN_CONTROL, - GNLD_DIDT, - GNLD_GFXOFF, - GNLD_CG, - GNLD_DPM_FCLK, - GNLD_DS_FCLK, - GNLD_DS_MP1CLK, - GNLD_DS_MP0CLK, - GNLD_XGMI, - GNLD_ECC, - - GNLD_FEATURES_MAX -}; - - -#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) - -#define SMC_DPM_FEATURES 0x30F - -struct smu_features { - bool supported; - bool enabled; - bool allowed; - uint32_t smu_feature_id; - uint64_t smu_feature_bitmap; -}; - -struct vega20_performance_level { - uint32_t soc_clock; - uint32_t gfx_clock; - uint32_t mem_clock; -}; - -struct vega20_bacos { - uint32_t baco_flags; - /* struct vega20_performance_level performance_level; */ -}; - -struct vega20_uvd_clocks { - uint32_t vclk; - uint32_t dclk; -}; - -struct vega20_vce_clocks { - uint32_t evclk; - uint32_t ecclk; -}; - -struct vega20_power_state { - uint32_t magic; - struct vega20_uvd_clocks uvd_clks; - struct vega20_vce_clocks vce_clks; - uint16_t performance_level_count; - bool dc_compatible; - uint32_t sclk_threshold; - struct vega20_performance_level performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS]; -}; - -struct vega20_dpm_level { - bool enabled; - uint32_t value; - uint32_t param1; -}; - -#define VEGA20_MAX_DEEPSLEEP_DIVIDER_ID 5 -#define MAX_REGULAR_DPM_NUMBER 16 -#define MAX_PCIE_CONF 2 -#define VEGA20_MINIMUM_ENGINE_CLOCK 2500 - -struct vega20_max_sustainable_clocks { - PP_Clock display_clock; - PP_Clock phy_clock; - PP_Clock pixel_clock; - PP_Clock uclock; - PP_Clock dcef_clock; - PP_Clock soc_clock; -}; - -struct vega20_dpm_state { - uint32_t soft_min_level; - uint32_t soft_max_level; - uint32_t hard_min_level; - uint32_t hard_max_level; -}; - -struct vega20_single_dpm_table { - uint32_t count; - struct vega20_dpm_state dpm_state; - struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega20_odn_dpm_control { - uint32_t count; - uint32_t entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega20_pcie_table { - uint16_t count; - uint8_t pcie_gen[MAX_PCIE_CONF]; - uint8_t pcie_lane[MAX_PCIE_CONF]; - uint32_t lclk[MAX_PCIE_CONF]; -}; - -struct vega20_dpm_table { - struct vega20_single_dpm_table soc_table; - struct vega20_single_dpm_table gfx_table; - struct vega20_single_dpm_table mem_table; - struct vega20_single_dpm_table eclk_table; - struct vega20_single_dpm_table vclk_table; - struct vega20_single_dpm_table dclk_table; - struct vega20_single_dpm_table dcef_table; - struct vega20_single_dpm_table pixel_table; - struct vega20_single_dpm_table display_table; - struct vega20_single_dpm_table phy_table; - struct vega20_single_dpm_table fclk_table; - struct vega20_pcie_table pcie_table; -}; - -#define VEGA20_MAX_LEAKAGE_COUNT 8 -struct vega20_leakage_voltage { - uint16_t count; - uint16_t leakage_id[VEGA20_MAX_LEAKAGE_COUNT]; - uint16_t actual_voltage[VEGA20_MAX_LEAKAGE_COUNT]; -}; - -struct vega20_display_timing { - uint32_t min_clock_in_sr; - uint32_t num_existing_displays; -}; - -struct vega20_dpmlevel_enable_mask { - uint32_t uvd_dpm_enable_mask; - uint32_t vce_dpm_enable_mask; - uint32_t samu_dpm_enable_mask; - uint32_t sclk_dpm_enable_mask; - uint32_t mclk_dpm_enable_mask; -}; - -struct vega20_vbios_boot_state { - uint8_t uc_cooling_id; - uint16_t vddc; - uint16_t vddci; - uint16_t mvddc; - uint16_t vdd_gfx; - uint32_t gfx_clock; - uint32_t mem_clock; - uint32_t soc_clock; - uint32_t dcef_clock; - uint32_t eclock; - uint32_t dclock; - uint32_t vclock; - uint32_t fclock; -}; - -#define DPMTABLE_OD_UPDATE_SCLK 0x00000001 -#define DPMTABLE_OD_UPDATE_MCLK 0x00000002 -#define DPMTABLE_UPDATE_SCLK 0x00000004 -#define DPMTABLE_UPDATE_MCLK 0x00000008 -#define DPMTABLE_OD_UPDATE_VDDC 0x00000010 -#define DPMTABLE_OD_UPDATE_SCLK_MASK 0x00000020 -#define DPMTABLE_OD_UPDATE_MCLK_MASK 0x00000040 - -// To determine if sclk and mclk are in overdrive state -#define SCLK_MASK_OVERDRIVE_ENABLED 0x00000008 -#define MCLK_MASK_OVERDRIVE_ENABLED 0x00000010 -#define SOCCLK_OVERDRIVE_ENABLED 0x00000020 - -struct vega20_smc_state_table { - uint32_t soc_boot_level; - uint32_t gfx_boot_level; - uint32_t dcef_boot_level; - uint32_t mem_boot_level; - uint32_t uvd_boot_level; - uint32_t vce_boot_level; - uint32_t gfx_max_level; - uint32_t mem_max_level; - uint8_t vr_hot_gpio; - uint8_t ac_dc_gpio; - uint8_t therm_out_gpio; - uint8_t therm_out_polarity; - uint8_t therm_out_mode; - PPTable_t pp_table; - Watermarks_t water_marks_table; - AvfsDebugTable_t avfs_debug_table; - AvfsFuseOverride_t avfs_fuse_override_table; - SmuMetrics_t smu_metrics; - DriverSmuConfig_t driver_smu_config; - DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint; - OverDriveTable_t overdrive_table; -}; - -struct vega20_mclk_latency_entries { - uint32_t frequency; - uint32_t latency; -}; - -struct vega20_mclk_latency_table { - uint32_t count; - struct vega20_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega20_registry_data { - uint64_t disallowed_features; - uint8_t ac_dc_switch_gpio_support; - uint8_t acg_loop_support; - uint8_t clock_stretcher_support; - uint8_t db_ramping_support; - uint8_t didt_mode; - uint8_t didt_support; - uint8_t edc_didt_support; - uint8_t force_dpm_high; - uint8_t fuzzy_fan_control_support; - uint8_t mclk_dpm_key_disabled; - uint8_t od_state_in_dc_support; - uint8_t pcie_lane_override; - uint8_t pcie_speed_override; - uint32_t pcie_clock_override; - uint8_t pcie_dpm_key_disabled; - uint8_t dcefclk_dpm_key_disabled; - uint8_t prefetcher_dpm_key_disabled; - uint8_t quick_transition_support; - uint8_t regulator_hot_gpio_support; - uint8_t master_deep_sleep_support; - uint8_t gfx_clk_deep_sleep_support; - uint8_t sclk_deep_sleep_support; - uint8_t lclk_deep_sleep_support; - uint8_t dce_fclk_deep_sleep_support; - uint8_t sclk_dpm_key_disabled; - uint8_t sclk_throttle_low_notification; - uint8_t skip_baco_hardware; - uint8_t socclk_dpm_key_disabled; - uint8_t sq_ramping_support; - uint8_t tcp_ramping_support; - uint8_t td_ramping_support; - uint8_t dbr_ramping_support; - uint8_t gc_didt_support; - uint8_t psm_didt_support; - uint8_t thermal_support; - uint8_t fw_ctf_enabled; - uint8_t led_dpm_enabled; - uint8_t fan_control_support; - uint8_t ulv_support; - uint8_t od8_feature_enable; - uint8_t disable_water_mark; - uint8_t disable_workload_policy; - uint32_t force_workload_policy_mask; - uint8_t disable_3d_fs_detection; - uint8_t disable_pp_tuning; - uint8_t disable_xlpp_tuning; - uint32_t perf_ui_tuning_profile_turbo; - uint32_t perf_ui_tuning_profile_powerSave; - uint32_t perf_ui_tuning_profile_xl; - uint16_t zrpm_stop_temp; - uint16_t zrpm_start_temp; - uint32_t stable_pstate_sclk_dpm_percentage; - uint8_t fps_support; - uint8_t vr0hot; - uint8_t vr1hot; - uint8_t disable_auto_wattman; - uint32_t auto_wattman_debug; - uint32_t auto_wattman_sample_period; - uint32_t fclk_gfxclk_ratio; - uint8_t auto_wattman_threshold; - uint8_t log_avfs_param; - uint8_t enable_enginess; - uint8_t custom_fan_support; - uint8_t disable_pcc_limit_control; - uint8_t gfxoff_controlled_by_driver; -}; - -struct vega20_odn_clock_voltage_dependency_table { - uint32_t count; - struct phm_ppt_v1_clock_voltage_dependency_record - entries[MAX_REGULAR_DPM_NUMBER]; -}; - -struct vega20_odn_dpm_table { - struct vega20_odn_dpm_control control_gfxclk_state; - struct vega20_odn_dpm_control control_memclk_state; - struct phm_odn_clock_levels odn_core_clock_dpm_levels; - struct phm_odn_clock_levels odn_memory_clock_dpm_levels; - struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; - struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; - struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_socclk; - uint32_t odn_mclk_min_limit; -}; - -struct vega20_odn_fan_table { - uint32_t target_fan_speed; - uint32_t target_temperature; - uint32_t min_performance_clock; - uint32_t min_fan_limit; - bool force_fan_pwm; -}; - -struct vega20_odn_temp_table { - uint16_t target_operating_temp; - uint16_t default_target_operating_temp; - uint16_t operating_temp_min_limit; - uint16_t operating_temp_max_limit; - uint16_t operating_temp_step; -}; - -struct vega20_odn_data { - uint32_t apply_overdrive_next_settings_mask; - uint32_t overdrive_next_state; - uint32_t overdrive_next_capabilities; - uint32_t odn_sclk_dpm_enable_mask; - uint32_t odn_mclk_dpm_enable_mask; - struct vega20_odn_dpm_table odn_dpm_table; - struct vega20_odn_fan_table odn_fan_table; - struct vega20_odn_temp_table odn_temp_table; -}; - -enum OD8_FEATURE_ID -{ - OD8_GFXCLK_LIMITS = 1 << 0, - OD8_GFXCLK_CURVE = 1 << 1, - OD8_UCLK_MAX = 1 << 2, - OD8_POWER_LIMIT = 1 << 3, - OD8_ACOUSTIC_LIMIT_SCLK = 1 << 4, //FanMaximumRpm - OD8_FAN_SPEED_MIN = 1 << 5, //FanMinimumPwm - OD8_TEMPERATURE_FAN = 1 << 6, //FanTargetTemperature - OD8_TEMPERATURE_SYSTEM = 1 << 7, //MaxOpTemp - OD8_MEMORY_TIMING_TUNE = 1 << 8, - OD8_FAN_ZERO_RPM_CONTROL = 1 << 9 -}; - -enum OD8_SETTING_ID -{ - OD8_SETTING_GFXCLK_FMIN = 0, - OD8_SETTING_GFXCLK_FMAX, - OD8_SETTING_GFXCLK_FREQ1, - OD8_SETTING_GFXCLK_VOLTAGE1, - OD8_SETTING_GFXCLK_FREQ2, - OD8_SETTING_GFXCLK_VOLTAGE2, - OD8_SETTING_GFXCLK_FREQ3, - OD8_SETTING_GFXCLK_VOLTAGE3, - OD8_SETTING_UCLK_FMAX, - OD8_SETTING_POWER_PERCENTAGE, - OD8_SETTING_FAN_ACOUSTIC_LIMIT, - OD8_SETTING_FAN_MIN_SPEED, - OD8_SETTING_FAN_TARGET_TEMP, - OD8_SETTING_OPERATING_TEMP_MAX, - OD8_SETTING_AC_TIMING, - OD8_SETTING_FAN_ZERO_RPM_CONTROL, - OD8_SETTING_COUNT -}; - -struct vega20_od8_single_setting { - uint32_t feature_id; - int32_t min_value; - int32_t max_value; - int32_t current_value; - int32_t default_value; -}; - -struct vega20_od8_settings { - uint32_t overdrive8_capabilities; - struct vega20_od8_single_setting od8_settings_array[OD8_SETTING_COUNT]; -}; - -struct vega20_hwmgr { - struct vega20_dpm_table dpm_table; - struct vega20_dpm_table golden_dpm_table; - struct vega20_registry_data registry_data; - struct vega20_vbios_boot_state vbios_boot_state; - struct vega20_mclk_latency_table mclk_latency_table; - - struct vega20_max_sustainable_clocks max_sustainable_clocks; - - struct vega20_leakage_voltage vddc_leakage; - - uint32_t vddc_control; - struct pp_atomfwctrl_voltage_table vddc_voltage_table; - uint32_t mvdd_control; - struct pp_atomfwctrl_voltage_table mvdd_voltage_table; - uint32_t vddci_control; - struct pp_atomfwctrl_voltage_table vddci_voltage_table; - - uint32_t active_auto_throttle_sources; - struct vega20_bacos bacos; - - /* ---- General data ---- */ - uint8_t need_update_dpm_table; - - bool cac_enabled; - bool battery_state; - bool is_tlu_enabled; - bool avfs_exist; - - uint32_t low_sclk_interrupt_threshold; - - uint32_t total_active_cus; - - uint32_t water_marks_bitmap; - - struct vega20_display_timing display_timing; - - /* ---- Vega20 Dyn Register Settings ---- */ - - uint32_t debug_settings; - uint32_t lowest_uclk_reserved_for_ulv; - uint32_t gfxclk_average_alpha; - uint32_t socclk_average_alpha; - uint32_t uclk_average_alpha; - uint32_t gfx_activity_average_alpha; - uint32_t display_voltage_mode; - uint32_t dcef_clk_quad_eqn_a; - uint32_t dcef_clk_quad_eqn_b; - uint32_t dcef_clk_quad_eqn_c; - uint32_t disp_clk_quad_eqn_a; - uint32_t disp_clk_quad_eqn_b; - uint32_t disp_clk_quad_eqn_c; - uint32_t pixel_clk_quad_eqn_a; - uint32_t pixel_clk_quad_eqn_b; - uint32_t pixel_clk_quad_eqn_c; - uint32_t phy_clk_quad_eqn_a; - uint32_t phy_clk_quad_eqn_b; - uint32_t phy_clk_quad_eqn_c; - - /* ---- Thermal Temperature Setting ---- */ - struct vega20_dpmlevel_enable_mask dpm_level_enable_mask; - - /* ---- Power Gating States ---- */ - bool uvd_power_gated; - bool vce_power_gated; - bool samu_power_gated; - bool need_long_memory_training; - - /* Internal settings to apply the application power optimization parameters */ - bool apply_optimized_settings; - uint32_t disable_dpm_mask; - - /* ---- Overdrive next setting ---- */ - struct vega20_odn_data odn_data; - bool gfxclk_overdrive; - bool memclk_overdrive; - - /* ---- Overdrive8 Setting ---- */ - struct vega20_od8_settings od8_settings; - - /* ---- Workload Mask ---- */ - uint32_t workload_mask; - - /* ---- SMU9 ---- */ - uint32_t smu_version; - struct smu_features smu_features[GNLD_FEATURES_MAX]; - struct vega20_smc_state_table smc_state_table; - - /* ---- Gfxoff ---- */ - bool gfxoff_allowed; - uint32_t counter_gfxoff; - - unsigned long metrics_time; - SmuMetrics_t metrics_table; - struct gpu_metrics_v1_0 gpu_metrics_table; - - bool pcie_parameters_override; - uint32_t pcie_gen_level1; - uint32_t pcie_width_level1; - - bool is_custom_profile_set; -}; - -#define VEGA20_DPM2_NEAR_TDP_DEC 10 -#define VEGA20_DPM2_ABOVE_SAFE_INC 5 -#define VEGA20_DPM2_BELOW_SAFE_INC 20 - -#define VEGA20_DPM2_LTA_WINDOW_SIZE 7 - -#define VEGA20_DPM2_LTS_TRUNCATE 0 - -#define VEGA20_DPM2_TDP_SAFE_LIMIT_PERCENT 80 - -#define VEGA20_DPM2_MAXPS_PERCENT_M 90 -#define VEGA20_DPM2_MAXPS_PERCENT_H 90 - -#define VEGA20_DPM2_PWREFFICIENCYRATIO_MARGIN 50 - -#define VEGA20_DPM2_SQ_RAMP_MAX_POWER 0x3FFF -#define VEGA20_DPM2_SQ_RAMP_MIN_POWER 0x12 -#define VEGA20_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 -#define VEGA20_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E -#define VEGA20_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF - -#define VEGA20_VOLTAGE_CONTROL_NONE 0x0 -#define VEGA20_VOLTAGE_CONTROL_BY_GPIO 0x1 -#define VEGA20_VOLTAGE_CONTROL_BY_SVID2 0x2 -#define VEGA20_VOLTAGE_CONTROL_MERGED 0x3 -/* To convert to Q8.8 format for firmware */ -#define VEGA20_Q88_FORMAT_CONVERSION_UNIT 256 - -#define VEGA20_UNUSED_GPIO_PIN 0x7F - -#define VEGA20_THERM_OUT_MODE_DISABLE 0x0 -#define VEGA20_THERM_OUT_MODE_THERM_ONLY 0x1 -#define VEGA20_THERM_OUT_MODE_THERM_VRHOT 0x2 - -#define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT 0xffffffff -#define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT 0xffffffff - -#define PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ -#define PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff -#define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT 0xffffffff -#define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT 0xffffffff - -#define VEGA20_UMD_PSTATE_GFXCLK_LEVEL 0x3 -#define VEGA20_UMD_PSTATE_SOCCLK_LEVEL 0x3 -#define VEGA20_UMD_PSTATE_MCLK_LEVEL 0x2 -#define VEGA20_UMD_PSTATE_UVDCLK_LEVEL 0x3 -#define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL 0x3 - -#endif /* _VEGA20_HWMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h deleted file mode 100644 index 613cb1989b3d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA20_INC_H -#define VEGA20_INC_H - -#include "asic_reg/thm/thm_11_0_2_offset.h" -#include "asic_reg/thm/thm_11_0_2_sh_mask.h" - -#include "asic_reg/mp/mp_9_0_offset.h" -#include "asic_reg/mp/mp_9_0_sh_mask.h" - -#include "asic_reg/nbio/nbio_7_4_offset.h" -#include "asic_reg/nbio/nbio_7_4_sh_mask.h" - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c deleted file mode 100644 index d7cc3d2d9e17..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "hwmgr.h" -#include "vega20_hwmgr.h" -#include "vega20_powertune.h" -#include "vega20_smumgr.h" -#include "vega20_ppsmc.h" -#include "vega20_inc.h" -#include "pp_debug.h" - -int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) -{ - struct vega20_hwmgr *data = - (struct vega20_hwmgr *)(hwmgr->backend); - - if (data->smu_features[GNLD_PPT].enabled) - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetPptLimit, n, - NULL); - - return 0; -} - -int vega20_validate_power_level_request(struct pp_hwmgr *hwmgr, - uint32_t tdp_percentage_adjustment, uint32_t tdp_absolute_value_adjustment) -{ - return (tdp_percentage_adjustment > hwmgr->platform_descriptor.TDPLimit) ? -1 : 0; -} - -static int vega20_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, - uint32_t adjust_percent) -{ - return smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_OverDriveSetPercentage, adjust_percent, - NULL); -} - -int vega20_power_control_set_level(struct pp_hwmgr *hwmgr) -{ - int adjust_percent, result = 0; - - if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { - adjust_percent = - hwmgr->platform_descriptor.TDPAdjustmentPolarity ? - hwmgr->platform_descriptor.TDPAdjustment : - (-1 * hwmgr->platform_descriptor.TDPAdjustment); - result = vega20_set_overdrive_target_percentage(hwmgr, - (uint32_t)adjust_percent); - } - return result; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h deleted file mode 100644 index d68c734c0f4e..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _VEGA20_POWERTUNE_H_ -#define _VEGA20_POWERTUNE_H_ - -int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); -int vega20_power_control_set_level(struct pp_hwmgr *hwmgr); -int vega20_validate_power_level_request(struct pp_hwmgr *hwmgr, - uint32_t tdp_percentage_adjustment, - uint32_t tdp_absolute_value_adjustment); -#endif /* _VEGA20_POWERTUNE_H_ */ - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_pptable.h deleted file mode 100644 index 2222e29405c6..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_pptable.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _VEGA20_PPTABLE_H_ -#define _VEGA20_PPTABLE_H_ - -#pragma pack(push, 1) - -#define ATOM_VEGA20_PP_THERMALCONTROLLER_NONE 0 -#define ATOM_VEGA20_PP_THERMALCONTROLLER_VEGA20 26 - -#define ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY 0x1 -#define ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 -#define ATOM_VEGA20_PP_PLATFORM_CAP_HARDWAREDC 0x4 -#define ATOM_VEGA20_PP_PLATFORM_CAP_BACO 0x8 -#define ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO 0x10 -#define ATOM_VEGA20_PP_PLATFORM_CAP_ENABLESHADOWPSTATE 0x20 - -#define ATOM_VEGA20_TABLE_REVISION_VEGA20 11 -#define ATOM_VEGA20_ODFEATURE_MAX_COUNT 32 -#define ATOM_VEGA20_ODSETTING_MAX_COUNT 32 -#define ATOM_VEGA20_PPCLOCK_MAX_COUNT 16 - -enum ATOM_VEGA20_ODFEATURE_ID { - ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS = 0, - ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE, - ATOM_VEGA20_ODFEATURE_UCLK_MAX, - ATOM_VEGA20_ODFEATURE_POWER_LIMIT, - ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT, //FanMaximumRpm - ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN, //FanMinimumPwm - ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN, //FanTargetTemperature - ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM, //MaxOpTemp - ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE, - ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL, - ATOM_VEGA20_ODFEATURE_COUNT, -}; - -enum ATOM_VEGA20_ODSETTING_ID { - ATOM_VEGA20_ODSETTING_GFXCLKFMAX = 0, - ATOM_VEGA20_ODSETTING_GFXCLKFMIN, - ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P1, - ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1, - ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P2, - ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2, - ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P3, - ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3, - ATOM_VEGA20_ODSETTING_UCLKFMAX, - ATOM_VEGA20_ODSETTING_POWERPERCENTAGE, - ATOM_VEGA20_ODSETTING_FANRPMMIN, - ATOM_VEGA20_ODSETTING_FANRPMACOUSTICLIMIT, - ATOM_VEGA20_ODSETTING_FANTARGETTEMPERATURE, - ATOM_VEGA20_ODSETTING_OPERATINGTEMPMAX, - ATOM_VEGA20_ODSETTING_COUNT, -}; -typedef enum ATOM_VEGA20_ODSETTING_ID ATOM_VEGA20_ODSETTING_ID; - -typedef struct _ATOM_VEGA20_OVERDRIVE8_RECORD -{ - UCHAR ucODTableRevision; - ULONG ODFeatureCount; - UCHAR ODFeatureCapabilities [ATOM_VEGA20_ODFEATURE_MAX_COUNT]; //OD feature support flags - ULONG ODSettingCount; - ULONG ODSettingsMax [ATOM_VEGA20_ODSETTING_MAX_COUNT]; //Upper Limit for each OD Setting - ULONG ODSettingsMin [ATOM_VEGA20_ODSETTING_MAX_COUNT]; //Lower Limit for each OD Setting -} ATOM_VEGA20_OVERDRIVE8_RECORD; - -enum ATOM_VEGA20_PPCLOCK_ID { - ATOM_VEGA20_PPCLOCK_GFXCLK = 0, - ATOM_VEGA20_PPCLOCK_VCLK, - ATOM_VEGA20_PPCLOCK_DCLK, - ATOM_VEGA20_PPCLOCK_ECLK, - ATOM_VEGA20_PPCLOCK_SOCCLK, - ATOM_VEGA20_PPCLOCK_UCLK, - ATOM_VEGA20_PPCLOCK_FCLK, - ATOM_VEGA20_PPCLOCK_DCEFCLK, - ATOM_VEGA20_PPCLOCK_DISPCLK, - ATOM_VEGA20_PPCLOCK_PIXCLK, - ATOM_VEGA20_PPCLOCK_PHYCLK, - ATOM_VEGA20_PPCLOCK_COUNT, -}; -typedef enum ATOM_VEGA20_PPCLOCK_ID ATOM_VEGA20_PPCLOCK_ID; - -typedef struct _ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD -{ - UCHAR ucTableRevision; - ULONG PowerSavingClockCount; // Count of PowerSavingClock Mode - ULONG PowerSavingClockMax [ATOM_VEGA20_PPCLOCK_MAX_COUNT]; // PowerSavingClock Mode Clock Maximum array In MHz - ULONG PowerSavingClockMin [ATOM_VEGA20_PPCLOCK_MAX_COUNT]; // PowerSavingClock Mode Clock Minimum array In MHz -} ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD; - -typedef struct _ATOM_VEGA20_POWERPLAYTABLE -{ - struct atom_common_table_header sHeader; - UCHAR ucTableRevision; - USHORT usTableSize; - ULONG ulGoldenPPID; - ULONG ulGoldenRevision; - USHORT usFormatID; - - ULONG ulPlatformCaps; - - UCHAR ucThermalControllerType; - - USHORT usSmallPowerLimit1; - USHORT usSmallPowerLimit2; - USHORT usBoostPowerLimit; - USHORT usODTurboPowerLimit; - USHORT usODPowerSavePowerLimit; - USHORT usSoftwareShutdownTemp; - - ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD PowerSavingClockTable; //PowerSavingClock Mode Clock Min/Max array - - ATOM_VEGA20_OVERDRIVE8_RECORD OverDrive8Table; //OverDrive8 Feature capabilities and Settings Range (Max and Min) - - USHORT usReserve[5]; - - PPTable_t smcPPTable; - -} ATOM_Vega20_POWERPLAYTABLE; - -#pragma pack(pop) - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c deleted file mode 100644 index f56a3cbdfa3b..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/fb.h> - -#include "smu11_driver_if.h" -#include "vega20_processpptables.h" -#include "ppatomfwctrl.h" -#include "atomfirmware.h" -#include "pp_debug.h" -#include "cgs_common.h" -#include "vega20_pptable.h" - -#define VEGA20_FAN_TARGET_TEMPERATURE_OVERRIDE 105 - -static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, - enum phm_platform_caps cap) -{ - if (enable) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); - else - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); -} - -static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) -{ - int index = GetIndexIntoMasterDataTable(powerplayinfo); - - u16 size; - u8 frev, crev; - const void *table_address = hwmgr->soft_pp_table; - - if (!table_address) { - table_address = (ATOM_Vega20_POWERPLAYTABLE *) - smu_atom_get_data_table(hwmgr->adev, index, - &size, &frev, &crev); - - hwmgr->soft_pp_table = table_address; - hwmgr->soft_pp_table_size = size; - } - - return table_address; -} - -#if 0 -static void dump_pptable(PPTable_t *pptable) -{ - int i; - - pr_info("Version = 0x%08x\n", pptable->Version); - - pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); - pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); - - pr_info("SocketPowerLimitAc0 = %d\n", pptable->SocketPowerLimitAc0); - pr_info("SocketPowerLimitAc0Tau = %d\n", pptable->SocketPowerLimitAc0Tau); - pr_info("SocketPowerLimitAc1 = %d\n", pptable->SocketPowerLimitAc1); - pr_info("SocketPowerLimitAc1Tau = %d\n", pptable->SocketPowerLimitAc1Tau); - pr_info("SocketPowerLimitAc2 = %d\n", pptable->SocketPowerLimitAc2); - pr_info("SocketPowerLimitAc2Tau = %d\n", pptable->SocketPowerLimitAc2Tau); - pr_info("SocketPowerLimitAc3 = %d\n", pptable->SocketPowerLimitAc3); - pr_info("SocketPowerLimitAc3Tau = %d\n", pptable->SocketPowerLimitAc3Tau); - pr_info("SocketPowerLimitDc = %d\n", pptable->SocketPowerLimitDc); - pr_info("SocketPowerLimitDcTau = %d\n", pptable->SocketPowerLimitDcTau); - pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc); - pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau); - pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx); - pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau); - - pr_info("TedgeLimit = %d\n", pptable->TedgeLimit); - pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit); - pr_info("ThbmLimit = %d\n", pptable->ThbmLimit); - pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit); - pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit); - pr_info("Tliquid1Limit = %d\n", pptable->Tliquid1Limit); - pr_info("Tliquid2Limit = %d\n", pptable->Tliquid2Limit); - pr_info("TplxLimit = %d\n", pptable->TplxLimit); - pr_info("FitLimit = %d\n", pptable->FitLimit); - - pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit); - pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold); - - pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage); - pr_info("padding8_limits = 0x%02x\n", pptable->padding8_limits); - pr_info("Tvr_SocLimit = %d\n", pptable->Tvr_SocLimit); - - pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc); - pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx); - - pr_info("UlvSmnclkDid = %d\n", pptable->UlvSmnclkDid); - pr_info("UlvMp1clkDid = %d\n", pptable->UlvMp1clkDid); - pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass); - pr_info("Padding234 = 0x%02x\n", pptable->Padding234); - - pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx); - pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc); - pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx); - pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc); - - pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx); - pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc); - - pr_info("[PPCLK_GFXCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_GFXCLK].padding, - pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c); - - pr_info("[PPCLK_VCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_VCLK].padding, - pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c); - - pr_info("[PPCLK_DCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_DCLK].padding, - pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c); - - pr_info("[PPCLK_ECLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_ECLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_ECLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_ECLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_ECLK].padding, - pptable->DpmDescriptor[PPCLK_ECLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_ECLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.c); - - pr_info("[PPCLK_SOCCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_SOCCLK].padding, - pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c); - - pr_info("[PPCLK_UCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_UCLK].padding, - pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c); - - pr_info("[PPCLK_DCEFCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_DCEFCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_DCEFCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_DCEFCLK].padding, - pptable->DpmDescriptor[PPCLK_DCEFCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_DCEFCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.c); - - pr_info("[PPCLK_DISPCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_DISPCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_DISPCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_DISPCLK].padding, - pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.c); - - pr_info("[PPCLK_PIXCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_PIXCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_PIXCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_PIXCLK].padding, - pptable->DpmDescriptor[PPCLK_PIXCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_PIXCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.c); - - pr_info("[PPCLK_PHYCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_PHYCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_PHYCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_PHYCLK].padding, - pptable->DpmDescriptor[PPCLK_PHYCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_PHYCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.c); - - pr_info("[PPCLK_FCLK]\n" - " .VoltageMode = 0x%02x\n" - " .SnapToDiscrete = 0x%02x\n" - " .NumDiscreteLevels = 0x%02x\n" - " .padding = 0x%02x\n" - " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" - " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n", - pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, - pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, - pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, - pptable->DpmDescriptor[PPCLK_FCLK].padding, - pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, - pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, - pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, - pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, - pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c); - - - pr_info("FreqTableGfx\n"); - for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]); - - pr_info("FreqTableVclk\n"); - for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]); - - pr_info("FreqTableDclk\n"); - for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]); - - pr_info("FreqTableEclk\n"); - for (i = 0; i < NUM_ECLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableEclk[i]); - - pr_info("FreqTableSocclk\n"); - for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]); - - pr_info("FreqTableUclk\n"); - for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]); - - pr_info("FreqTableFclk\n"); - for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]); - - pr_info("FreqTableDcefclk\n"); - for (i = 0; i < NUM_DCEFCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDcefclk[i]); - - pr_info("FreqTableDispclk\n"); - for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDispclk[i]); - - pr_info("FreqTablePixclk\n"); - for (i = 0; i < NUM_PIXCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePixclk[i]); - - pr_info("FreqTablePhyclk\n"); - for (i = 0; i < NUM_PHYCLK_DPM_LEVELS; i++) - pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePhyclk[i]); - - pr_info("DcModeMaxFreq[PPCLK_GFXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); - pr_info("DcModeMaxFreq[PPCLK_VCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_VCLK]); - pr_info("DcModeMaxFreq[PPCLK_DCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCLK]); - pr_info("DcModeMaxFreq[PPCLK_ECLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_ECLK]); - pr_info("DcModeMaxFreq[PPCLK_SOCCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); - pr_info("DcModeMaxFreq[PPCLK_UCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); - pr_info("DcModeMaxFreq[PPCLK_DCEFCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCEFCLK]); - pr_info("DcModeMaxFreq[PPCLK_DISPCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DISPCLK]); - pr_info("DcModeMaxFreq[PPCLK_PIXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PIXCLK]); - pr_info("DcModeMaxFreq[PPCLK_PHYCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PHYCLK]); - pr_info("DcModeMaxFreq[PPCLK_FCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); - pr_info("Padding8_Clks = %d\n", pptable->Padding8_Clks); - - pr_info("Mp0clkFreq\n"); - for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]); - - pr_info("Mp0DpmVoltage\n"); - for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]); - - pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); - pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate); - pr_info("CksEnableFreq = 0x%x\n", pptable->CksEnableFreq); - pr_info("Padding789 = 0x%x\n", pptable->Padding789); - pr_info("CksVoltageOffset[a = 0x%08x b = 0x%08x c = 0x%08x]\n", - pptable->CksVoltageOffset.a, - pptable->CksVoltageOffset.b, - pptable->CksVoltageOffset.c); - pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]); - pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]); - pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]); - pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]); - pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq); - pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource); - pr_info("Padding456 = 0x%x\n", pptable->Padding456); - - pr_info("LowestUclkReservedForUlv = %d\n", pptable->LowestUclkReservedForUlv); - pr_info("Padding8_Uclk[0] = 0x%x\n", pptable->Padding8_Uclk[0]); - pr_info("Padding8_Uclk[1] = 0x%x\n", pptable->Padding8_Uclk[1]); - pr_info("Padding8_Uclk[2] = 0x%x\n", pptable->Padding8_Uclk[2]); - - pr_info("PcieGenSpeed\n"); - for (i = 0; i < NUM_LINK_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->PcieGenSpeed[i]); - - pr_info("PcieLaneCount\n"); - for (i = 0; i < NUM_LINK_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]); - - pr_info("LclkFreq\n"); - for (i = 0; i < NUM_LINK_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->LclkFreq[i]); - - pr_info("EnableTdpm = %d\n", pptable->EnableTdpm); - pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature); - pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature); - pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit); - - pr_info("FanStopTemp = %d\n", pptable->FanStopTemp); - pr_info("FanStartTemp = %d\n", pptable->FanStartTemp); - - pr_info("FanGainEdge = %d\n", pptable->FanGainEdge); - pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot); - pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid); - pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx); - pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc); - pr_info("FanGainPlx = %d\n", pptable->FanGainPlx); - pr_info("FanGainHbm = %d\n", pptable->FanGainHbm); - pr_info("FanPwmMin = %d\n", pptable->FanPwmMin); - pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm); - pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm); - pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm); - pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature); - pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk); - pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable); - pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev); - - pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta); - pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta); - pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta); - pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved); - - pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); - pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); - pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]); - pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]); - - pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, - pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, - pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); - pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, - pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, - pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); - pr_info("dBtcGbGfxCksOn{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->dBtcGbGfxCksOn.a, - pptable->dBtcGbGfxCksOn.b, - pptable->dBtcGbGfxCksOn.c); - pr_info("dBtcGbGfxCksOff{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->dBtcGbGfxCksOff.a, - pptable->dBtcGbGfxCksOff.b, - pptable->dBtcGbGfxCksOff.c); - pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->dBtcGbGfxAfll.a, - pptable->dBtcGbGfxAfll.b, - pptable->dBtcGbGfxAfll.c); - pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->dBtcGbSoc.a, - pptable->dBtcGbSoc.b, - pptable->dBtcGbSoc.c); - pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", - pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, - pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); - pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", - pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, - pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); - - pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, - pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, - pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); - pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, - pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, - pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); - - pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); - pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); - - pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); - pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); - pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); - pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); - - pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); - pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); - pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); - pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); - - pr_info("XgmiLinkSpeed\n"); - for (i = 0; i < NUM_XGMI_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]); - pr_info("XgmiLinkWidth\n"); - for (i = 0; i < NUM_XGMI_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]); - pr_info("XgmiFclkFreq\n"); - for (i = 0; i < NUM_XGMI_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]); - pr_info("XgmiUclkFreq\n"); - for (i = 0; i < NUM_XGMI_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->XgmiUclkFreq[i]); - pr_info("XgmiSocclkFreq\n"); - for (i = 0; i < NUM_XGMI_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->XgmiSocclkFreq[i]); - pr_info("XgmiSocVoltage\n"); - for (i = 0; i < NUM_XGMI_LEVELS; i++) - pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]); - - pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides); - pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->ReservedEquation0.a, - pptable->ReservedEquation0.b, - pptable->ReservedEquation0.c); - pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->ReservedEquation1.a, - pptable->ReservedEquation1.b, - pptable->ReservedEquation1.c); - pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->ReservedEquation2.a, - pptable->ReservedEquation2.b, - pptable->ReservedEquation2.c); - pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", - pptable->ReservedEquation3.a, - pptable->ReservedEquation3.b, - pptable->ReservedEquation3.c); - - pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx); - pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc); - - pr_info("MGpuFanBoostLimitRpm = %d\n", pptable->MGpuFanBoostLimitRpm); - pr_info("padding16_Fan = %d\n", pptable->padding16_Fan); - - pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0); - pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0); - - pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); - pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); - - for (i = 0; i < 11; i++) - pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]); - - for (i = 0; i < 3; i++) - pr_info("Padding32[%d] = 0x%x\n", i, pptable->Padding32[i]); - - pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx); - pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc); - - pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); - pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); - pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); - pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); - - pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); - pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); - pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent); - pr_info("Padding8_V = 0x%x\n", pptable->Padding8_V); - - pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); - pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset); - pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); - - pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); - pr_info("SocOffset = 0x%x\n", pptable->SocOffset); - pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); - - pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); - pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset); - pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); - - pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); - pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset); - pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); - - pr_info("AcDcGpio = %d\n", pptable->AcDcGpio); - pr_info("AcDcPolarity = %d\n", pptable->AcDcPolarity); - pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio); - pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity); - - pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio); - pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity); - pr_info("Padding1 = 0x%x\n", pptable->Padding1); - pr_info("Padding2 = 0x%x\n", pptable->Padding2); - - pr_info("LedPin0 = %d\n", pptable->LedPin0); - pr_info("LedPin1 = %d\n", pptable->LedPin1); - pr_info("LedPin2 = %d\n", pptable->LedPin2); - pr_info("padding8_4 = 0x%x\n", pptable->padding8_4); - - pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled); - pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent); - pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq); - - pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled); - pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent); - pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq); - - pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled); - pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent); - pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq); - - pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled); - pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent); - pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq); - - for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) { - pr_info("I2cControllers[%d]:\n", i); - pr_info(" .Enabled = %d\n", - pptable->I2cControllers[i].Enabled); - pr_info(" .SlaveAddress = 0x%x\n", - pptable->I2cControllers[i].SlaveAddress); - pr_info(" .ControllerPort = %d\n", - pptable->I2cControllers[i].ControllerPort); - pr_info(" .ControllerName = %d\n", - pptable->I2cControllers[i].ControllerName); - pr_info(" .ThermalThrottler = %d\n", - pptable->I2cControllers[i].ThermalThrottler); - pr_info(" .I2cProtocol = %d\n", - pptable->I2cControllers[i].I2cProtocol); - pr_info(" .I2cSpeed = %d\n", - pptable->I2cControllers[i].I2cSpeed); - } - - for (i = 0; i < 10; i++) - pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]); - - for (i = 0; i < 8; i++) - pr_info("MmHubPadding[%d] = 0x%x\n", i, pptable->MmHubPadding[i]); -} -#endif - -static int check_powerplay_tables( - struct pp_hwmgr *hwmgr, - const ATOM_Vega20_POWERPLAYTABLE *powerplay_table) -{ - PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= - ATOM_VEGA20_TABLE_REVISION_VEGA20), - "Unsupported PPTable format!", return -1); - PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, - "Invalid PowerPlay Table!", return -1); - - if (powerplay_table->smcPPTable.Version != PPTABLE_V20_SMU_VERSION) { - pr_info("Unmatch PPTable version: " - "pptable from VBIOS is V%d while driver supported is V%d!", - powerplay_table->smcPPTable.Version, - PPTABLE_V20_SMU_VERSION); - return -EINVAL; - } - - //dump_pptable(&powerplay_table->smcPPTable); - - return 0; -} - -static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) -{ - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY), - PHM_PlatformCaps_PowerPlaySupport); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), - PHM_PlatformCaps_BiosPowerSourceControl); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_BACO), - PHM_PlatformCaps_BACO); - - set_hw_cap( - hwmgr, - 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO), - PHM_PlatformCaps_BAMACO); - - return 0; -} - -static int copy_overdrive_feature_capabilities_array( - struct pp_hwmgr *hwmgr, - uint8_t **pptable_info_array, - const uint8_t *pptable_array, - uint8_t od_feature_count) -{ - uint32_t array_size, i; - uint8_t *table; - bool od_supported = false; - - array_size = sizeof(uint8_t) * od_feature_count; - table = kzalloc(array_size, GFP_KERNEL); - if (NULL == table) - return -ENOMEM; - - for (i = 0; i < od_feature_count; i++) { - table[i] = le32_to_cpu(pptable_array[i]); - if (table[i]) - od_supported = true; - } - - *pptable_info_array = table; - - if (od_supported) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ACOverdriveSupport); - - return 0; -} - -static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable) -{ - struct atom_smc_dpm_info_v4_4 *smc_dpm_table; - int index = GetIndexIntoMasterDataTable(smc_dpm_info); - int i; - - PP_ASSERT_WITH_CODE( - smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL), - "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!", - return -1); - - ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx; - ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc; - - ppsmc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping; - ppsmc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping; - ppsmc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping; - ppsmc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping; - - ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask; - ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask; - ppsmc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent; - - ppsmc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent; - ppsmc_pptable->GfxOffset = smc_dpm_table->gfxoffset; - ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx; - - ppsmc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent; - ppsmc_pptable->SocOffset = smc_dpm_table->socoffset; - ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc; - - ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent; - ppsmc_pptable->Mem0Offset = smc_dpm_table->mem0offset; - ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0; - - ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent; - ppsmc_pptable->Mem1Offset = smc_dpm_table->mem1offset; - ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1; - - ppsmc_pptable->AcDcGpio = smc_dpm_table->acdcgpio; - ppsmc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity; - ppsmc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio; - ppsmc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity; - - ppsmc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio; - ppsmc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity; - ppsmc_pptable->Padding1 = smc_dpm_table->padding1; - ppsmc_pptable->Padding2 = smc_dpm_table->padding2; - - ppsmc_pptable->LedPin0 = smc_dpm_table->ledpin0; - ppsmc_pptable->LedPin1 = smc_dpm_table->ledpin1; - ppsmc_pptable->LedPin2 = smc_dpm_table->ledpin2; - - ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled; - ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent; - ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq; - - ppsmc_pptable->UclkSpreadEnabled = 0; - ppsmc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent; - ppsmc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq; - - ppsmc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled; - ppsmc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent; - ppsmc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq; - - ppsmc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled; - ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent; - ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq; - - for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) { - ppsmc_pptable->I2cControllers[i].Enabled = - smc_dpm_table->i2ccontrollers[i].enabled; - ppsmc_pptable->I2cControllers[i].SlaveAddress = - smc_dpm_table->i2ccontrollers[i].slaveaddress; - ppsmc_pptable->I2cControllers[i].ControllerPort = - smc_dpm_table->i2ccontrollers[i].controllerport; - ppsmc_pptable->I2cControllers[i].ThermalThrottler = - smc_dpm_table->i2ccontrollers[i].thermalthrottler; - ppsmc_pptable->I2cControllers[i].I2cProtocol = - smc_dpm_table->i2ccontrollers[i].i2cprotocol; - ppsmc_pptable->I2cControllers[i].I2cSpeed = - smc_dpm_table->i2ccontrollers[i].i2cspeed; - } - - return 0; -} - -static int override_powerplay_table_fantargettemperature(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - PPTable_t *ppsmc_pptable = (PPTable_t *)(pptable_information->smc_pptable); - - ppsmc_pptable->FanTargetTemperature = VEGA20_FAN_TARGET_TEMPERATURE_OVERRIDE; - - return 0; -} - -#define VEGA20_ENGINECLOCK_HARDMAX 198000 -static int init_powerplay_table_information( - struct pp_hwmgr *hwmgr, - const ATOM_Vega20_POWERPLAYTABLE *powerplay_table) -{ - struct phm_ppt_v3_information *pptable_information = - (struct phm_ppt_v3_information *)hwmgr->pptable; - uint32_t disable_power_control = 0; - uint32_t od_feature_count, od_setting_count, power_saving_clock_count; - int result; - - hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType; - pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType; - hwmgr->thermal_controller.fanInfo.ulMinRPM = 0; - hwmgr->thermal_controller.fanInfo.ulMaxRPM = powerplay_table->smcPPTable.FanMaximumRpm; - - set_hw_cap(hwmgr, - ATOM_VEGA20_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, - PHM_PlatformCaps_ThermalController); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); - - if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) { - od_feature_count = - (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) > - ATOM_VEGA20_ODFEATURE_COUNT) ? - ATOM_VEGA20_ODFEATURE_COUNT : - le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount); - od_setting_count = - (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) > - ATOM_VEGA20_ODSETTING_COUNT) ? - ATOM_VEGA20_ODSETTING_COUNT : - le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount); - - copy_overdrive_feature_capabilities_array(hwmgr, - &pptable_information->od_feature_capabilities, - powerplay_table->OverDrive8Table.ODFeatureCapabilities, - od_feature_count); - phm_copy_overdrive_settings_limits_array(hwmgr, - &pptable_information->od_settings_max, - powerplay_table->OverDrive8Table.ODSettingsMax, - od_setting_count); - phm_copy_overdrive_settings_limits_array(hwmgr, - &pptable_information->od_settings_min, - powerplay_table->OverDrive8Table.ODSettingsMin, - od_setting_count); - } - - pptable_information->us_small_power_limit1 = le16_to_cpu(powerplay_table->usSmallPowerLimit1); - pptable_information->us_small_power_limit2 = le16_to_cpu(powerplay_table->usSmallPowerLimit2); - pptable_information->us_boost_power_limit = le16_to_cpu(powerplay_table->usBoostPowerLimit); - pptable_information->us_od_turbo_power_limit = le16_to_cpu(powerplay_table->usODTurboPowerLimit); - pptable_information->us_od_powersave_power_limit = le16_to_cpu(powerplay_table->usODPowerSavePowerLimit); - - pptable_information->us_software_shutdown_temp = le16_to_cpu(powerplay_table->usSoftwareShutdownTemp); - - hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]); - - disable_power_control = 0; - if (!disable_power_control && hwmgr->platform_descriptor.TDPODLimit) - /* enable TDP overdrive (PowerControl) feature as well if supported */ - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerControl); - - if (powerplay_table->PowerSavingClockTable.ucTableRevision == 1) { - power_saving_clock_count = - (le32_to_cpu(powerplay_table->PowerSavingClockTable.PowerSavingClockCount) >= - ATOM_VEGA20_PPCLOCK_COUNT) ? - ATOM_VEGA20_PPCLOCK_COUNT : - le32_to_cpu(powerplay_table->PowerSavingClockTable.PowerSavingClockCount); - phm_copy_clock_limits_array(hwmgr, - &pptable_information->power_saving_clock_max, - powerplay_table->PowerSavingClockTable.PowerSavingClockMax, - power_saving_clock_count); - phm_copy_clock_limits_array(hwmgr, - &pptable_information->power_saving_clock_min, - powerplay_table->PowerSavingClockTable.PowerSavingClockMin, - power_saving_clock_count); - } - - pptable_information->smc_pptable = kmalloc(sizeof(PPTable_t), GFP_KERNEL); - if (pptable_information->smc_pptable == NULL) - return -ENOMEM; - - memcpy(pptable_information->smc_pptable, - &(powerplay_table->smcPPTable), - sizeof(PPTable_t)); - - - result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable)); - if (result) - return result; - - result = override_powerplay_table_fantargettemperature(hwmgr); - - return result; -} - -static int vega20_pp_tables_initialize(struct pp_hwmgr *hwmgr) -{ - int result = 0; - const ATOM_Vega20_POWERPLAYTABLE *powerplay_table; - - hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL); - PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), - "Failed to allocate hwmgr->pptable!", return -ENOMEM); - - powerplay_table = get_powerplay_table(hwmgr); - PP_ASSERT_WITH_CODE((powerplay_table != NULL), - "Missing PowerPlay Table!", return -1); - - result = check_powerplay_tables(hwmgr, powerplay_table); - PP_ASSERT_WITH_CODE((result == 0), - "check_powerplay_tables failed", return result); - - result = set_platform_caps(hwmgr, - le32_to_cpu(powerplay_table->ulPlatformCaps)); - PP_ASSERT_WITH_CODE((result == 0), - "set_platform_caps failed", return result); - - result = init_powerplay_table_information(hwmgr, powerplay_table); - PP_ASSERT_WITH_CODE((result == 0), - "init_powerplay_table_information failed", return result); - - return result; -} - -static int vega20_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v3_information *pp_table_info = - (struct phm_ppt_v3_information *)(hwmgr->pptable); - - kfree(pp_table_info->power_saving_clock_max); - pp_table_info->power_saving_clock_max = NULL; - - kfree(pp_table_info->power_saving_clock_min); - pp_table_info->power_saving_clock_min = NULL; - - kfree(pp_table_info->od_feature_capabilities); - pp_table_info->od_feature_capabilities = NULL; - - kfree(pp_table_info->od_settings_max); - pp_table_info->od_settings_max = NULL; - - kfree(pp_table_info->od_settings_min); - pp_table_info->od_settings_min = NULL; - - kfree(pp_table_info->smc_pptable); - pp_table_info->smc_pptable = NULL; - - kfree(hwmgr->pptable); - hwmgr->pptable = NULL; - - return 0; -} - -const struct pp_table_func vega20_pptable_funcs = { - .pptable_init = vega20_pp_tables_initialize, - .pptable_fini = vega20_pp_tables_uninitialize, -}; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.h deleted file mode 100644 index 846c2cb40b35..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA20_PROCESSPPTABLES_H -#define VEGA20_PROCESSPPTABLES_H - -#include "hwmgr.h" - -extern const struct pp_table_func vega20_pptable_funcs; - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c deleted file mode 100644 index 7add2f60f49c..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "vega20_thermal.h" -#include "vega20_hwmgr.h" -#include "vega20_smumgr.h" -#include "vega20_ppsmc.h" -#include "vega20_inc.h" -#include "soc15_common.h" -#include "pp_debug.h" - -static int vega20_disable_fan_control_feature(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = hwmgr->backend; - int ret = 0; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - ret = vega20_enable_smc_features( - hwmgr, false, - data->smu_features[GNLD_FAN_CONTROL]. - smu_feature_bitmap); - PP_ASSERT_WITH_CODE(!ret, - "Disable FAN CONTROL feature Failed!", - return ret); - data->smu_features[GNLD_FAN_CONTROL].enabled = false; - } - - return ret; -} - -int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) - return vega20_disable_fan_control_feature(hwmgr); - - return 0; -} - -static int vega20_enable_fan_control_feature(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = hwmgr->backend; - int ret = 0; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) { - ret = vega20_enable_smc_features( - hwmgr, true, - data->smu_features[GNLD_FAN_CONTROL]. - smu_feature_bitmap); - PP_ASSERT_WITH_CODE(!ret, - "Enable FAN CONTROL feature Failed!", - return ret); - data->smu_features[GNLD_FAN_CONTROL].enabled = true; - } - - return ret; -} - -int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - struct vega20_hwmgr *data = hwmgr->backend; - - if (data->smu_features[GNLD_FAN_CONTROL].supported) - return vega20_enable_fan_control_feature(hwmgr); - - return 0; -} - -static int vega20_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - struct amdgpu_device *adev = hwmgr->adev; - - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, TMIN, 0)); - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), - CG_FDO_CTRL2, FDO_PWM_MODE, mode)); - - return 0; -} - -static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) -{ - int ret = 0; - - PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_GetCurrentRpm, - current_rpm)) == 0, - "Attempt to get current RPM from SMC Failed!", - return ret); - - return 0; -} - -int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t *speed) -{ - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - PPTable_t *pp_table = &(data->smc_state_table.pp_table); - uint32_t current_rpm, percent = 0; - int ret = 0; - - ret = vega20_get_current_rpm(hwmgr, ¤t_rpm); - if (ret) - return ret; - - percent = current_rpm * 100 / pp_table->FanMaximumRpm; - - *speed = percent > 100 ? 100 : percent; - - return 0; -} - -int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t speed) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t duty100; - uint32_t duty; - uint64_t tmp64; - - if (speed > 100) - speed = 100; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) - vega20_fan_ctrl_stop_smc_fan_control(hwmgr); - - duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), - CG_FDO_CTRL1, FMAX_DUTY100); - - if (duty100 == 0) - return -EINVAL; - - tmp64 = (uint64_t)speed * duty100; - do_div(tmp64, 100); - duty = (uint32_t)tmp64; - - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), - CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); - - return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); -} - -int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info) -{ - memset(fan_speed_info, 0, sizeof(*fan_speed_info)); - fan_speed_info->supports_percent_read = true; - fan_speed_info->supports_percent_write = true; - fan_speed_info->supports_rpm_read = true; - fan_speed_info->supports_rpm_write = true; - - return 0; -} - -int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) -{ - *speed = 0; - - return vega20_get_current_rpm(hwmgr, speed); -} - -int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t tach_period, crystal_clock_freq; - int result = 0; - - if (!speed) - return -EINVAL; - - if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { - result = vega20_fan_ctrl_stop_smc_fan_control(hwmgr); - if (result) - return result; - } - - crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); - tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); - WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), - CG_TACH_CTRL, TARGET_PERIOD, - tach_period)); - - return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM); -} - -/** -* Reads the remote temperature from the SIslands thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - int temp = 0; - - temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); - - temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> - CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; - - temp = temp & 0x1ff; - - temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - return temp; -} - -/** -* Set the requested temperature range for high and low alert signals -* -* @param hwmgr The address of the hardware manager. -* @param range Temperature range to be programmed for -* high and low alert signals -* @exception PP_Result_BadInput if the input data is not valid. -*/ -static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range) -{ - struct amdgpu_device *adev = hwmgr->adev; - int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - uint32_t val; - - if (low < range->min) - low = range->min; - if (high > range->max) - high = range->max; - - if (low > high) - return -EINVAL; - - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); - - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); - - return 0; -} - -/** -* Enable thermal alerts on the RV770 thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -static int vega20_thermal_enable_alert(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - uint32_t val = 0; - - val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); - val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); - val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); - - return 0; -} - -/** -* Disable thermal alerts on the RV770 thermal controller. -* @param hwmgr The address of the hardware manager. -*/ -int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr) -{ - struct amdgpu_device *adev = hwmgr->adev; - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); - - return 0; -} - -/** -* Uninitialize the thermal controller. -* Currently just disables alerts. -* @param hwmgr The address of the hardware manager. -*/ -int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) -{ - int result = vega20_thermal_disable_alert(hwmgr); - - return result; -} - -/** -* Set up the fan table to control the fan using the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -static int vega20_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) -{ - int ret; - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - PPTable_t *table = &(data->smc_state_table.pp_table); - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetFanTemperatureTarget, - (uint32_t)table->FanTargetTemperature, - NULL); - - return ret; -} - -int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range) -{ - int ret = 0; - - if (range == NULL) - return -EINVAL; - - ret = vega20_thermal_set_temperature_range(hwmgr, range); - if (ret) - return ret; - - ret = vega20_thermal_enable_alert(hwmgr); - if (ret) - return ret; - - ret = vega20_thermal_setup_fan_table(hwmgr); - - return ret; -}; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h deleted file mode 100644 index 2d1769bbd24e..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef VEGA20_THERMAL_H -#define VEGA20_THERMAL_H - -#include "hwmgr.h" - -struct vega20_temperature { - uint16_t edge_temp; - uint16_t hot_spot_temp; - uint16_t hbm_temp; - uint16_t vr_soc_temp; - uint16_t vr_mem_temp; - uint16_t liquid1_temp; - uint16_t liquid2_temp; - uint16_t plx_temp; -}; - -#define VEGA20_THERMAL_HIGH_ALERT_MASK 0x1 -#define VEGA20_THERMAL_LOW_ALERT_MASK 0x2 - -#define VEGA20_THERMAL_MINIMUM_TEMP_READING -256 -#define VEGA20_THERMAL_MAXIMUM_TEMP_READING 255 - -#define VEGA20_THERMAL_MINIMUM_ALERT_TEMP 0 -#define VEGA20_THERMAL_MAXIMUM_ALERT_TEMP 255 - -#define FDO_PWM_MODE_STATIC 1 -#define FDO_PWM_MODE_STATIC_RPM 5 - -extern int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr); -extern int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info); -extern int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, - uint32_t *speed); -extern int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, - uint32_t speed); -extern int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t *speed); -extern int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t speed); -extern int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr); -extern int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr, - struct PP_TemperatureRange *range); -extern int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); - -#endif - |