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authorPrike Liang <Prike.Liang@amd.com>2019-09-24 14:40:09 +0800
committerAlex Deucher <alexander.deucher@amd.com>2019-10-03 09:11:04 -0500
commit4045f36fce82ba7023bb7849190e04df8595e2f0 (patch)
tree0b9ec103ec89c31a51a7fe417ddc121b480ad44b /drivers/gpu/drm/amd/powerplay/inc
parentaf1ec44f9a56354bac98d000cbac2c8fed1f2e87 (diff)
drm/amd/powerplay: implement the interface for setting soft freq range
The APU soft freq range set by different way from DGPU, thus need implement the function respectively base on each common SMU part. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc')
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index f1b378965551..504d6487c3d2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -548,6 +548,7 @@ struct smu_funcs
int (*baco_reset)(struct smu_context *smu);
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
};
#define smu_init_microcode(smu) \
@@ -777,6 +778,8 @@ struct smu_funcs
#define smu_get_dpm_uclk_limited(smu, clock, max) \
((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
+#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,