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authorRex Zhu <Rex.Zhu@amd.com>2016-09-09 13:29:47 +0800
committerAlex Deucher <alexander.deucher@amd.com>2016-09-19 13:22:10 -0400
commit34a564eaf5289ad72798a07dc475b85fbffc68f2 (patch)
treed5eaa6b9aae5e44d16fff2e417372dd4adb1d6c5 /drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
parent599a7e9fe1b683d04f889d68f866f5548b1e0239 (diff)
drm/amd/powerplay: implement fw image related smum interface for Polaris.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h')
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h23
1 files changed, 19 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
index 7c2445f1f043..1ab9b1d9df9a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
@@ -24,9 +24,13 @@
#ifndef _POLARIS10_SMUMANAGER_H
#define _POLARIS10_SMUMANAGER_H
-#include <polaris10_ppsmc.h>
+
#include <pp_endian.h>
#include "smu74.h"
+#include "smu74_discrete.h"
+
+
+#define SMC_RAM_END 0x40000
struct polaris10_avfs {
enum AVFS_BTC_STATUS avfs_btc_status;
@@ -65,7 +69,13 @@ struct polaris10_smumgr {
uint8_t *mec_image;
struct polaris10_buffer_entry smu_buffer;
struct polaris10_buffer_entry header_buffer;
- uint32_t soft_regs_start;
+
+ uint32_t soft_regs_start;
+ uint32_t dpm_table_start;
+ uint32_t mc_reg_table_start;
+ uint32_t fan_table_start;
+ uint32_t arb_table_start;
+
uint8_t *read_rrm_straps;
uint32_t read_drm_straps_mc_address_high;
uint32_t read_drm_straps_mc_address_low;
@@ -74,15 +84,20 @@ struct polaris10_smumgr {
uint8_t protected_mode;
uint8_t security_hard_key;
struct polaris10_avfs avfs;
+ SMU74_Discrete_DpmTable smc_state_table;
+ struct SMU74_Discrete_Ulv ulv_setting;
+ struct SMU74_Discrete_PmFuses power_tune_table;
+ struct polaris10_range_table range_table[NUM_SCLK_RANGE];
+ const struct polaris10_pt_defaults *power_tune_defaults;
+ uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS];
+ uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK];
};
int polaris10_smum_init(struct pp_smumgr *smumgr);
-
int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit);
#endif
-