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authorDave Airlie <airlied@redhat.com>2017-09-29 12:15:46 +1000
committerAlex Deucher <alexander.deucher@amd.com>2017-09-29 12:24:40 -0400
commit6f5c2f9d3c5c335ae86203f9548e1a861bdd154a (patch)
treeceb3be03b7535f4aea6d5df0cf2818ba043d2d98 /drivers/gpu/drm/amd/powerplay/smumgr
parentc6622f3afcb4da90e2600ee98e91a8a5640f7a27 (diff)
amdgpu/pp: rewrite polaris pwrvirus upload code.
This reduces the pwrvirus table size by 30k, by moving the sequences of writes to the data register into blocks. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smumgr')
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c37
1 files changed, 27 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index f039320fa794..61ee6281fbda 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -60,27 +60,44 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
-static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
+static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)
{
int i;
- int result = -EINVAL;
uint32_t reg, data;
- const PWR_Command_Table *pvirus = pwr_virus_table;
-
- for (i = 0; i < ARRAY_SIZE(pwr_virus_table); i++) {
+ for (i = 0; i < size; i++) {
reg = pvirus->reg;
data = pvirus->data;
- if (reg != 0xffffffff) {
+ if (reg != 0xffffffff)
cgs_write_register(hwmgr->device, reg, data);
- } else {
- result = 0;
+ else
break;
- }
pvirus++;
}
+}
- return result;
+static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)
+{
+ int i;
+ cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);
+ cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);
+ cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);
+ for (i = 0; i < section->dfy_size; i++)
+ cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);
+}
+
+static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
+{
+ execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);
+ execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));
+
+ return 0;
}
static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)