diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2019-12-20 14:53:35 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-12-23 14:59:57 -0500 |
| commit | d24d26540bab53e093ec5e290071883e0f1d152c (patch) | |
| tree | 94305d51854306efe093678cbbd0a7901930ec57 /drivers/gpu/drm/amd/powerplay | |
| parent | 46cf2fecf5971b4019c6565c2a895a77f574eb9b (diff) | |
drm/amdgpu/smu/navi: Adjust default behavior for peak sclk profile
Fetch the sclk from the pptable if there is no specified sclk for
the board.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index bf87e93b26fc..c33744a0d46b 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1587,7 +1587,7 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; int ret = 0; uint32_t sclk_freq = 0, uclk_freq = 0; - uint32_t uclk_level = 0; + uint32_t sclk_level = 0, uclk_level = 0; switch (adev->asic_type) { case CHIP_NAVI10: @@ -1629,7 +1629,13 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) } break; default: - return -EINVAL; + ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level); + if (ret) + return ret; + ret = smu_get_dpm_freq_by_index(smu, SMU_SCLK, sclk_level - 1, &sclk_freq); + if (ret) + return ret; + break; } ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level); |