diff options
| author | Victor Zhao <Victor.Zhao@amd.com> | 2024-08-07 17:32:27 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-08-13 12:12:51 -0400 |
| commit | ef6c2cb349c708676b7820c36a5beb75868ad544 (patch) | |
| tree | f4df4cdb929b6c12c31c0c95896e43a62bef2ec9 /drivers/gpu/drm/amd | |
| parent | bbec7cea6fa4a0463d4766ed0e6bb347773d3949 (diff) | |
drm/amd/sriov: extend NV_MAILBOX_POLL_MSG_TIMEDOUT
on MI300/MI308 UBB products, when doing mode1 reset, since 1 gpu need to
wait all 8 gpus finish mode1 reset and then do re-init. As observed,
sometimes the gpu which triggered the reset need to wait 15s for all
gpus to finish.
If poll msg timeout, guest driver will send the reset message again, and
may mess up the following reinit sequence on other gpus.
So extend the time to cover the maximum time needed to recover.
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h index caf616a2c8a6..1d099ffb3a5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h @@ -25,7 +25,7 @@ #define __MXGPU_NV_H__ #define NV_MAILBOX_POLL_ACK_TIMEDOUT 500 -#define NV_MAILBOX_POLL_MSG_TIMEDOUT 6000 +#define NV_MAILBOX_POLL_MSG_TIMEDOUT 15000 #define NV_MAILBOX_POLL_FLR_TIMEDOUT 10000 #define NV_MAILBOX_POLL_MSG_REP_MAX 11 |