summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
diff options
context:
space:
mode:
authorzain wang <wzz@rock-chips.com>2018-04-23 12:49:52 +0200
committerAndrzej Hajda <a.hajda@samsung.com>2018-04-24 08:34:43 +0200
commit4805b7ce5031381e8fe9f25b0f5a323653259178 (patch)
tree9953ea55df9ce763b5f3db9b93d67fe61a4554a9 /drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
parentc4d3b1a21ec2d3a9065b46c13021344ffa7ecead (diff)
drm/bridge: analogix_dp: Fix incorrect operations with register ANALOGIX_DP_FUNC_EN_1
Register ANALOGIX_DP_FUNC_EN_1(offset 0x18), Rockchip is different to Exynos: on Exynos edp phy, BIT 7 MASTER_VID_FUNC_EN_N BIT 6 reserved BIT 5 SLAVE_VID_FUNC_EN_N on Rockchip edp phy, BIT 7 reserved BIT 6 RK_VID_CAP_FUNC_EN_N BIT 5 RK_VID_FIFO_FUNC_EN_N So, we should do some private operations to Rockchip. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by: zain wang <wzz@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-17-enric.balletbo@collabora.com
Diffstat (limited to 'drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h')
-rw-r--r--drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index b633a4a5082a..0cf27c731727 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -127,7 +127,9 @@
/* ANALOGIX_DP_FUNC_EN_1 */
#define MASTER_VID_FUNC_EN_N (0x1 << 7)
+#define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
+#define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
#define AUD_FUNC_EN_N (0x1 << 3)
#define HDCP_FUNC_EN_N (0x1 << 2)