diff options
| author | Yakir Yang <ykk@rock-chips.com> | 2016-02-15 19:10:54 +0800 |
|---|---|---|
| committer | Yakir Yang <ykk@rock-chips.com> | 2016-04-05 10:13:06 +0800 |
| commit | bcec20fd5ad63ea03427c40027b33c7fd995c8bc (patch) | |
| tree | bfe8f00639fd5d6b852bfd0ff22a04d90fd34c2c /drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | |
| parent | be91c36247089d41fd76cd51d338203de65294ff (diff) | |
drm: bridge: analogix/dp: add some rk3288 special registers setting
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Diffstat (limited to 'drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h')
| -rw-r--r-- | drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 738db4c474a0..337912b0aeab 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -22,6 +22,14 @@ #define ANALOGIX_DP_VIDEO_CTL_8 0x3C #define ANALOGIX_DP_VIDEO_CTL_10 0x44 +#define ANALOGIX_DP_PLL_REG_1 0xfc +#define ANALOGIX_DP_PLL_REG_2 0x9e4 +#define ANALOGIX_DP_PLL_REG_3 0x9e8 +#define ANALOGIX_DP_PLL_REG_4 0x9ec +#define ANALOGIX_DP_PLL_REG_5 0xa00 + +#define ANALOGIX_DP_PD 0x12c + #define ANALOGIX_DP_LANE_MAP 0x35C #define ANALOGIX_DP_ANALOG_CTL_1 0x370 @@ -154,6 +162,10 @@ #define VSYNC_POLARITY_CFG (0x1 << 1) #define HSYNC_POLARITY_CFG (0x1 << 0) +/* ANALOGIX_DP_PLL_REG_1 */ +#define REF_CLK_24M (0x1 << 1) +#define REF_CLK_27M (0x0 << 1) + /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) |