diff options
| author | Imre Deak <imre.deak@intel.com> | 2022-04-15 00:06:53 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-04-20 20:42:12 +0300 |
| commit | 979e1b32e0e202197f182ec0abfadecbdd53b1ec (patch) | |
| tree | 6e1619c960caef1e2f23adb717b7a850ecc41726 /drivers/gpu/drm/i915/display/g4x_dp.c | |
| parent | eb6dedcc194a5bdbe7e47ad111771abb4ebdd2b8 (diff) | |
drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the corresponding port is TC1. To make it clear what
port/domain the code refers to add a mapping between them which matches
the bspec terms on different display versions.
This also allows for removing the aliasing in enum values in a follow-up
patch.
v2: Add the functions to intel_display_power.c, use
intel_display_power_ prefix.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414210657.1785773-14-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/g4x_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/g4x_dp.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 16bb21ad898b..5a957acebfd6 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -13,6 +13,7 @@ #include "intel_connector.h" #include "intel_crtc.h" #include "intel_de.h" +#include "intel_display_power.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" @@ -1375,7 +1376,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, dig_port->max_lanes = 4; intel_encoder->type = INTEL_OUTPUT_DP; - intel_encoder->power_domain = intel_port_to_power_domain(port); + intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); if (IS_CHERRYVIEW(dev_priv)) { if (port == PORT_D) intel_encoder->pipe_mask = BIT(PIPE_C); |