diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2019-06-14 17:42:10 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2019-06-17 13:40:20 -0700 |
| commit | c6f7acb80abf5f73be4ee08541e3393a0146b15e (patch) | |
| tree | 630dc79db0f9f5c1074d8528a07a711825a39d71 /drivers/gpu/drm/i915/display/intel_bios.c | |
| parent | 32a1963148277407f7af0160da2b7c0527afc8a4 (diff) | |
drm/i915/ehl: Introduce Mule Creek Canyon PCH
Although EHL introduces a new PCH, the South Display part of the PCH
that we care about is nearly identical to ICP, just with some pins
remapped. Most notably, Port C is mapped to the pins that ICP uses for
TC Port 1.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190615004210.16656-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_bios.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bios.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 270719fabbc5..c4710889cb32 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1348,12 +1348,21 @@ static const u8 icp_ddc_pin_map[] = { [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, }; +static const u8 mcc_ddc_pin_map[] = { + [MCC_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, + [MCC_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, + [MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, +}; + static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) { const u8 *ddc_pin_map; int n_entries; - if (HAS_PCH_ICP(dev_priv)) { + if (HAS_PCH_MCC(dev_priv)) { + ddc_pin_map = mcc_ddc_pin_map; + n_entries = ARRAY_SIZE(mcc_ddc_pin_map); + } else if (HAS_PCH_ICP(dev_priv)) { ddc_pin_map = icp_ddc_pin_map; n_entries = ARRAY_SIZE(icp_ddc_pin_map); } else if (HAS_PCH_CNP(dev_priv)) { |