diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-01-11 18:37:11 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-01-29 19:05:02 +0200 |
| commit | 6ede6b0616b23611560ec9dc4053ae35651810d2 (patch) | |
| tree | 36d6f9473cd6f6e896bb5210b2210de8b5982cf6 /drivers/gpu/drm/i915/display/intel_display.c | |
| parent | 4bb18054adc4939a3c1f895d8d0a1556a5f8b26a (diff) | |
drm/i915: Implement async flips for vlv/chv
Add support for async flips on vlv/chv. Unlike all the other
platforms vlv/chv do not use the async flip bit in DSPCNTR and
instead we select between async vs. sync flips based on the
surface address register. The normal DSPSURF generates sync
flips DSPADDR_VLV generates async flips. And as usual the
interrupt bits are different from the other platforms.
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-12-ville.syrjala@linux.intel.com
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2ae49da32588..55e9240f6081 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1319,9 +1319,7 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr static bool has_async_flips(struct drm_i915_private *i915) { - return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) || - IS_HASWELL(i915) || IS_IVYBRIDGE(i915) || - IS_GEN_RANGE(i915, 5, 6); + return INTEL_GEN(i915) >= 5; } static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |