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authorMatt Roper <matthew.d.roper@intel.com>2019-07-09 11:39:33 -0700
committerMatt Roper <matthew.d.roper@intel.com>2019-07-10 18:29:55 -0700
commitd8fe2ab6bb283dd9b511ea9bea52874fafd3de61 (patch)
tree5372af7235272b443e52ea6dd917572027690188 /drivers/gpu/drm/i915/display/intel_display.c
parentdc867bc7d88769910b58748040240906540ea8c1 (diff)
drm/i915: Transition port type checks to phy checks
Transition the remaining uses of intel_port_is_* over to the equivalent intel_phy_is_* functions and drop the port functions. v5: Fix a call in a debug function that's only called when CONFIG_DRM_I915_DEBUG_RUNTIME_PM is on. (CI) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190709183934.445-5-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_display.c38
1 files changed, 10 insertions, 28 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 44c79f8bd028..c2ed4bd8d56b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6671,20 +6671,6 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
-{
- if (port == PORT_NONE)
- return false;
-
- if (IS_ELKHARTLAKE(dev_priv))
- return port <= PORT_C;
-
- if (INTEL_GEN(dev_priv) >= 11)
- return port <= PORT_B;
-
- return false;
-}
-
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
@@ -6699,14 +6685,6 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
-{
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
- return port >= PORT_C && port <= PORT_F;
-
- return false;
-}
-
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
@@ -6756,8 +6734,9 @@ enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port)
{
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
- if (intel_port_is_tc(dev_priv, dig_port->base.port) &&
+ if (intel_phy_is_tc(dev_priv, phy) &&
dig_port->tc_mode == TC_PORT_TBT_ALT) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
@@ -10091,16 +10070,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
enum port port,
struct intel_crtc_state *pipe_config)
{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
enum icl_port_dpll_id port_dpll_id;
enum intel_dpll_id id;
u32 temp;
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
temp = I915_READ(ICL_DPCLKA_CFGCR0) &
- DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
+ ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- } else if (intel_port_is_tc(dev_priv, port)) {
+ } else if (intel_phy_is_tc(dev_priv, phy)) {
u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
if (clk_sel == DDI_CLK_SEL_MG) {
@@ -16962,9 +16942,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
/* Sanitize the TypeC port mode upfront, encoders depend on this */
for_each_intel_encoder(dev, encoder) {
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
/* We need to sanitize only the MST primary port. */
if (encoder->type != INTEL_OUTPUT_DP_MST &&
- intel_port_is_tc(dev_priv, encoder->port))
+ intel_phy_is_tc(dev_priv, phy))
intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
}