diff options
| author | Imre Deak <imre.deak@intel.com> | 2022-04-15 00:06:54 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-04-20 20:42:12 +0300 |
| commit | c97bbab02ad7d174b50541864bfa45cf1e4ee14f (patch) | |
| tree | c224f921f8c18a43573ad8ffa32ab6c7f484d3a8 /drivers/gpu/drm/i915/display/intel_display_power.h | |
| parent | 979e1b32e0e202197f182ec0abfadecbdd53b1ec (diff) | |
drm/i915: Remove the aliasing of power domain enum values
Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1. Make this clearer by removing the aliasing which is
possible after a previous patch converting the mask to a bitmap.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414210657.1785773-15-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_power.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.h | 26 |
1 files changed, 7 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 2ea30a4cfaa8..b58c5bada6d8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -48,18 +48,15 @@ enum intel_display_power_domain { POWER_DOMAIN_PORT_DDI_LANES_D, POWER_DOMAIN_PORT_DDI_LANES_E, POWER_DOMAIN_PORT_DDI_LANES_F, - POWER_DOMAIN_PORT_DDI_LANES_G, - POWER_DOMAIN_PORT_DDI_LANES_H, - POWER_DOMAIN_PORT_DDI_LANES_I, - POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /* tgl+ */ + POWER_DOMAIN_PORT_DDI_LANES_TC1, POWER_DOMAIN_PORT_DDI_LANES_TC2, POWER_DOMAIN_PORT_DDI_LANES_TC3, POWER_DOMAIN_PORT_DDI_LANES_TC4, POWER_DOMAIN_PORT_DDI_LANES_TC5, POWER_DOMAIN_PORT_DDI_LANES_TC6, - POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */ + POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, POWER_DOMAIN_PORT_DDI_IO_A, @@ -68,18 +65,15 @@ enum intel_display_power_domain { POWER_DOMAIN_PORT_DDI_IO_D, POWER_DOMAIN_PORT_DDI_IO_E, POWER_DOMAIN_PORT_DDI_IO_F, - POWER_DOMAIN_PORT_DDI_IO_G, - POWER_DOMAIN_PORT_DDI_IO_H, - POWER_DOMAIN_PORT_DDI_IO_I, - POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */ + POWER_DOMAIN_PORT_DDI_IO_TC1, POWER_DOMAIN_PORT_DDI_IO_TC2, POWER_DOMAIN_PORT_DDI_IO_TC3, POWER_DOMAIN_PORT_DDI_IO_TC4, POWER_DOMAIN_PORT_DDI_IO_TC5, POWER_DOMAIN_PORT_DDI_IO_TC6, - POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */ + POWER_DOMAIN_PORT_DDI_IO_D_XELPD, POWER_DOMAIN_PORT_DDI_IO_E_XELPD, POWER_DOMAIN_PORT_DSI, @@ -94,18 +88,15 @@ enum intel_display_power_domain { POWER_DOMAIN_AUX_D, POWER_DOMAIN_AUX_E, POWER_DOMAIN_AUX_F, - POWER_DOMAIN_AUX_G, - POWER_DOMAIN_AUX_H, - POWER_DOMAIN_AUX_I, - POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */ + POWER_DOMAIN_AUX_USBC1, POWER_DOMAIN_AUX_USBC2, POWER_DOMAIN_AUX_USBC3, POWER_DOMAIN_AUX_USBC4, POWER_DOMAIN_AUX_USBC5, POWER_DOMAIN_AUX_USBC6, - POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */ + POWER_DOMAIN_AUX_D_XELPD, POWER_DOMAIN_AUX_E_XELPD, POWER_DOMAIN_AUX_IO_A, @@ -113,11 +104,8 @@ enum intel_display_power_domain { POWER_DOMAIN_AUX_TBT_D, POWER_DOMAIN_AUX_TBT_E, POWER_DOMAIN_AUX_TBT_F, - POWER_DOMAIN_AUX_TBT_G, - POWER_DOMAIN_AUX_TBT_H, - POWER_DOMAIN_AUX_TBT_I, - POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */ + POWER_DOMAIN_AUX_TBT1, POWER_DOMAIN_AUX_TBT2, POWER_DOMAIN_AUX_TBT3, POWER_DOMAIN_AUX_TBT4, |