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authorVille Syrjälä <ville.syrjala@linux.intel.com>2023-07-05 23:21:13 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2023-08-24 15:22:19 +0300
commit7176dca94314bada5b715611b2a54630ee68e48f (patch)
tree4bcac92e29ba12fab231a2dbe5b0322c35a5f833 /drivers/gpu/drm/i915/display/intel_dpll.c
parent469c09624b56be6ae059cd3a692b105c815a1f16 (diff)
drm/i915: Don't warn about zero N/P in *_calc_dpll_params()
Allow *_calc_dpll_params() to be called even if the N/P dividers are zero without warning. We'll want to call these to make sure the derived values are fully computed, but not all users (VLV DSI in particular) even enable the DPLL and thus the dividers will be left at zero. It could also be possible that the BIOS has misprogrammed the DPLL (IIRC happened with some SNB machines with 4k+ displays) and thus we'll currently generate a lot of dmesg spew. Better be silent and just let the normal state checker/etc. deal with any driver bugs. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230705202122.17915-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dpll.c37
1 files changed, 20 insertions, 17 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 999badfe2906..71bfeea4cef2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -314,10 +314,11 @@ int pnv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m2 + 2;
clock->p = clock->p1 * clock->p2;
- if (WARN_ON(clock->n == 0 || clock->p == 0))
- return 0;
- clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
- clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
+
+ clock->vco = clock->n == 0 ? 0 :
+ DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
+ clock->dot = clock->p == 0 ? 0 :
+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
return clock->dot;
}
@@ -331,10 +332,11 @@ int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = i9xx_dpll_compute_m(clock);
clock->p = clock->p1 * clock->p2;
- if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
- return 0;
- clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
- clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
+
+ clock->vco = clock->n + 2 == 0 ? 0 :
+ DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
+ clock->dot = clock->p == 0 ? 0 :
+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
return clock->dot;
}
@@ -343,10 +345,11 @@ int vlv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
clock->p = clock->p1 * clock->p2 * 5;
- if (WARN_ON(clock->n == 0 || clock->p == 0))
- return 0;
- clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
- clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
+
+ clock->vco = clock->n == 0 ? 0 :
+ DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
+ clock->dot = clock->p == 0 ? 0 :
+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
return clock->dot;
}
@@ -355,11 +358,11 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
clock->p = clock->p1 * clock->p2 * 5;
- if (WARN_ON(clock->n == 0 || clock->p == 0))
- return 0;
- clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
- clock->n << 22);
- clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
+
+ clock->vco = clock->n == 0 ? 0 :
+ DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
+ clock->dot = clock->p == 0 ? 0 :
+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
return clock->dot;
}