diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2019-07-11 10:31:15 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2019-07-11 16:31:27 -0700 |
| commit | a1c5f1510b3f39d57a6eaa9d75c70e5beaa952ff (patch) | |
| tree | 0519e059df7260bb9ddab4ef3b72beb87577c578 /drivers/gpu/drm/i915/display/intel_dpll_mgr.c | |
| parent | 36ca5335f202bd54faf38b37fed1b99078e1839e (diff) | |
drm/i915/tgl: Update DPLL clock reference register
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-22-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 267e6d7df706..319a26a1ec10 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2597,8 +2597,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) | DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) | DPLL_CFGCR1_KDIV(pll_params.kdiv) | - DPLL_CFGCR1_PDIV(pll_params.pdiv) | - DPLL_CFGCR1_CENTRAL_FREQ_8400; + DPLL_CFGCR1_PDIV(pll_params.pdiv); + + if (INTEL_GEN(dev_priv) >= 12) + cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; + else + cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; memset(pll_state, 0, sizeof(*pll_state)); |