diff options
| author | Jouni Högander <jouni.hogander@intel.com> | 2022-12-09 14:05:43 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-12-12 10:20:26 -0800 |
| commit | 2357f2b271adf61e47426c7e5a94de1b65a51e42 (patch) | |
| tree | 290cf29570910784e437d5e9c4f60452a55e1732 /drivers/gpu/drm/i915/display/intel_fbc.c | |
| parent | 4c0eb35fc103eb71e9b842270f449b79b1cf69b2 (diff) | |
drm/i915/mtl: Initial display workarounds
This patch introduces initial workarounds for mtl platform
v2: switch IS_MTL_DISPLAY_STEP to use IS_METEORLAKE from testing display
ver. (Tvrtko)
v3: clerical issues, extend 16015201720 to mtl. (MattR)
v4: make sure 16015201720 includes display 13. (MattR)
Bspec: 66624
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221209220543.502047-1-matthew.s.atwood@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fbc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index deba0c49c827..5e69d3c11d21 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -811,7 +811,7 @@ static void intel_fbc_program_cfb(struct intel_fbc *fbc) static void intel_fbc_program_workarounds(struct intel_fbc *fbc) { - /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp */ + /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */ if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915)) intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); @@ -1091,7 +1091,9 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, } /* Wa_14016291713 */ - if (IS_DISPLAY_VER(i915, 12, 13) && crtc_state->has_psr) { + if ((IS_DISPLAY_VER(i915, 12, 13) || + IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) && + crtc_state->has_psr) { plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; return 0; } |