diff options
| author | Jouni Högander <jouni.hogander@intel.com> | 2023-12-18 19:50:02 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2024-01-09 15:39:59 +0200 |
| commit | 3291bbb93e160e8b9b74ed0116738570f8744fe5 (patch) | |
| tree | 6c6e107e702cd38b7bc7d55e3a7ad903680ae7f2 /drivers/gpu/drm/i915/display/intel_psr.c | |
| parent | 7f85883e4a7b95559fb61cd202196ac8c8f857d7 (diff) | |
drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport
There is a new register used to configure selective update area size
for early transport.
Configure PIPE_SRCSZ_ERLY_TPT using calculated selective update area
carried in crtc_state->su_area.
Bspec: 68927
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231218175004.52875-6-jouni.hogander@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_psr.c')
0 files changed, 0 insertions, 0 deletions