diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-03-03 14:39:52 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-03-07 19:01:26 +0200 |
| commit | 68b97b12c46105b0859dd7636f3247e9f6fceab2 (patch) | |
| tree | 564805a278c5f626c1d80f721f73ede7abf6e2a9 /drivers/gpu/drm/i915/display | |
| parent | 30a6be2c200fdbdaad8adcdd68eae9d90a23c291 (diff) | |
drm/i915: Program CURSOR_PROGRAM and COEFF_POLARITY for icl+ combo PHYs
Bspec asks us to clear the CURSOR_PROGRAM and COEFF_POLARITY
bits in PORT_TX_DW5 on icl+ combo PHYs. Make it so.
Bspec: 21257, 49291
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250303123952.5669-2-ville.syrjala@linux.intel.com
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_combo_phy_regs.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h index 0964e392d02c..ee41acdccf4e 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h @@ -133,6 +133,8 @@ #define TX_TRAINING_EN REG_BIT(31) #define TAP2_DISABLE REG_BIT(30) #define TAP3_DISABLE REG_BIT(29) +#define CURSOR_PROGRAM REG_BIT(26) +#define COEFF_POLARITY REG_BIT(25) #define SCALING_MODE_SEL_MASK REG_GENMASK(20, 18) #define SCALING_MODE_SEL(x) REG_FIELD_PREP(SCALING_MODE_SEL_MASK, (x)) #define RTERM_SELECT_MASK REG_GENMASK(5, 3) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 676c1826f15c..f38c998935b9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1193,7 +1193,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, /* Set PORT_TX_DW5 */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | - TAP2_DISABLE | TAP3_DISABLE); + COEFF_POLARITY | CURSOR_PROGRAM | + TAP2_DISABLE | TAP3_DISABLE); val |= SCALING_MODE_SEL(0x2); val |= RTERM_SELECT(0x6); val |= TAP3_DISABLE; |