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| author | Ashutosh Dixit <ashutosh.dixit@intel.com> | 2022-12-15 11:17:27 -0800 |
|---|---|---|
| committer | Anshuman Gupta <anshuman.gupta@intel.com> | 2023-01-06 15:53:59 +0530 |
| commit | d2c3c8c3d3833c45c09be671da48f9d46b79e347 (patch) | |
| tree | 47c254652dcc95a1482af06005d161ea18b532c6 /drivers/gpu/drm/i915/gt/intel_engine_cs.c | |
| parent | bed4b455cf5374e68879be56971c1da563bcd90c (diff) | |
drm/i915/hwmon: Display clamped PL1 limit
HW allows arbitrary PL1 limits to be set but silently clamps these values
to "typical but not guaranteed" min/max values in pkg_power_sku
register. Follow the same pattern for sysfs, allow arbitrary PL1 limits to
be set but display clamped values when read, so that users see PL1 limits
HW is likely using. Otherwise users think HW is using arbitrarily high/low
PL1 limits they might have set. The previous write/read I1 power1_crit
limit also follows the same clamping pattern.
v2: Explain "why" in commit message and include bug link (Jani Nikula)
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7704
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221215191727.2468770-1-ashutosh.dixit@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_engine_cs.c')
0 files changed, 0 insertions, 0 deletions