diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2022-06-10 16:08:01 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-06-14 14:52:13 -0700 |
| commit | 9affc1b87ecba31458567359b5a28b0b08920a24 (patch) | |
| tree | f24ab92895f54fdf92f54330c10be8129930585c /drivers/gpu/drm/i915/gt/intel_sseu.c | |
| parent | e0d7371b46c7b47cdf5391717292033365801437 (diff) | |
drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()
If we're treating each bit in the EU fuse register as a single EU
instead of a pair of EUs, then that also cuts the number of potential
EUs per subslice in half.
Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610230801.459577-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_sseu.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 7ef75f0d9c9e..c6d3050604c8 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -229,7 +229,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt) */ intel_sseu_set_info(sseu, 1, 32 * max(num_geometry_regs, num_compute_regs), - 16); + HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16); sseu->has_xehp_dss = 1; xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, |