diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-11-15 10:21:18 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2023-11-17 12:58:14 -0800 |
| commit | 89a410b2e416f2216b29183d6b8537abeccc7abb (patch) | |
| tree | b01e8035593d5c57288aea8287e9d5ce9d8cf72f /drivers/gpu/drm/i915/gt/intel_workarounds.c | |
| parent | d3715a6471c8f0a90fb852c10a5a84948d6a1ff5 (diff) | |
drm/i915/dg2: Wa_18028616096 now applies to all DG2
The workaround database was just updated to extend this workaround to
DG2-G11 (whereas previously it applied only to G10 and G12).
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231115182117.2551522-2-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_workarounds.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 63205edfea50..9bc0654efdc0 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2937,6 +2937,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18028616096 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); } if (IS_DG2_G11(i915)) { @@ -2965,11 +2968,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li true); } - if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) { - /* Wa_18028616096 */ - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); - } - if (IS_XEHPSDV(i915)) { /* Wa_1409954639 */ wa_mcr_masked_en(wal, |