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authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>2023-03-29 18:23:36 -0300
committerMatt Roper <matthew.d.roper@intel.com>2023-03-30 12:47:27 -0700
commit9079363eda1ea0d9fa2cc5635e65821d8ed4f994 (patch)
treeb0e940ae858b433f87a02eb82e29f41cceaacb93 /drivers/gpu/drm/i915/gt/intel_workarounds.c
parent5fba65efa7cfb8cef227a2c555deb10327a5e27b (diff)
drm/i915/mtl: Add Wa_22015279794
Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive). Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-3-gustavo.sousa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_workarounds.c')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_workarounds.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f22a43d98925..642e57e6e3b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -3060,6 +3060,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
MTL_DISABLE_SAMPLER_SC_OOO);
+ if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* Wa_22015279794 */
+ wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
+ DISABLE_PREFETCH_INTO_IC);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||