diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2020-02-27 14:00:54 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-03-02 12:00:41 -0800 |
| commit | f2097beed59e8811c218222b17d2b3bfd5ce2110 (patch) | |
| tree | d087a6d6a7720b19ebeb379cf3123a8e52c12446 /drivers/gpu/drm/i915/gt/intel_workarounds.c | |
| parent | 52c2e4e6f12cb2261e6d430596d9884fd85c53df (diff) | |
drm/i915/tgl: Extend Wa_1606931601 for all steppings
According to BSpec. Wa_1606931601 applies for all TGL steppings.
This patch moves the WA implementation out of A0 only block of
rcs_engine_wa_init().
The WA is has also been referred to by an alternate name
Wa_1607090982.
Bspec: 46045, 52890
Fixes: 3873fd1a43c7 ("drm/i915: Use engine wa list for Wa_1607090982")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-4-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_workarounds.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 927cf2bc9d15..3021cc127403 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1359,11 +1359,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE); - /* Wa_1606931601:tgl */ - wa_masked_en(wal, - GEN7_ROW_CHICKEN2, - GEN12_DISABLE_EARLY_READ); - /* * Wa_1409085225:tgl * Wa_14010229206:tgl @@ -1372,6 +1367,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl */ + wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); + /* Wa_1409804808:tgl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); |