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| author | Imre Deak <imre.deak@intel.com> | 2017-07-06 17:40:36 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-27 09:38:53 +0200 |
| commit | 76347c04d879267839337adc2aea6136b58c2ca7 (patch) | |
| tree | a2f5b2d3c6f765e58884cfa7bf45035fc37ae7a4 /drivers/gpu/drm/i915/gvt/display.c | |
| parent | 001bd2cb17f7df768fb3a5c1e7c3d2cd2cfb3439 (diff) | |
drm/i915/hsw, bdw: Wait for the power well disabled state
Similarly to GEN9+ waiting for the power well disabled state is a safer
option and also provides diagnostic info if the disabling didn't succeed
or the power well was forced on by an external requester. While at it
also use the existing GEN9+ helper to wait for the enabled state.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-15-git-send-email-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/display.c')
0 files changed, 0 insertions, 0 deletions