diff options
| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-04-08 18:43:56 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-04-18 09:43:16 +0200 |
| commit | b7c36d25461ae41e6562a2f70cb3423bcf8af2d2 (patch) | |
| tree | 6b6a9bb0d909fb2ee7c90bdb79aa1b316ddc69ed /drivers/gpu/drm/i915/i915_gem_gtt.c | |
| parent | 5963cf049a044f41be7dc90c83756fb245f038b4 (diff) | |
drm/i915: Allow PPGTT enable to fail
I'm really not happy that we have to support this, but this will be the
simplest way to handle cases where PPGTT init can fail, which I promise
will be coming in the future.
v2: Resolve conflicts due to patch series reordering.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index d32912e07bad..11143b4982fc 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -75,7 +75,7 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, return pte; } -static void gen6_ppgtt_enable(struct drm_device *dev) +static int gen6_ppgtt_enable(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; uint32_t pd_offset; @@ -128,6 +128,7 @@ static void gen6_ppgtt_enable(struct drm_device *dev) I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); } + return 0; } /* PPGTT support for Sandybdrige/Gen6 and later */ |