diff options
author | Ashutosh Dixit <ashutosh.dixit@intel.com> | 2022-12-02 19:14:54 -0800 |
---|---|---|
committer | Anshuman Gupta <anshuman.gupta@intel.com> | 2022-12-07 10:25:09 +0530 |
commit | 3d0f98fa66bc459d0ba516d1d46a0b22e3005244 (patch) | |
tree | d2c05f5a5d6238a5645435d1454720123ce11c48 /drivers/gpu/drm/i915/i915_hwmon.c | |
parent | de3a9ab97069488b23427726e86b8628f4fe278e (diff) |
drm/i915/hwmon: Silence "mailbox access failed" warning in snb_pcode_read
hwm_pcode_read_i1 is called during i915 load. This results in the following
warning from snb_pcode_read because POWER_SETUP_SUBCOMMAND_READ_I1 is
unsupported on DG1/DG2.
[drm:snb_pcode_read [i915]] warning: pcode (read from mbox 47c) \
mailbox access failed for snb_pcode_read_p [i915]: -6
The code handles the unsupported command but the warning in dmesg is
a red herring which has resulted in a couple of bugs being filed.
Therefore silence the warning by avoiding calling snb_pcode_read_p
for DG1/DG2.
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221203031454.1280538-1-ashutosh.dixit@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_hwmon.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_hwmon.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index c588a17f97e9..cca7a4350ec8 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -293,6 +293,10 @@ static const struct hwmon_channel_info *hwm_gt_info[] = { /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval) { + /* Avoid ILLEGAL_SUBCOMMAND "mailbox access failed" warning in snb_pcode_read */ + if (IS_DG1(i915) || IS_DG2(i915)) + return -ENXIO; + return snb_pcode_read_p(&i915->uncore, PCODE_POWER_SETUP, POWER_SETUP_SUBCOMMAND_READ_I1, 0, uval); } |