diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-08-17 15:26:24 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2022-08-19 12:38:54 +0300 |
| commit | 4cf05a4d7125854800a0e88eb3e1dbd74368e9af (patch) | |
| tree | 5f2677d7b03922364ef997cdc99a8cde3c0784ef /drivers/gpu/drm/i915/i915_pci.c | |
| parent | f386832509b85e567acc849cdef22843ed33a525 (diff) | |
drm/i915/mtl: Introduce FBC B
MTL introduces a second FBC engine. The two FBC engines can
operate entirely independently, FBC A serving pipe A and
FBC B serving pipe B.
The one place where things might go a bit wrong is the CFB
allocation from stolen. We might have to consider some change
to the allocation strategy to have a better chance of both
engines being able to allocate its CFB. Maybe FBC A should
allocate bottom up and FBC B top down, or something? For the
moment the allocation strategy is DRM_MM_INSERT_BEST for both.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220817122624.213889-1-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 9fd788e147a3..d8446bb25d5e 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1111,7 +1111,8 @@ static const struct intel_device_info pvc_info = { #define XE_LPDP_FEATURES \ XE_LPD_FEATURES, \ .display.ver = 14, \ - .display.has_cdclk_crawl = 1 + .display.has_cdclk_crawl = 1, \ + .display.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) __maybe_unused static const struct intel_device_info mtl_info = { |