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| author | Badal Nilawar <badal.nilawar@intel.com> | 2022-11-14 18:03:46 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2022-11-17 10:46:37 -0500 |
| commit | 22009b6dad6621893e9b5c14665f247b6162499c (patch) | |
| tree | 18c231fc38f2291222346c3ab6fc833d22c89357 /drivers/gpu/drm/i915/i915_pmu.c | |
| parent | 01b8c2e60e96ce8a30d23683fba56b478be7287c (diff) | |
drm/i915/mtl: Modify CAGF functions for MTL
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing forcewake for Gen12+ and
returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)
Bspec: 66300
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221114123348.3474216-4-badal.nilawar@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pmu.c')
0 files changed, 0 insertions, 0 deletions