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authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>2022-08-18 16:41:55 -0700
committerRadhakrishna Sripada <radhakrishna.sripada@intel.com>2022-08-25 14:53:54 -0700
commitc41aa0204d1c05edadc42e50fdba62784f5841bd (patch)
treee0925cfa8c5226e128c0e1b81b17a202b822d84a /drivers/gpu/drm/i915/i915_reg.h
parenta2b4cefafa26e6e4dc550366b2caa87a916c179a (diff)
drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM
Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers instead of GT driver mailbox. v2: Use the extracted wm latency adjustment function(Matt) v3: Use Odd/even for Latency fields(MattR) Bspec: 64608 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/<20220818234202.451742-15-radhakrishna.sripada@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f140c26d79f..f60dda8702e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8355,4 +8355,10 @@ enum skl_power_gate {
#define GEN12_CULLBIT2 _MMIO(0x7030)
#define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC)
+#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
+#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
+#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
+#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
+#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
+
#endif /* _I915_REG_H_ */