diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-07-03 23:08:22 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-07-05 13:14:05 +0300 |
| commit | d56e823ac32a793b24c857e8635def13d42b4008 (patch) | |
| tree | 3b1f8748037ad17a9fa527e7a231692a3e098bbb /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 94e15723df815497347408631203b2dabcb0bca3 (diff) | |
drm/i915: Deal with cpp==8 for g4x watermarks
Docs tell us that on g4x we have to compute the SR watermarks
using 4 bytes per pixel. I'm going to assume that only applies
to 1 and 2 byte per pixel formats, and not 8 byte per pixel
formats. That seems like a recipe for an insufficient watermark
which could lead to underruns. Use the maximum of the two numbers
instead.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190703200824.5971-5-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d10c62d3f10c..87244d8215a7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1116,6 +1116,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, if (!intel_wm_plane_visible(crtc_state, plane_state)) return 0; + cpp = plane_state->base.fb->format->cpp[0]; + /* * Not 100% sure which way ELK should go here as the * spec only says CL/CTG should assume 32bpp and BW @@ -1129,9 +1131,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, */ if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY && level != G4X_WM_LEVEL_NORMAL) - cpp = 4; - else - cpp = plane_state->base.fb->format->cpp[0]; + cpp = max(cpp, 4u); clock = adjusted_mode->crtc_clock; htotal = adjusted_mode->crtc_htotal; |