diff options
| author | Matt Coster <matt.coster@imgtec.com> | 2025-04-10 10:55:07 +0100 |
|---|---|---|
| committer | Matt Coster <matt.coster@imgtec.com> | 2025-04-15 12:21:51 +0100 |
| commit | 2c08b72598cc15eafbf5c9c3870e5c29e21f4827 (patch) | |
| tree | d5a9e2f0698506104dbc640e0be49f9321487f7f /drivers/gpu/drm/imagination/pvr_fw_meta.c | |
| parent | 96822d38ff574433e06a2ec0f88ebc50d44c8eaa (diff) | |
drm/imagination: Remove firmware enable_reg
After a previous commit ("drm/imagination: Mask GPU IRQs in threaded
handler"), this register is now only used to enable firmware interrupts at
start-of-day. This is, however, unnecessary since they are enabled by
default.
In addition, the soon-to-be-added RISC-V firmware processors do not have
an equivalent register.
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-8-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Diffstat (limited to 'drivers/gpu/drm/imagination/pvr_fw_meta.c')
| -rw-r--r-- | drivers/gpu/drm/imagination/pvr_fw_meta.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c index c7cfdd60116d..77596a2a6c4e 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -547,7 +547,6 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { .wrapper_init = pvr_meta_wrapper_init, .has_fixed_data_addr = pvr_meta_has_fixed_data_addr, .irq = { - .enable_reg = ROGUE_CR_META_SP_MSLVIRQENABLE, .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .event_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, |