diff options
author | Stephen Boyd <swboyd@chromium.org> | 2020-09-09 17:49:02 -0700 |
---|---|---|
committer | Rob Clark <robdclark@chromium.org> | 2020-09-15 10:54:35 -0700 |
commit | 937f941ca06f2f3ab64baebf31be2c16d57ae7b8 (patch) | |
tree | 3e1729d78c6584d60f47280bdec910af16ff9ce5 /drivers/gpu/drm/msm/dp/dp_parser.h | |
parent | ab205927592be25ddef5db10344925b389fd4344 (diff) |
drm/msm/dp: Use qmp phy for DP PLL and PHY
Make the necessary changes to the DP driver to use the qmp phy from the
common phy framework instead of rolling our own in the drm subsystem.
This also removes the PLL code and adds proper includes so things build.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dp/dp_parser.h')
-rw-r--r-- | drivers/gpu/drm/msm/dp/dp_parser.h | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 841e776124c4..34b49628bbaf 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -7,10 +7,11 @@ #define _DP_PARSER_H_ #include <linux/platform_device.h> +#include <linux/phy/phy.h> +#include <linux/phy/phy-dp.h> #include "dpu_io_util.h" #include "msm_drv.h" -#include "dp_pll.h" #define DP_LABEL "MDSS DP DISPLAY" #define DP_MAX_PIXEL_CLK_KHZ 675000 @@ -62,15 +63,11 @@ struct dp_display_data { * * @dp_controller: Display Port controller mapped memory address * @phy_io: phy's mapped memory address - * @ln_tx0_io: USB-DP lane TX0's mapped memory address - * @ln_tx1_io: USB-DP lane TX1's mapped memory address - * @dp_pll_io: DP PLL mapped memory address - * @usb3_dp_com: USB3 DP PHY combo mapped memory address */ struct dp_io { struct dss_io_data dp_controller; - struct dss_io_data phy_reg; - struct dss_io_data usb3_dp_com; + struct phy *phy; + union phy_configure_opts phy_opts; }; /** @@ -117,7 +114,6 @@ struct dp_parser { struct dp_pinctrl pinctrl; struct dp_io io; struct dp_display_data disp_data; - struct msm_dp_pll *pll; const struct dp_regulator_cfg *regulator_cfg; u32 max_dp_lanes; |