drm/msm/dp: add support for DP PLL driver

Add the needed DP PLL specific files to support
display port interface on msm targets.

The DP driver calls the DP PLL driver registration.
The DP driver sets the link and pixel clock sources.

Changes in v2:
-- Update copyright markings on all relevant files.
-- Use DRM_DEBUG_DP for debug msgs.

Changes in v4:
-- Update the DP link clock provider names

Changes in V5:
-- Addressed comments from Stephen Boyd, Rob clark.

Changes in V6:
-- Remove PLL as separate driver and include PLL as DP module
-- Remove redundant clock parsing from PLL module and make DP as
   clock provider
-- Map USB3 DPCOM and PHY IO using hardcoded register address and
   move mapping form parser to PLL module
-- Access DP PHY modules from same base address using offsets instead of
   deriving base address of individual module from device tree.
-- Remove dp_pll_10nm_util.c and include its functionality in
   dp_pll_10nm.c
-- Introduce new data structures private to PLL module

Changes in v7:

-- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig
-- Remove set_parent from determin_rate API
-- Remove phy_pll_vco_div_clk from parent list
-- Remove flag CLK_DIVIDER_ONE_BASED
-- Remove redundant cell-index property parsing

Changes in v8:

-- Unregister hardware clocks during driver cleanup

Changes in v9:

-- Remove redundant Kconfig option DRM_MSM_DP_10NM_PLL

Changes in v10:

-- Limit 10nm PLL function scope

Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

1 files changed, 16 insertions, 0 deletions

diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 67a2d040b221..893fc3250c3e 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -6,6 +6,22 @@
 #ifndef _DP_REG_H_
 #define _DP_REG_H_
 
+/* DP PHY Register Regions */
+#define REG_DP_PHY_REGION_BASE			(0x088ea000)
+#define REG_DP_PHY_REGION_SIZE			(0x00000C00)
+
+#define REG_USB3_DP_COM_REGION_BASE		(0x088e8000)
+#define REG_USB3_DP_COM_REGION_SIZE		(0x00000020)
+
+#define DP_PHY_PLL_OFFSET			(0x00000000)
+#define DP_PHY_PLL_SIZE				(0x00000200)
+#define DP_PHY_REG_OFFSET			(0x00000A00)
+#define DP_PHY_REG_SIZE				(0x00000200)
+#define DP_PHY_LN_TX0_OFFSET			(0x00000200)
+#define DP_PHY_LN_TX0_SIZE			(0x00000200)
+#define DP_PHY_LN_TX1_OFFSET			(0x00000600)
+#define DP_PHY_LN_TX1_SIZE			(0x00000200)
+
 /* DP_TX Registers */
 #define REG_DP_HW_VERSION			(0x00000000)