Merge tag 'drm-next-2020-08-06' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "New xilinx displayport driver, AMD support for two new GPUs (more
  header files), i915 initial support for RocketLake and some work on
  their DG1 (discrete chip).

  The core also grew some lockdep annotations to try and constrain what
  drivers do with dma-fences, and added some documentation on why the
  idea of indefinite fences doesn't work.

  The long list is below.

  I do have some fixes trees outstanding, but I'll follow up with those
  later.

  core:
   - add user def flag to cmd line modes
   - dma_fence_wait added might_sleep
   - dma-fence lockdep annotations
   - indefinite fences are bad documentation
   - gem CMA functions used in more drivers
   - struct mutex removal
   - more drm_ debug macro usage
   - set/drop master api fixes
   - fix for drm/mm hole size comparison
   - drm/mm remove invalid entry optimization
   - optimise drm/mm hole handling
   - VRR debugfs added
   - uncompressed AFBC modifier support
   - multiple display id blocks in EDID
   - multiple driver sg handling fixes
   - __drm_atomic_helper_crtc_reset in all drivers
   - managed vram helpers

  ttm:
   - ttm_mem_reg handling cleanup
   - remove bo offset field
   - drop CMA memtype flag
   - drop mappable flag

  xilinx:
   - New Xilinx ZynqMP DisplayPort Subsystem driver

  nouveau:
   - add CRC support
   - start using NVIDIA published class header files
   - convert all push buffer emission to new macros
   - Proper push buffer space management for EVO/NVD channels.
   - firmware loading fixes
   - 2MiB system memory pages support on Pascal and newer

  vkms:
   - larger cursor support

  i915:
   - Rocketlake platform enablement
   - Early DG1 enablement
   - Numerous GEM refactorings
   - DP MST fixes
   - FBC, PSR, Cursor, Color, Gamma fixes
   - TGL, RKL, EHL workaround updates
   - TGL 8K display support fixes
   - SDVO/HDMI/DVI fixes

  amdgpu:
   - Initial support for Sienna Cichlid GPU
   - Initial support for Navy Flounder GPU
   - SI UVD/VCE support
   - expose rotation property
   - Add support for unique id on Arcturus
   - Enable runtime PM on vega10 boards that support BACO
   - Skip BAR resizing if the bios already did id
   - Major swSMU code cleanup
   - Fixes for DCN bandwidth calculations

  amdkfd:
   - Track SDMA usage per process
   - SMI events interface

  radeon:
   - Default to on chip GART for AGP boards on all arches
   - Runtime PM reference count fixes

  msm:
   - headers regenerated causing churn
   - a650/a640 display and GPU enablement
   - dpu dither support for 6bpc panels
   - dpu cursor fix
   - dsi/mdp5 enablement for sdm630/sdm636/sdm66

  tegra:
   - video capture prep support
   - reflection support

  mediatek:
   - convert mtk_dsi to bridge API

  meson:
   - FBC support

  sun4i:
   - iommu support

  rockchip:
   - register locking fix
   - per-pixel alpha support PX30 VOP

  mgag200:
   - ported to simple and shmem helpers
   - device init cleanups
   - use managed pci functions
   - dropped hw cursor support

  ast:
   - use managed pci functions
   - use managed VRAM helpers
   - rework cursor support

  malidp:
   - dev_groups support

  hibmc:
   - refactor hibmc_drv_vdac:

  vc4:
   - create TXP CRTC

  imx:
   - error path fixes and cleanups

  etnaviv:
   - clock handling and error handling cleanups
   - use pin_user_pages"

* tag 'drm-next-2020-08-06' of git://anongit.freedesktop.org/drm/drm: (1747 commits)
  drm/msm: use kthread_create_worker instead of kthread_run
  drm/msm/mdp5: Add MDP5 configuration for SDM636/660
  drm/msm/dsi: Add DSI configuration for SDM660
  drm/msm/mdp5: Add MDP5 configuration for SDM630
  drm/msm/dsi: Add phy configuration for SDM630/636/660
  drm/msm/a6xx: add A640/A650 hwcg
  drm/msm/a6xx: hwcg tables in gpulist
  drm/msm/dpu: add SM8250 to hw catalog
  drm/msm/dpu: add SM8150 to hw catalog
  drm/msm/dpu: intf timing path for displayport
  drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3
  drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845
  drm/msm/dpu: move some sspp caps to dpu_caps
  drm/msm/dpu: update UBWC config for sm8150 and sm8250
  drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250
  drm/msm/a6xx: set ubwc config for A640 and A650
  drm/msm/adreno: un-open-code some packets
  drm/msm: sync generated headers
  drm/msm/a6xx: add build_bw_table for A640/A650
  drm/msm/a6xx: fix crashstate capture for A650
  ...

1 files changed, 153 insertions, 0 deletions

diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h
new file mode 100644
index 000000000000..5b2ca337cf2b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_nv50_memory_to_memory_format_h_
+#define _cl_nv50_memory_to_memory_format_h_
+
+#define NV5039_SET_OBJECT                                                                                  0x0000
+#define NV5039_SET_OBJECT_POINTER                                                                            15:0
+
+#define NV5039_NO_OPERATION                                                                                0x0100
+#define NV5039_NO_OPERATION_V                                                                                31:0
+
+#define NV5039_SET_CONTEXT_DMA_NOTIFY                                                                      0x0180
+#define NV5039_SET_CONTEXT_DMA_NOTIFY_HANDLE                                                                 31:0
+
+#define NV5039_SET_CONTEXT_DMA_BUFFER_IN                                                                   0x0184
+#define NV5039_SET_CONTEXT_DMA_BUFFER_IN_HANDLE                                                              31:0
+
+#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT                                                                  0x0188
+#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE                                                             31:0
+
+#define NV5039_SET_SRC_MEMORY_LAYOUT                                                                       0x0200
+#define NV5039_SET_SRC_MEMORY_LAYOUT_V                                                                        0:0
+#define NV5039_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR                                                     0x00000000
+#define NV5039_SET_SRC_MEMORY_LAYOUT_V_PITCH                                                           0x00000001
+
+#define NV5039_SET_SRC_BLOCK_SIZE                                                                          0x0204
+#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NV5039_SET_SRC_WIDTH                                                                               0x0208
+#define NV5039_SET_SRC_WIDTH_V                                                                               31:0
+
+#define NV5039_SET_SRC_HEIGHT                                                                              0x020c
+#define NV5039_SET_SRC_HEIGHT_V                                                                              31:0
+
+#define NV5039_SET_SRC_DEPTH                                                                               0x0210
+#define NV5039_SET_SRC_DEPTH_V                                                                               31:0
+
+#define NV5039_SET_SRC_LAYER                                                                               0x0214
+#define NV5039_SET_SRC_LAYER_V                                                                               31:0
+
+#define NV5039_SET_SRC_ORIGIN                                                                              0x0218
+#define NV5039_SET_SRC_ORIGIN_X                                                                              15:0
+#define NV5039_SET_SRC_ORIGIN_Y                                                                             31:16
+
+#define NV5039_SET_DST_MEMORY_LAYOUT                                                                       0x021c
+#define NV5039_SET_DST_MEMORY_LAYOUT_V                                                                        0:0
+#define NV5039_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR                                                     0x00000000
+#define NV5039_SET_DST_MEMORY_LAYOUT_V_PITCH                                                           0x00000001
+
+#define NV5039_SET_DST_BLOCK_SIZE                                                                          0x0220
+#define NV5039_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NV5039_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NV5039_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NV5039_SET_DST_WIDTH                                                                               0x0224
+#define NV5039_SET_DST_WIDTH_V                                                                               31:0
+
+#define NV5039_SET_DST_HEIGHT                                                                              0x0228
+#define NV5039_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NV5039_SET_DST_DEPTH                                                                               0x022c
+#define NV5039_SET_DST_DEPTH_V                                                                               31:0
+
+#define NV5039_SET_DST_LAYER                                                                               0x0230
+#define NV5039_SET_DST_LAYER_V                                                                               31:0
+
+#define NV5039_SET_DST_ORIGIN                                                                              0x0234
+#define NV5039_SET_DST_ORIGIN_X                                                                              15:0
+#define NV5039_SET_DST_ORIGIN_Y                                                                             31:16
+
+#define NV5039_OFFSET_IN_UPPER                                                                             0x0238
+#define NV5039_OFFSET_IN_UPPER_VALUE                                                                          7:0
+
+#define NV5039_OFFSET_OUT_UPPER                                                                            0x023c
+#define NV5039_OFFSET_OUT_UPPER_VALUE                                                                         7:0
+
+#define NV5039_OFFSET_IN                                                                                   0x030c
+#define NV5039_OFFSET_IN_VALUE                                                                               31:0
+
+#define NV5039_OFFSET_OUT                                                                                  0x0310
+#define NV5039_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NV5039_PITCH_IN                                                                                    0x0314
+#define NV5039_PITCH_IN_VALUE                                                                                31:0
+
+#define NV5039_PITCH_OUT                                                                                   0x0318
+#define NV5039_PITCH_OUT_VALUE                                                                               31:0
+
+#define NV5039_LINE_LENGTH_IN                                                                              0x031c
+#define NV5039_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NV5039_LINE_COUNT                                                                                  0x0320
+#define NV5039_LINE_COUNT_VALUE                                                                              31:0
+
+#define NV5039_FORMAT                                                                                      0x0324
+#define NV5039_FORMAT_IN                                                                                      7:0
+#define NV5039_FORMAT_IN_ONE                                                                           0x00000001
+#define NV5039_FORMAT_OUT                                                                                    15:8
+#define NV5039_FORMAT_OUT_ONE                                                                          0x00000001
+
+#define NV5039_BUFFER_NOTIFY                                                                               0x0328
+#define NV5039_BUFFER_NOTIFY_TYPE                                                                            31:0
+#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_ONLY                                                           0x00000000
+#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                    0x00000001
+#endif /* _cl_nv50_memory_to_memory_format_h_ */